© 2007 IBM Corporation

Step-and-FlashImprint Lithography forStorage-Class Memory

Mark W. HartAlmaden Research Center

San Jose, California

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Acknowledgements

ALMADENGian-Luca BonaSpike NarayanBulent KurdiCarl Larson

Rohit ShenoyKailash Gopalakrishnan

Ron JihCharles Rettner

Philip RiceEugene Delenia

Leslie KruppTeya Topuria

Martha SanchezJane Frommer

WATSONT.C. Chen

Mary-Beth RothwellEdmund Sikorski

Ying ZhangALBANY

John GaudielloJennifer Fullam

Mark Melliar-SmithS.V. SreenivassanDwayne LaBrakeDouglas Resnick

Niyaz KhusnatdinovCindy Brooks

Gerard SchmidtEcron Thompson

John MaltabesScott Balaguer

Mike Stubelt

Tony DiBiasePedro Herrera

Jim MankaShawn MacNish

Randy GoodallWalt Trybula

Naoya HayashiYasutaka Morikawa

Shiho SasakiMasa-Aki KuriharaNobuhito Toyama

Hideo KobayashiTakashi Sato

Osamu Nagarekawa

Nety KrishnaRobin Cheung

Ajay KumarMadhavi Chandrachood

Eva GabrielLuke ThomasMichael Lin

Dan Radack

Jordan OwensTony VanderHeyden

Jeff WetzelDoug GuentherGabe GebaraKen Sotoodah

Rene DiazArnie Ford

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What is Storage Class Memory (SCM) and Why?

Solid-State, Non-Volatile Memory to Enable >100X Performance Increase of Large Scale Data Centers

Hard-Disk Drive (HDD) and Flash Technologies Will Not Scale for the Needs of High-Performance Computing (HPC) Systems

Paradigm Shift in HPC Applications Requires Even More HDD’s

COMPUTE-CENTRICIntegrating Differential Equations

CPU and Memory

Finite Element AnalysisFluid Dynamics

Multi-Body Simulations

DATA-CENTRICAnalyze Petabytes of Data

Storage and Input/Output

Network Processing and AnalysisSearch and Data Mining

Analysis of Large Scientific Experiments

FOCUS

BOTTLENECK

EXAMPLES

To Meet Bandwidth Requirement of Conventional Balanced HPC System

2005: ~10,000 HDD’s Required2020: >500,000 HDD’s Required

Projected HDD Reliability, Power, and Space ConsumptionMakes Using These Large Numbers of HDD’s Untenable

-- EXAMPLE --

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Need Effective Cell Size < 4Fo2 (Fo Optical-Litho Half-Pitch)

Storage Class Memory REQUIRES High Density

2D Better Scaling & Fewer Process Steps, but Requires:● Interface Between Optical-Litho (Fo) and Sub-Litho (Fs)● Viable Method to Manufacture Sub-Lithographic NCA’s

3D Optical-LithoCrosspoint Memory

4Fo2 / (# of Layers)

2D Sub-LithoCrosspoint Memory

4Fo2 / (# of Nodes)2

Fo

Fs

Blocks of Nanoscale Crossbar

Arrays (NCA)

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Interfacing Optical-Litho (Fo) to Sub-Litho (Fs)

Fo

Fs

Sub-LithoLine

Optical-Litho Pad

MNAB

MN

AB

Nanoscale Crossbar Array (NCA)

Uniquely Address Individual Sub-Litho (Nano) Lines from

an Optical-Litho (Micro) Contact Pad

Micro-to-NanoAddressing Block (MNAB)

K. Gopalakrishnan et al, IEDM Tech. Dig., 2005, pp. 471-474R.S. Shenoy et al, Proc. Symp. VLSI Technology, June 2006, pp. 140-141

● Exploits the Fact that Optical-Litho Tool Alignment can be Much Less than the Minimum Available Optical-Litho Pitch

● Concept is Independent of Memory Node Details

● Permits Accessing the Nanoscale with both Optical Lithographyand Fab Technology from Nodes that are 2 to 3 Generations Old

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F 30 F F F F F F

80 nm

40 nm 80 nm

160 nm

130 nm210 nm

F 30 F F F F F F

80 nm

40 nm 80 nm

160 nm

130 nm210 nm

NCAN(Right Edge)

NCAN+1(Left Edge)

Stagger Alternate Linesat NCA Array Boundaryto Give Lines at Twice

the Sub-Litho Pitch

Contact to CMOS Poly Gate

Optical-Litho Defined Implant Mask (N-Select Shown)

High, but Feasible Overlay Required (15nm)

MNAB Concept - 10nm Half-Pitch NCA’s (~Tb/cm2)6

MNAB Selection Scheme & 3D View

F 30 F F F F F F

80 nm

40 nm 80 nm

160 nm

130 nm210 nm

F 30 F F F F F F

80 nm

40 nm 80 nm

160 nm

130 nm210 nm

G1 G2

G1 G2

Four Permutations of a Series NMOS and PMOSPass-Transistor Uniquely

Connect One of Four Nanoscale Lines

to Common Contact

Intersection of MNABSelect Gates and Lines Results in 3D FinFET

StructureTo Crossbar Array (NCA)

Contact to M1

SilicidedNano-Fin

MNAB Select Gates

Polycid

e

Polycid

e

Poly TEOS/Nitride Spacer

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MNAB Concept Demonstrated via E-Beam Lithography andis Compatible with Phase-Change Memory Node Materials

50nm Half-Pitch MNAB Test Structure

Gate1 = -2.0V

Selectivity> 105 MNAB Can Drive mA/μm and

Can Therefore Reset and ReadPhase Change Materials

Phase Change Materials Demonstrated to Scale Down

to SCM-Required Volumes

3nm x 20nm Phase-ChangeBridge Memory Cell

20nmIBM, Macronix, Qimonda(IEDM, December 2006)

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Storage Class Memory (SCM) Requires Manufacturing10nm Lines on 20nm Pitch within 5-7 Years at Low-Cost

Consider Step-and-Flash Imprint Lithography (SFIL)● High Resolution and Acceptable Overlay

● Memory is More “Nano” Defect Tolerant than Logic● Plausibly Cost Effective

“Sub-Lithography” via Imprint Lithography

Align, Print, and EtchSFIL Pattern to Form

an Oxide Hard-Mask forSilicon Fin Formation

Patterned Oxide Etch Mask

“Zero-Level” Alignment Mark

Silicon

Buried OxideSilicon

Initial SFIL Evaluation Use to Build MNAB Devices

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Step-and-Flash Imprint Lithography (SFIL)

Imprint Fluid Dispenser

Planarization and/or Adhesion LayerSubstrate

Low Viscosity MonomerStep 1: Dispense Drops

Step 2: Lower Template, Fill Pattern, Perform Alignment

Step 3: Polymerize Imprint Fluid with UV Exposure

Step 4: Separate Template From Substrate

Template

Step & Repeat

Rigid Fused-Silica Template

Very Low Imprint Pressure ( < 1/20 Atm at RT )

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Resist AppliedOver 10-15 nm Cr

Expose/DevelopE-Beam Resist

Etch Chrome,Strip Resist

Etch Quartz,Strip Chrome

6025 QuartzCr

Resist

SFIL Template Fabrication

6025 Photomask(with 4 Patterned Templates)

After Dice(4 Templates & Discarded Glass)

Pattern 15μm Mesa

65mm

25mm

6mm

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Use SFIL to Form Thermal-Oxide Hard Mask to Form Silicon Fins

SFIL Direct● Need Feature Recessed Template● Positive-Tone E-Beam Resist

Allows Fabrication in CommercialTemplate Houses (Hoya or DNP)

● Exceptional Imprint Quality andDemanding Etch Process Required

TOx

SiBOxSi

Template

Organic

SFIL Reverse● Need Feature Proud Template

● Provides Larger Process Window for Both Imprint and Etch

● More Process Steps

● Negative-Tone E-Beam Resist are Currently More Problematic and were Not Available in Commercial Template Houses (Hoya or DNP)

Si

TOx

Template

BOxSi

Si-Organic

Organic

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CD and Overlay Metrology, Defect

Inspection

Direct-ToneTemplate

Production

Direct-ToneTemplate

Production

State-of-the-Art NanoimprintTechnology and Template

Development

193nm Lithography, Ion Implantation, CD Metrology, and Direct-Tone Imprint Etch Development, Funded Through DARPA

Reverse-Tone Template and Reverse-Tone Imprint Etch

Development

SCM and MNAB Device ConceptCMOS Processing at MRL

Reverse-Tone Template E-BeamLithography, TEM, SEM, AFM

Engage in Multi-Organization Effort to Integrate SFIL with Conventional 200mm CMOS Processes to Produce Working MNAB Devices

with 20-30nm Fin-Widths on an 80-120nm Pitch(7 Mask Steps 3 at 193nm and 4 at 248nm)

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Integrate SFIL into CMOS Process

193nm Implant Lithography,Measure Alignment, Implant

Gate Stack Definitionand Spacer Formation

Silicidation, Back-End Metallization, and

Electrical Test

Oxide / Imprint Etch Silicon / Oxide Etch

Zero-Level Formation193nm Lithography and Etch

TemplateDevelopment

Imprint and Measure Alignment to Zero-Level

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Base Pattern of 4-Fin MNAB StructureFeature-Recessed in Fused-Silica

30nm Lines / 120nm Pitch

80nm Etch Depth

Side-Wall Angle ~880

SFIL Template Development15

SFIL Printing of MNAB Base Structure

80nm

BOX

Si - 50nm

SiO2 - 20nm

30nm

BOx

Si - 50nm

SiO2 - 20nm

RLT15nmRLT

15nmRLT

15nm

Imprinting Features Downto 30nm Wide and 75-80nm Tall

Achieving 15nm (Mean+3σ)Residual Layer Thickness (RLT)

Over Full 200mm Wafers

Imprint Produced on Molecular Imprints Imprio 250

from Hoya 30nm/120nmFeature-Recessed Template

Creates the Most ChallengingScenario for Imprinting and

Subsequent Pattern Transfer

SFIL Direct Process Required

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Silicon Fin Definition After Imprint and Oxide EtchMetrology Analysis of SFIL Process

BOx

Si

Ox

30nm

Imprint Etched Through Oxide and Silicon-on-Insulator

1 2 31 2 3

Examined LWR, LER, and CD UniformityFrom Template to Imprint to Etch

Using Templates from HOYA and DNP

LWR = 2.4nm, 3σLER = 2.2nm, 3σCD Variation = 1.6nm, 3σ

30nmImprintedFeatures

► Imprint Adds No Measurable LWR to Template LWR ► Our Etch Process Appears to Add ~10% LWR

to Imprint LWR and ~5% Radial CD Variation

► ITRS Guidelines Say LWR <8% of CD

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Mix-and-Match Overlay of SFILto 193nm Optical Lithography

Imprio 250 and 193nm ASML Mix-and-Match Overlay Results~2350 In-Chip KT Moiré Targets/Wafer, 100nm “Flyer” Clamp*

HOYA 30/120nm ImprintsXAVE = 18.5nm / σx = 12.4nm YAVE = 19.2nm / σY = 14.0nm

DNP 26/80nm ImprintsXAVE = 14.1nm / σx = 11.0nmYAVE = 21.4nm / σY = 18.6nm

Generate “Zero-Level” Marks in Wafer via 193nm Lithography and Etch to Ensure

they Survive the Full MNAB Process Build

Align both Imprint Level and Subsequent Optical Levels to These Zero-Level Marks

Zero-Level Mark Etched Through SOI

Good Incomplete Fill Pull-Out Noisy

Target Measurement Failures

~1.2% Extreme Values “Flyer”*

~2.4% No Measurement

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1930nm/120nm MNAB Device Build - Summary and Status

-- Summary --● Features Successfully Imprinted with Uniform 15nm Residual Layer

● Achieved ~20nm Overlay Imprint-to-193nm-Lithography Zero-Level● Imprint-to-Oxide Pattern Transfer Successfully Developed and Demonstrated

● N- and P-Type 193nm Ion-Implant with Alignment Successfully Completed,Achieved ~25nm Overlay Between N and P Implant Levels and Imprint Level

● Zero-Level, Imprint, and 180 MRL Pre-Implant Process Steps Complete

-- Status --

● Full Device Wafers are at Last Block of the Process Flow

● Split Two Wafers from Lot, Blanket Implant Each Wafer, One N-Doped, One P-Doped, Completed Build, andPerformed Electrical Tests

30nm N-Type FinFET Device Data Resulting from Blanket Implantation

-- Initial Results --

● Obtain Expected Turn-On Voltage

● No Forming Gas Anneal

● On-Off Ratio > 100

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From 30/120nm To 20/80nmMNAB Structures

Etch Depth = 58nm

Template Test Structure

Line Width26nm

Pitch80nm

Imprinted MNAB Structure

Imprint Etched Through SOI

Oxide

Si

● Successful SFIL-Direct Processwith Shorter Imprinted Features

● Etch Times Need to be Tweaked to Further Minimize LWR

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SFIL Reverse Etch Process Developmentand Feature-Proud Template Fabrication

Feature-Proud Template

120nm

Developed / RefinedO2 / N2 / H2 - Based Etch Process to Breakthrough

Si-Organic PlanarizingLayer and Remove

Organic Imprinted Features

SFIL Reverse

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Closing Points

MNAB Permits Accessing the Nanoscale with both Optical Lithography and Fab Technology from Nodes 2 to 3 Generations Old

SCM is a “Pull” Application for SFIL that Could Leadto Its Larger Role in Semiconductor Manufacturing

SFIL is a Potentially Executable Option that Permits Scaling toSub-20nm and Avoid the High Cost of Sub-45nm Optical Lithography

MNAB + SFIL Enables the Low-Cost, High DensityNon-Volatile Memory Roadmap to Continue

Storage Class Memory (SCM) is Required for the ContinuedScaling of High-Performance Computing and the Growing

Importance of “Data-Centric” Applications

Cost is a Critical Issue for the Timely Emergence of SCM,and Lithography Cost is a Major Threat to 2D SCM Scaling

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