16 www.rfdesign.com June 1999

The step recovery diode (SRD) oper-ates in one of two states. The state

is determined by the presence or ab-sence of the stored charge at the PNjunction. When a charge is present, theequivalent circuit of the diode is a largevalued diffusion capacitance in parallelwith the AC resistance of the forwardbiased diode. This combination is a goodapproximation of a short circuit. Theamount of charge stored at the junctionis determined by the forward current IF,the time it flows tF, and the carrier life-time according to

(1)

If all of the charge is removed by a re-verse current IR, then the diode changesalmost instantaneously to its secondstate. In this high-impedance state, thediode looks like a small capacitor whosevalue is equal to the depletion layer ca-pacitance of the junction. If a forwardcurrent flows for a time >> tand then areverse current IR begins, then the timets that elapses before all the charge isremoved and the diode changes to itshigh impedance state is

(2)

A common way to measure the car-rier lifetime t is to set IF/IR equal to1.718 so that the time elapsed fromwhen the reverse current begins, towhen the diode turns off, is equal to the

carrier lifetime. To minimize inputlosses caused by carrier recombination,the selected diode should have a carrierlifetime of t‡ 5/w in. For a 100 MHzinput, the diode should have t‡8 ns.

SPICE model of SRDBefore proceeding with the design, it

is important to confirm that the genericSPICE model for a PN junction diodewill exhibit a charge-controlled stepchange in impedance. Figure 1a showsa simple SPICE circuit that tests forSRD action using IF = 10 mA and IR =5.82 mA, a ratio of 1.718. The model pa-rameters of primary importance forSRD modeling are carrier lifetime t(TT), depletion layer capacitance at aspecified value of reverse voltage Cj–6and junction-grading coefficient M. Thefirst two parameters are supplied by themanufacturer. The grading coefficientdetermines the variation of depletioncapacitance with reverse voltage. Avalue of M = 0.5, typical for an abruptjunction diode, was chosen and providedgood results in the simulation. TheSPICE model requires the value of de-pletion capacitance at zero volts Cj0.This may be calculated from the equa-tion for depletion layer capacitanceshown in Equation 3

(3)

Vj is the reverse junction voltage andfis the contact potential, which is setequal to 0.6 V.

Breakdown voltage and series resis-tance play a secondary role of limitingthe maximum power available from themultiplier circuit. The model parame-ters used for the SRD are shown inTable 1.

The results from the test circuit areshown in Figure 1b and demonstratethe effect of charge storage. BecauseIF/IR =1.718, the charge removal time tsis equal to t. The voltage source goes

CC

Vj

j

j

M=−

0

1φ

tI

IsF

R

= ⋅ +

τ ln 1

Q I eF

tF

= ⋅ ⋅ −

−τ 1 τ

discrete components

SPICE up the development of a steprecovery diode frequency multiplier

Figure 1. Testing SPICE model for SRD behavior. (a) Test circuit (b) Diode current showing sudden tran-sistion after tseconds.

With the aid of one of the many versions of SPICE, the design of frequencymultipliers using step recovery diodes is expedited and made more tractable.

V1 +

By George H. Stauffer Jr.

–5.1

+10.7

D1

Id

R1

IF = 10 mA

180

–2

Id(mA)

–8

–6

–4

0

8

6

4

2

160140120100806040200

TIME (ns)

IR = –5.8 mA t

A

B

18 www.rfdesign.com June 1999

negative at t = 100 ns, but because ofthe stored charge, the diode continuesto conduct a negative current for 20 ns.The transition time from on to off iscaused by the RC time constant of the 1

kW resistor and the diode depletionlayer capacitance.

Initial design of 100 MHz multiplierInitial circuit values are found

using the simplified multiplier circuitshown in Figure 2a. During the posi-tive portion of the input voltage, andfor part of the negative portion, theequivalent circuit is shown in Figure2b where the diode is represented by ashort circuit. Here, the circuit isshown at t0- the instant before thediode switches to its high impedancestate. A large reverse current that hasbeen removing charge from the SRD isflowing through the inductor and isabout to undergo a large di/dt whenthe diode switches at t = t0. Figure 2cshows the circuit at t = t0+. This is asimple parallel inductive-capacitive-resistive (LCR) circuit with an un-loaded resonant frequency w r @1/ LCj–6 and Q = R/w rL.

A large amplitude negative pulse be-gins at t = t0+. The pulse width is ap-proximately one half the period of theresonant frequency of the parallel LCcircuit. More accurate design formulasare available [2, 3 and 4]; however, sig-nificant design time is saved by usingthese approximate methods and thenusing the SPICE simulation to arrive atthe final values.

The initial value for the series in-ductance L is calculated by consideringthe required pulse width. Power at theoutput frequency fo is maximized forpulse widths between 1/2fo and 1/fo. Forfo = 3.2 GHz, a pulse width of 234 ps ishalfway between 1/2fo and 1/fo. For thispulse width, the resonant frequency ofthe parallel LC circuit of Figure 2c is fr= 2.17 GHz. A value of Q @ 1 is recom-mended for stable operation. For fr =2.17 GHz and Cj–6 = 0.7 pF, a value ofL = 8 nH is calculated using w r @1/ LCj–6 and R=107 W is found using Q= R/wrL = 1.

SPICE simulation ofmultiplier circuit

The simplified multiplier circuitusing the initial values is shown inFigure 3. Voltage source Vs supplies a100 MHz sine wave with 600 mV peakamplitude. Voltage source Vbias is a DCbias voltage. This bias voltage is ad-justed so that the current flowingthrough the inductor is at its negativepeak (dI L/dt =0) when the diodeswitches to the high impedance state.Figures 4a, b and c show the results ofthe SPICE simulation. Note that thediode current is at its peak maximumvalue at the transition time. The outputpulse has a width @ 260 ps and an am-plitude slightly less than the diodeFigure 4. Results from basic multiplier circuit. (a) Vin + Vbias (b) Diode current (c) Output pulse.

Id(mA)

Vd

(V)

1 ns

Vin + Vbias

(mV)

–800

–2

–4

–6

–8

–10

–12

–200

–100

–400

800

400

0

200

100

0

0

Figure 3. Basic multiplier with calculated compo-nent values ready for SPICE simulation.

Vbias

VdVinIin

L8 nH

Id R

DC

100 MHz

–+

Vs

Figure 2. Two states of the basic multiplier cir-cuit. (a) Basic circuit. (b) Circuit with SRD in lowimpedance state at t0– (c) Circuit with SRD inhigh impedance state at t0+.

L

C

B

A

RCJ–6

IL (t0+)

L

IL (t0–)

L

R

Parameter Symbol Value

Reverse saturation current Is 1 nACj at –6 V Cj–6 0.7 pFCj at 0 V Cj0 2.3 pFCarrier lifetime TT 20 nSBreakdown voltage BV –15 VSeries resistance Rs 0.7 WEmission factor N 1.5Grading coefficient M 0.5

Table 1. SRD SPICE model parameters.

20 www.rfdesign.com June 1999

breakdown voltage.

Input match at 100 MHzThe actual circuit will be driven by a

100 MHz generator with a 50 W sourceimpedance. For best efficiency, it is nec-essary to match the relatively low im-pedance of the SRD circuit to 50 W atthe input frequency. The ratio of theFourier components of the inputvoltage, and current at 100 MHz is theimpedance of the diode under operatingconditions. A fast Fourier transform(FFT) post-processing feature availablein many versions of SPICE can be usedfor this purpose. Figure 5a shows theinput current and voltage waveformsfrom the circuit of Figure 3 and the cal-culation of Zin. Figure 5b shows Zinplotted on a Smith chart and the results

after matching with an LC p network.

Ringer circuitA quarter wave resonant transmis-

sion line at 3.2 GHz is one way to boostthe level of the desired harmonic abovethe other harmonics before additionalfiltering. The line is terminated with aresistance chosen so that the loaded Qof the resonant line is approximately(p/4)N, where N is the ratio of desiredoutput frequency to input frequency (N= 32 for this design). The output of theresonant line for this value of Q is adamped sine wave that spans one inputcycle. Q is adjusted by varying the de-gree of coupling to the 50 W load with asmall series capacitor. The length ofline is adjusted so that the sinusoidrings with a period of 312 ps. The char-acteristic impedance Z0 of the line ismade equal to the shunt resistance R inFigure 3. Z0 is 107 W for this design,and is the resistance that the pulse seesbefore the first reflection arrives back at

the SRD. Figures 6a, b and c show thefinal circuit, the damped waveform andan FFT of the damped waveform. Thepower in the 3.2 GHz line is –9.1 dBmwith 14.5 dBm input.

Results from working circuitThe layout of the 100 MHz to 3.2

GHz multiplier is shown in Figure 7.The circuit was built on a 2†·2†FR-4board, 0.031†thick using 0805 and 0603surface mounted components .Comparison between simulated andmeasured performance is shown inTable 2.

ConclusionThe simple SPICE model of a 100

MHz to 3.2 GHz multiplier predicted ac-tual circuit operation accurately for anoutput frequency in the low microwaverange using the generic SPICE modelsfor the SRD and all passive components.The extremely non-linear behavior of anSRD diode is easily handled by the time-

Figure 6. Final multiplier circuit (a) Circuit with input match and ringer. (b) Damped waveform at output.(c) Output spectrum.

Iin

Vs100 MHz

50 W

1,000 pF

Vin 1 mH

VbiasDC

25 nH

150 pF 200 pFId

Vp

Zo = 110 W

Td = 68 ps

0.1 pF

Vout

50 W

10 nH

51

–800

10 ns

400

TIME (ns)

Vout(mV)

–400

800

0

35 39 43 47 4.0

20

140

FREQUENCY (GHz)

Vout(mV)

60

180

100

2.4 2.8 3.2 3.6

Pin Vbias Harmonic : 3.1 GHz 3.2 GHz 3.3 GHz

SPICE 14.5 dBm + 0.3 V –12.3 dBm –9.1 dBm –15.2 dBmMeasured 14.5 dBm + 0.3 V –18 dBm –10.3 dBm –13 dBm

Table 2. SPICE vs. measured results.

Figure 5. Input impedance Zin at 100 MHz. (a)input voltage, current waveforms and calculationof Zin. (b) Matching to Zin with p network.

Iin(mA)

Vin(V)

1 ns

Vin

Iin

200

TIME (ns)

–800

–400

–200

–100

0

400

800

0

100

17.5nH

Zin

200pF

185pF

50 W

50 W

17.5 nH

185pF

200pF

568 pF

2.9 W

Zin = 2.9 – j2.8

Vin

j

= ∠ −

∠ −

= ∠ − − ( )

0 6 90

45 8

4 44 2 2 9 2 8

.

.

. . .

!

!

!

V at 100 MHz

Iin = 0.149 A at 100 MHz

Zin =Vin

Iin= 100 MHzΩ

22 June 1999

domain simulator resulting in short sim-ulation times. Adjustments to the circuitmodel are reflected in circuit perfor-mance that reduces time spent doing de-tailed theoretical calculations and hard-ware iterations.

References1. S. Goldman, “Computer Aids

Design of Impulse Mult ipl iers , ”Microwaves & RF, October 1983, pp101-110.

2. S. Hamilton and R. Hall, “ShuntMode Harmonic Generation Using StepRecovery Diodes,” Microwave Journal,April 1967, pp 69-78.

3. Pulse and Waveform Generationwith Step Recovery Diodes, Hewlett-Packard Application Note #918.

4. Harmonic Generation Using StepRecovery Diodes, Hewlett-PackardApplication Note #920.

5. J. Zhang and A.V. Raisanen,“Computer-Aided Design of StepRecovery Diode Frequency Multipliers,”IEEE Trans. Microwave Theory Tech.,Vol 44, pp 2612-2616, Dec. 1996.

6. S.A. Maas, Nonlinear MicrowaveCircuits, Artech House, Norwood, MA,1988.

Join us at the IEEE-MTT-S SHOW in Anaheim, CA JUNE 15-17 “99 booth #2121INFO/CARD 71

About the authorGeorge H. Stauffer Jr. is an assis-

tant professor of electronics and elec-trical engineering at Capitol College,Laurel, MD. Previously he worked asan RF and microwave circuit designengineer in the Radio Receiver Groupof Watkins Johnson Company inGaithersburg, MD. He holds the A.Band B.S.E.E degrees from LafayetteCollege, Easton, PA. and an M.S. de-gree f rom The Johns HopkinsUniversity. He can be reached at 301-369-2800 or by e -mai l a tgstauffer@capitol-college.edu.

Vbias

10 nH

180 pF150 pF

25 nH1 m H

1,000 pF

100 MHz

0.1 pF

3.2 GHz BPF(NOT SHOWN)