stick diagram.pptx

8/9/2019 Stick diagram.pptx

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STICK DIAGRAMS

P- Diffusion

n- Diffusion

Poly silicon

Metal 1

Contact cut

N implant

Demarcation line

Substrate contact

PMS !n"ancement Transistor

NMS !n"ancement Transistor

NMS Depletion transistor

NPN #ipolar Transistor

#urie$ Contact


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%DD

GND

NMS IN%!RT!R STICK DIAGRAM

D

A

#S

D


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%DD

GND

CMS IN%!RT!R STICK DIAGRAM

&IG 1 Supply rails


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VDD

GND

PMOS

NMOS

S

S

D

D

CMOS INVERTER STICK DIAGRAM

Fig 2 Drawing Pmos and Nmos Transistors between S!!"# rai"s


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%DD

GND

PMS

NMS

A

S

S

D

D


&i' ( Combinin' Gate of Pmos an$ Nmos Transistors an$ 'i)in' common input

*it" same 'ate poly silicon metal


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%DD

GND

PMS

NMS

A

DS

S D


&i' + Combinin' Drain pf Pmos an$ Nmos Transistors to ta,e output it" metal 1


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%DD

GND

PMS

NMS

D

A

S

S D

$


&i' . Ta,e t"e output it" t"e poly silicon metal


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%DD

GND

PMS

NMS

D

A

S

S D

#


&i' / Connect t"e source of Pmos to %DD an$ Nmos to GND


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%DD

GND

PMS

NMS

D

A

S

S D

#

CNTACT


&i' 0 Connect t"e contact cuts "ere t"e $ifferent metals are connecte$


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%DD

GND

PMS

NMS

D

A

S

S D

#

CNTACT


&i' &inal CMS In)erter

Substrate contact


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%DD

GND

CMS NAND GAT! STICK DIAGRAM

&IG 2 Supply rails


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%DD

GND


&i' 13 Drain' P an$ N Diffusion beteen Supply rails


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%DD

GND

SS

SD

DD

DS

A #

C


&i' 11 Drain' t"e poly silicon for to $ifferent inputs an$

i$entify t"e source an$ $rain


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%DD

GND

SS

SD

DD

DS

A #

C


&i' 14 Connect t"e source of Pmos to %DD an$ Nmos to GND an$

subtrate contacts of bot"


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%DD

GND

SS

SD

DD

DS

A #

C


&i' 1( Dra t"e output connections


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%DD

GND

SS

SD

DD

DS

A #

C


&i' 1+ Connect t"e contact cuts "ere t"e $ifferent metals are connecte$


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%A&O'T


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2(

2(

)(

2(

*(

P di+sion N di+sion

P di+sion

P di+sion N di+sion

P di+sion

META% )

META% ),(

,(*(


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2(

,(

,(

)( 2( ,(

,(

)(

2(*(


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%AM$DA $SED R'%ES


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CMOS INVERTER%A&O'T


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VDD

VSS


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VDD

VSS

ND

PD


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VDD

VSS

ND

PD

PO

% &

S D

S D


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VDD

VSS

ND

PD

PO

% &

S D

S D


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VDD

VSS

ND

PD

PO

% &

S D

S D

INP' T

O'TP' T

S'$CONT

S'$CONT


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CMOS NAND%A&O'T


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VDD

VSS


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VDD

VSS

S S

S SD

DD

D


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VDD

VSS

S'$CONT

S'$

CONT

A $ O'TP' T

S SDD

S SD D


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Scaling

%5SI tec"nolo'y is constantly e)ol)in' toar$s

smaller line i$t"s

Re$uce$ feature si6e 'enerally lea$s to

better 7 faster performance

More 'ate 7 c"ip

More accurate $escription of mo$ern tec"nolo'y is

85SI 9ultra lar'e scale inte'ration:


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MOSFET Scaling

SCA5ING - refers to or$ere$ re$uction in $imensions of

t"e MS&!T an$ ot"er %5SI features

Re$uce Si6e of %5SI c"ips?

C"an'e operational c"aracteristics of MS&!Ts an$

parasitic?

P"ysical limits restrict $e'ree of scalin' t"at can be

ac"ie)e$?


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2. Constant Voltage Scaling

%$$ is ,ept constant?

All $imensions; inclu$in' t"ose )ertical to t"e

surface are scale$?

Concentration $ensities are scale$?


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DERIVATION OF SCA%ING PARAMETERS 6

1?Gate Area9 A': #efore Scalin'

After Scalin'

Area is reduced by α2,it is advantage.


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* Gate Ca!a3itan3e 7C 86


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* Gate Ca!a3itan3e 7Cg 86

#efore Scalin'

After Scalin'

Cg is s3a"ed b#

9:;2


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< C4arge in C4anne" = 6


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- C4anne" Resistan3e 7RON 86

#efore Scalin'

After Scalin'

H - Constant

RON is s3a"ed b#

)

> G t d " 7T 8


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#efore Scalin'

After Scalin'

>Gate de"a# 7Td8 6

Td is s3a"ed b# 9 :

;2


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@ Satration Crrent 7I 8 6


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@ Satration Crrent 7Idss8 6

#efore Scalin'

After Scalin'

Ids is s3a"ed b# ):9

) Crrent Densit# 7B8 6


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) Crrent Densit# 7B8 6

#efore Scalin'

After Scalin'

B is s3a"ed b# ;2:9


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ower ss !at on !er gate


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! ! g7Pg8 6

#efore Scalin'

Static Component

Dynamic Component

After Scalin'


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Pg is s3a"ed b# ):92


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), Power S!eed Prod3t 7PT8 6


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), Power S!eed Prod3t 7P T8 6

#efore Scalin' After Scalin'

P T is s3a"ed b#

):;29

PARAM!T!R SCA5ING MD!5


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PARAM!T!R SCA5ING MD!5Constant Constant 5ateral

&iel$ %olta'e

5en't" 95: 17α 17α 17α

*i$t" 9*: 17α 17α 1

Supply %olta'e 9%: 17α 1 1

Gate >i$e t"ic,ness 9to>: 17α 17α 1

unction $ept" 9J: 17α 17α 1

Current 9I: 17α α α

Poer Dissipation 9P: 17α2 α α

!lectric &iel$ 1 α 15oa$ Capacitance 9C: 17α 17α 17α

Gate Delay 9T: 17α 17α2 17α2


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Scalin' of Interconnects

• Resistance of trac, R L 5 7 t

• R 9scale$: L 95 7


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Scalin' - Time Constant

• Time constant of trac, connecte$ to 'ate;• T B R C'

• T9scale$: B < R 9= 7


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stick diagram.pptx

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