© 2007 Altera Corporation—Confidential

Stratix II GXTransceivers with IntegrityHigh-Speed Serial I/O WorkshopsQ4, 2006 and Q1, 2007(Version 02/2007)

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

AgendaAgenda

Stratix® II GX overviewComplete solution− Transceiver building blocks− Hard IP and IP cores− Pre-emphasis and equalization− Lowest-power solution− Development kits− Characterization results

Deliverable / schedules

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

65 nm90 nm

Altera FPGA RoadmapAltera FPGA RoadmapPe

rfor

man

ce &

Den

sity

2002-04 2004-05 2006-07

130 nm2008-10

45 nm

Cyclone III

HardCopy IIIHardCopy III

Stratix III GXStratix III GX

Stratix III

Stratix II GX

Stratix II

Cyclone II

HardCopy II

Cyclone®

Stratix GX

HardCopy®

Stratix

Cyclone IVCyclone IV

HardCopy IVHardCopy IV

Stratix IV GXStratix IV GX

Stratix IVStratix IV

Planning

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX FPGAsStratix II GX FPGAs

Up to 20 transceivers operating between 600 Mbps and 6.375 GbpsLowest-power FPGA with embedded transceiversBest-in-class signal integrity solution includes pre-emphasis and equalizationComplete protocol solution including software support, intellectual property, system models and reference designs

Transceivers With Optimal Signal Integrity

Third Family on 90 nm

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX Family PlanStratix II GX Family Plan

Device TransceiverChannels

EquivalentLogic

ElementsPLLs

33,880 4

EP2SGX60C 4 60,440 2,544,192 144 6

EP2SGX60E 12 60,440 2,544,192 144 8

EP2SGX90F 16 90,960 4,520,448 192 8

EP2SGX30D 8 33,880 1,369,728 64 4

6

8

8

60,440

90,960

132,540

4

8

12

20

TotalMemory

Bits

18-Bit x18-Bit

Multipliers

EP2SGX30C 1,369,728 64

EP2SGX60D 2,544,192 144

EP2SGX90E 4,520,448 192

EP2SGX130G 6,747,840 252

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Device TransceiverChannels

LVDSChannels

4 29

29

29

29

42

45

EP2SGX90F 16 59 650

71

4

8

8

12

12

20

F780(29 mm)

User I/O Pins

F1152 (35 mm)

User I/O Pins

F1508 (40 mm)

User I/O Pins

EP2SGX30C 361

364

EP2SGX30D 361

EP2SGX60D 364

EP2SGX60C

EP2SGX60E 534

EP2SGX90E 558

EP2SGX130G 734

Stratix II GX Package PlanStratix II GX Package Plan

Devices in the Same Package Are Upward Pin Compatible

Preliminary User I/O Count

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX Addressable ProtocolsStratix II GX Addressable Protocols

OC-3

SDI-SD

OC-12CPRI

OBSAI

Gigabit EthernetSDI-HDCPRI

OBSAISerial RapidIO

1G Fibre Channel

Mbps Gbps155M 270M 622-768M 1-1.4G 2-2.25G 3-3.2G 4.25G 5G 6-6.5G 10-12G

PCI ExpressOC-48CPRISRIO

2G Fibre ChannelInfiniband 4G Fibre Channel

Serial RapidIO 2.0CEI6LR

XAUISerial RapidIO

PCI Express 2.0

Achievable With Over Sampling

Addressable by Stratix II GX

Optimized Performance for Applications Between 600 Mbps and 6.375 Gbps

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Complete Protocol SolutionsComplete Protocol Solutions

Hard protocol IP, IP core functions, reference designsSignal integrity modeling Protocol-specific development boards − PCI Express and SDI

Evaluation boardQuartus® II supportCompliance testingSystem validation reportsCharacterization reports

Dramatically Increase Ease of Design

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Standards SupportedStandards SupportedStandards Data Rate Built-in PCS Blocks

PCI Express 1.1 2.5 Gbps6.25 Gbps

Gigabit Ethernet 1.25 Gbps IEEE Gigabit Ethernet PCSSerial RapidIO 1.25, 2.5, 3.125 8B/10B

SONET OC-12 622 Mbps A1A2 Pattern Detector and Aligner

SONET OC-48 2.488 Gbps A1A2 or A1A1A2A2 Pattern Detector and Aligner

3.125 Gbps270 Mbps

HD-SDI 1.488 Gbps No special blocks for SDI

3G Basic 600 Mbps to 3.1875 Gbps For proprietary protocols: 8B/10B

6G Basic 1 Gbpsto 6.375 Gbps For proprietary protocols: 8B/10B

OIF CEI 6GPIPE Compliant

8B/10B

SD-SDIXAUI IEEE XAUI PCS

No special blocks for SDI

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Complete Transceiver Building BlocksComplete Transceiver Building Blocks600 Mbps – 6.375 GbpsPre-emphasis and equalizationGeneric (basic) transceiver functionality− 8b/10b encoder/decoder− Rate matcher− Phase compensation FIFO− 8,10,16, 20, 32, 40 bit interface to core

PCIe state machine− Power state sequencing− Electrical idle, receive detect and others− PIPE interface to core

Gigabit Ethernet state machine− Comma character insertion/deletion− GMII-like interface to core

XAUI state machine− Channel deskew, alignment,

and bonding− XGMII-like interface to core

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Dynamic Channel ReconfigurationDynamic Channel Reconfiguration

Quad architectureSupport for 2 clock domainsSupport for up to 4 distinct rates from 600 Mbps to 6.375 GbpsDynamic re-configuration of transceiver data rates and modes

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Soft IP CoresSoft IP Cores

MegaCore® IP function− Developed by Altera: PCIe, SDI, SRIO, GigE & SerialLite II− Sold and supported by Altera− OpenCore Plus for free evaluation− Helps customers focus on their core competency

Altera MegaFunction Partners Program (AMPP)− IP cores developed and supported by AMPP partners: 10GE, SONET

and FC− AMPP partners certified by Altera− Best-in-class IP providers in the industry− Helps customers focus on their core competency

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Reference DesignsReference Designs

Provide key to solving engineering challenge− Provide working examples− Improve productivity− Allow designers to concentrate on core competency

Allow for system validation− Proof of concept− Calculate real-world data rates

Include full documentation and design filesAvailable on Altera® web or development kits

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Transceiver MegaWizardTransceiver MegaWizard

Simplifies Transceiver Configuration

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Focus on Lowering PowerFocus on Lowering Power

425 mW

140 mW

550 mW

3.125 6.375

VirtexVirtex--4 FX4 FX

11 Watts of Power with 20 Transceiversat 6.375 Gbps

mW

500

300

100

Transceiver Speed (Gbps)

Stratix II GX Dissipates Less Than 7 Watts Compared to V4-FX at Full Speed!

4 Watts of Power with 20 Transceivers at 6.375 Gbps

VirtexVirtex--4 FX4 FX

200 mW

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Lowest Power and Best Jitter GenerationLowest Power and Best Jitter Generation

Power Optimized With Two Ranges of PLLs

One PLL shared between two transmitters for the entire range

TX1

TX2

PLL2.5-10 Gbps

Virtex-4 FX

TX3

TX4

PLL2.5-10 Gbps

Identical PLLs (.600- 6.375 Gbps) can be optimized for either low or high data

rates

TX1

TX2

TX3

TX4

PLL0.600 - 3.125 Gbps

PLL0.600 - 3.125 Gbps

PLL2.5 - 6.375 Gbps

PLL2.5 - 6.375 Gbps

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Voltage Regulator and Noise Filter- Required For All Transceiver DesignsVoltage Regulator and Noise Filter- Required For All Transceiver Designs

Internal Voltage Regulator Suppresses Noise

Internal voltage regulator and filter suppresses noise

Noise FilteringVoltage Regulator

Noise FilteringVoltage Regulator

PLLPLLPLLPLL

External voltage regulator susceptible to noise coupling

PLL

Voltage Regulator

FX

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

PCI Express Development KitPCI Express Development KitEP2SGX90FF1508x8 PCI ExpressDDR2− 72-bit, 333 MHz

QDRII− 36-bit, 300 MHz

(350 MHz QDRII+)2x SFP PortsJTAG header10/100/1G Ethernet2x mezzanine connector− Up to 84 LVDS − Up to 6 transceivers− Up to 3 clocks

SMA clock inputPCI Express Development Kit Stratix II GX Edition DK-PCIE-2SGX90N ($2,995)

Now Shipping

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Mezzanine SolutionsMezzanine Solutions Modular HSMC

AdaptersNew interface specification from AlteraProvides access to − 8 TXVR channels (full duplex)− 17 LVDS channels (full duplex)− 3 clocks (full duplex)− JTAG− System management bus

Provide Stratix II GX development kit access to industry standard busses− Advanced TCA mezzanine cards

(AMC)− CX-4 10GbE XAUI

Purchase from MorethanIP

PCIe x8

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Audio Video (SDI) Development KitAudio Video (SDI) Development Kit

EP2SGX90FF15082x SDI BNC connectors2x SFP portsJTAG header10/100/1G EthernetMezzanine connector− Up to 84 LVDS − Up to 6 transceivers− Up to 3 clocks

SMA clock inputAudio Video Development Kit Stratix II GX EditionDK-VIDEO-2SGX90N ($ 4,995)

Now Shipping

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Transceiver SI Development KitTransceiver SI Development Kit

EP2SGX90EF1152SMAs to transceivers− 6 full duplex channels− 3 quads− 40” trace on one transmit channel

On-board oscillators− External clock via SMA for jitter

testing16V DC wall adapter− External power via banana jacks

for jitter testingTransceiver Signal Integrity Development Kit Stratix II GX EditionDK-SI-2SGX90N ($1,295)

Now Shipping

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Pre-emphasis and/or Equalization Compensates for PCB DegradationPre-emphasis and/or Equalization Compensates for PCB Degradation

Increasing pre-emphasis levels

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Best-in-Class Signal IntegrityBest-in-Class Signal IntegritySimulated Receive Eye,

With No EqualizerSimulated Receive Eye,

With 17dB Equalizer

Eye Opening After 34” Tyco Backplane

Eye Opening After 34” Tyco Backplane & 9.5dB Pre-emphasis

ReceiveReceive

TransmitTransmit6.375 Gbps

6.375 Gbps

© 2007 Altera Corporation—Confidential

Altera’s Track Record of Success

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX Devices Have No Errata.. No Surprises.. Low RiskStratix II GX Devices Have No Errata.. No Surprises.. Low Risk

Full process, voltage, and temperature characterizationAvailable characterization reports− General transceiver (85 pages)− SONET: OC-48 and OC-12 (33 pages) Compliant− PCI Express (39 pages) Compliant− Fibre Channel (30 pages) Compliant− SSN (30 pages)− XAUI/Serial RapidIO in Q1

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

InteroperabilityInteroperabilityUNH validated− MAC, flow-control, interoperability− MorethanIP part of UNH lab equipment for interoperability testing

http://www.iol.unh.edu/services/testing/10gec/equipment.php

Tested with major ASSPs and standard parts

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

FC and SONET Compliance (PVT)FC and SONET Compliance (PVT)

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Built on Altera’s 90-nm SuccessBuilt on Altera’s 90-nm Success

All Products Delivered as Committed--Stratix II FPGAs, On Time in 2004--Cyclone II FPGAs, On Time in 2005--HardCopy II, On Time in 2005

Stratix II GX, On Time March 27, 2006

Altera 90-nm Report Card

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Why Is Altera Successful?Why Is Altera Successful?

Tight relationship with TSMC since 1989Test chips, test chips, and more test chips on advanced technologies − Now doing 65-nm test chips

Stratix II success followed (10) 90-nm test chipsStratix II GX builds on Stratix II success and leverages 3 transceiver test chips on 90 nm

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II Device FloorplanStratix II Device Floorplan

High-Speed I/OChannels with

Dynamic Phase Alignment (DPA)

I/O Channels with External Memory

Interface Circuitry

High-Speed I/OChannels with Dynamic Phase Alignment (DPA)

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Production Stratix II FPGA + Proven Transceiver Block = SuccessProduction Stratix II FPGA + Proven Transceiver Block = Success

Stratix II FPGATransceiver Block (TC2)

Transceiver I/Os replaced LVDS I/Os

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX Device FloorplanStratix II GX Device Floorplan

High-Speed Serial Transceiver Channels (600 Mbps- 6.375 Gbps)

Low-Risk Evolution of Stratix II GX

High-Speed I/OChannels with

Dynamic Phase Alignment (DPA)

I/O Channels with External Memory

Interface Circuitry

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II + TC2 BoardStratix II + TC2 Board

Transceiver Validation Prior to Integration Minimizes Risk

© 2007 Altera Corporation—Confidential

Stratix II GX Characterization Results

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX RX Jitter Tolerance: 6.375 GbpsStratix II GX RX Jitter Tolerance: 6.375 GbpsExcellent jitter tolerance with 80% core noise and 80% I/O switching2SGX90 closely tracked TC2 performance

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX RX Jitter Transfer: 6.375 GbpsStratix II GX RX Jitter Transfer: 6.375 GbpsExcellent jitter transfer with 80% core noise and 80% I/O switching2SGX90 closely tracked TC2 performance

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Low-Power TransceiversLow-Power Transceivers

© 2007 Altera Corporation—Confidential

Schedule Update

January 2007

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

Stratix II GX Device ScheduleStratix II GX Device Schedule

Stratix II GX Device Availability Schedule

Product Line

EngineeringSamples

lead & lead-free

ProductionDevices

lead (lead-free)

IndustrialDevices

lead & lead-freeEP2SGX90 Now Now WW10'07EP2SGX130 Now Now NowEP2SGX60 Now NowEP2SGX30 Now NowNotes:1) QA and characterization performed on the bigger die and package of the EP2SGX90 and EP2SGX130 devices are applicable to the smaller EP2SGX30 and EP2SGX60 devices. Hence, EP2SGX30 and EP2SGX60 devices w ill go directly to production and skip the ES phase

Stratix II GX Development Kit Availability ScheduleDev Kit Production (lead-free)DK-SI-2SGX90N ($1,295) NowDK-PCIE-2SGX90N ($2,995) NowDK-VIDEO-2SGX90N ($4,995) Now

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

What Customers Are Saying About Stratix II GXWhat Customers Are Saying About Stratix II GX

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© 2007 Altera Corporation—Confidential Altera, Stratix, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

SummarySummary

Optimal signal integrity Lowest powerTools, IP and proven protocol solutions that reduce your risk and time-to-marketAvailable now

Start Designing Today