Structure of Computer Structure of Computer SystemsSystems

Course 3Course 3

The Arithmetical and Logical UnitThe Arithmetical and Logical Unit

ALU- Arithmetical and Logical UnitALU- Arithmetical and Logical Unit

Purpose: computes arithmetical and logical operations:Purpose: computes arithmetical and logical operations: arithmetical: arithmetical:

• basic operations: add, subtract, multiply, division, modulobasic operations: add, subtract, multiply, division, modulo

• special functions: exponential, logarithm, sine, cosine, tangent, special functions: exponential, logarithm, sine, cosine, tangent, atangent, etc.atangent, etc.

logical:logical:• AND, OR, NOT, inclusiveOR, exclusiceORAND, OR, NOT, inclusiveOR, exclusiceOR

Types of arithmetic units:Types of arithmetic units: integer arithmeticinteger arithmetic floating point arithmetic (e.g. Intel’s co-processor)floating point arithmetic (e.g. Intel’s co-processor) signal processing arithmetic (e.g. with saturation MMX)signal processing arithmetic (e.g. with saturation MMX) parallel arithmetic (MMX - integer, SSE2- floating point)parallel arithmetic (MMX - integer, SSE2- floating point)

AdditionAddition

most used operationmost used operation all the other arithmetic operations are based on all the other arithmetic operations are based on

addition:addition: subtract – adding the complementsubtract – adding the complement multiply – repetitive addingmultiply – repetitive adding division – repetitive subtraction and addingdivision – repetitive subtraction and adding

efficient implementation of adding operation:efficient implementation of adding operation: influence directly all the other operationsinfluence directly all the other operations efficiency: speed and cost (complexity)efficiency: speed and cost (complexity)

AdditionAddition Basic (full) adder unit – one bit adderBasic (full) adder unit – one bit adder

inputs: xinputs: xii, y, yii, C, Cii

outputs: outputs: • SSii = = xxii yyi i CCii

• CCii = = xxiiyyii + (x + (xii y yii) ) CCii-1-1

delay: 3* gate_delaydelay: 3* gate_delay

One bit adder

xi yi

Ci Ci-1

Si

SSii

xi yi Ci-1

Ci

““n” bit adder with ripple carryn” bit adder with ripple carry n bit adder = n * (1 bit full adder)

delay: n*3*gate_delay

example:

• n=32; gate_delay = 10 ns (TTL gate) =>

• delay: 32*3*10ns ~= 1000 ns => fclk_max = 1/1000 ns = 106 =1MHz !!!

1 bit adder

Sn-1

yn-1

xn-1

Cn-2 1 bit adder

Sn-2

yn-2

xn-2

Cn-3 1 bit adder

S1

y1

x1

C0 1 bit adder

S0

y0

x0

C-1Cn-1

X Y

n bit adder

S

SubtractSubtract subtract = adding with the second number’s 2subtract = adding with the second number’s 2 thth complement complement n bit add and subtract:n bit add and subtract:

Add/Sub = 0 => addingAdd/Sub = 0 => adding Add/Sub = 1 => subtractionAdd/Sub = 1 => subtraction

1 bit adder

Sn-1

yn-1xn-1

Cn-2 1 bit adder

Sn-2

yn-2xn-2

Cn-31 bit adder

S1

y1

x1

C0 1 bit adder

S0

y0

x0

Cn-1

Add/Sub

Sequence of steps for addingSequence of steps for adding

StepStep BUSBUS SELSEL LD_A/LD_A/ LD_B/LD_B/ Add/SubAdd/Sub Wr_m/Wr_m/ ResultResult

11 XX 11 00 11 -- 11 A<=XA<=X

22 YY 00 11 00 00 11 B<=YB<=Y

33 -- 00 00 11 00 11 A<=X+YA<=X+Y

44 ZZ -- 11 11 -- 00 Z<=X+YZ<=X+Y

Control unit

MUX

Reg. A Reg. B

Add&Sub

ClkSelLd_A/

Ld_B/

Data Bus (D0-D15)

Add/Sub

0 1

Amp. Temp

Wr_m/

Instr. code

Improving the AdderImproving the Adder Carry Look-ahead AdderCarry Look-ahead Adder

Issue:Issue: the delay time of the carrythe delay time of the carry Solution: direct generation on carry => “Carry lookahead adder”Solution: direct generation on carry => “Carry lookahead adder”

CCii = = xxiiyyii + (x + (xii y yii) ) CCii-1-1 = g= gii +p +pii*c*ci-1i-1

where: gwhere: gii – carry generator – carry generator

ppii – carry propagator – carry propagator

CC00 = x = x00yy00 + (x + (x00 yy00)C)C-1-1 = g = g00 +p +p00*C*C-1-1

CC11 = x = x11yy11 + (x + (x11 yy11)C)C00 = g = g11 +p +p11*C*C00 = g = g11 +p +p11*(g*(g00 +p +p00*C*C-1-1)= g)= g11 +p +p11gg00 +p +p11pp00CC-1-1

CC22 = x = x22yy22 + (x + (x22 yy22)C)C11 = g = g22 +p +p22*C*C11 = g = g22 +p +p22*[g*[g11 +p +p11*(g*(g00 +p +p00*C*C-1-1)] =)] = = g= g22 +p +p22gg11 +p +p22pp11gg00 +p +p22pp11pp00*C*C-1-1

............CCi i =f(g=f(g00, g, g11, ... g, ... gii, p, p00, p, p11, ... p, ... pii, , CC-1-1) = f(x) = f(x00, x, x11, ... x, ... xii, y, y00, y, y11, ... y, ... yii,, CC-1-1))Conclusion: CConclusion: Cii is obtained directly by combining ONLY input signals is obtained directly by combining ONLY input signalsDrawbacks: Drawbacks:

- the circuit’s complexity grows exponentially with the number of bits (n)- the circuit’s complexity grows exponentially with the number of bits (n)- it requires gates with a lot of input signals- it requires gates with a lot of input signals- delay- delayidealideal = 2*gate_delay = 2*gate_delay

Carry Look-ahead Adder - CLUCarry Look-ahead Adder - CLU

generates a result in a shorter timegenerates a result in a shorter time CLU is feasible for 4 bits – the gate inputs’ number is limited CLU is feasible for 4 bits – the gate inputs’ number is limited it can be extended putting together 4 bit addersit can be extended putting together 4 bit adders

Carry Look-ahead Unit (CLU)

S0

C-1

x0 y0

C0 p0 g0

1 bit adder

C1 p1 g1

1 bit adder

Cn-1 pn-1 gn-1

1 bit adder

S1Sn-1

x1 y1xn-1 yn-1

Carry Look-ahead AdderCarry Look-ahead Adder

extension from 4 bits to 16 bitsextension from 4 bits to 16 bits Generators and propagators for blocks of bits from “i” to Generators and propagators for blocks of bits from “i” to

“k”“k”:: Group generateGroup generate ggii,,kk

Group propagateGroup propagate ppii,,kk For a block of 4 bitsFor a block of 4 bits::

GG0,30,3 = = gg33 + + pp3 3 gg22 + + pp3 3 pp2 2 gg11 + + pp3 3 pp22 pp1 1 gg00

PP0,30,3 = = pp3 3 pp22 pp1 1 pp00

Using this notation we obtain block caries CUsing this notation we obtain block caries C33, C, C77, C, C1111,, CC1515

CC33 = = GG0,30,3 + + PP0,30,3 CC-1-1 CC77 = = GG44,,77 + + PP44,,77 CC33 = = GG44,,77 + + PP44,,77((GG0,30,3 + + PP0,30,3 CC-1-1 ))

Carry Look-ahead AdderCarry Look-ahead Adder

16 bit carry look-ahead adder made of:16 bit carry look-ahead adder made of: 4 units of 4 bit carry look-ahead adders4 units of 4 bit carry look-ahead adders one 4 bit carry look-ahead unit one 4 bit carry look-ahead unit

p0,3g0,3

S0-3

X0-3 Y0-3

4 bit adder C-1

p0,3g0,3

S0-3

X0-3 Y0-3

4 bit adder

p0,3g0,3

S0-3

X0-3 Y0-3

4 bit adder

p0,3g0,3

S0-3

X0-3 Y0-3

4 bit adder

4 bit carry look-ahead unit

C3C7C11C15

C3 p3 g3 C2 p2 g2 C1 p1 g1 C0 p0 g0

Carry select adderCarry select adder Extra hardware to speed-up the adding Extra hardware to speed-up the adding Avoids complex carry look-ahead unitAvoids complex carry look-ahead unit

Y3,0 X3,0Y7,4 X7,4

MUX1 0

4 bit adder4 bit adder4 bit adder

S3,0C7,S7,4

1 0

C3

Serial adderSerial adder

Adding two sequences of bits with a 1 bit adder Adding two sequences of bits with a 1 bit adder

1 bit adder

Q D

An-1 ….A2 A1 A0

Bn-1 ….B2 B1 B0

Si

Ci

Ai

Bi

Ci-1

Sn-1 ….S2 S1 S0

Clkclk

shift entry

shift entry

BCD adderBCD adder

adding numbers in BCD –(binary coded decimal) adding numbers in BCD –(binary coded decimal) representationrepresentation

a correction is needed:a correction is needed:• if the figure is not a decimalif the figure is not a decimal• If a carry is generated to the next group of 4 bits (to the next decimal figure)If a carry is generated to the next group of 4 bits (to the next decimal figure)

solution: adding 6 (both cases)solution: adding 6 (both cases) Example:Example:

89+89+ 4242 CB+ correctionCB+ correction 6666131131

4 bits adder

4 bits adder

0 0

X3,0 Y3,0

S’3,0

S3,0

S3 S2 S1 S0 C Corr0 0 0 0 0 01 0 0 1 0 01 0 1 0 0 11 0 1 1 0 11 1 0 0 0 11 1 0 1 0 11 1 1 0 0 11 1 1 1 0 1x x x x 1 1

MultiplicationMultiplication

Multiply = repeated adding Multiply = repeated adding

1100 * 12 * 1010 10

0000 1100 00001100

1111000 = 78H = 120

Issues: - we need a 2n bits adder - partial products must be placed in different positions

Modified multiply: 00000000 Acumulator (AC)“0” → 0000000 0 shift right“1” → 1100 adding

0001100 0 partial product

000110 00 shift right.“0” → 00011 000 shift right“1” → 1100 adding

1111 000 final product

Solution: shift the partial result to the right and put the

product in the same place Advantages: - we need just an n bits adder - partial products in the same place

MultiplicationMultiplication

(n+1)

Command unitShift

X

Q0Q1Q n-1. . .

B0B1Bn-1. . .BS

A0A1An-1

. . .AS

Q S

Y

Clear

Write

Scriere

Test

Shift

Write

Multiply algorithmMultiply algorithm

1.1. Write the operands in registers (B ← X, Q ← Y), Write the operands in registers (B ← X, Q ← Y), clear accumulator (A ← 0)clear accumulator (A ← 0)

2.2. Complement the negative numbersComplement the negative numbers

3.3. Test QTest Q00 If QIf Q00 = 0, shift right A and Q = 0, shift right A and Q If QIf Q00 = 1, add A = B + A and shift right A and Q = 1, add A = B + A and shift right A and Q

4.4. Go to step 3 until YGo to step 3 until Yn-1 n-1 arrives inarrives in Q Q00. No shift is . No shift is needed after the last stepneeded after the last step

5.5. AASS = B = BSS + Q + QSS

6.6. If AIf ASS = 1 complement the result = 1 complement the result

Multiply with Booth algorithmMultiply with Booth algorithm Improvements:Improvements:

Multiply numbers in 2Multiply numbers in 2thth complement; no initial and final complement; no initial and final complementation are neededcomplementation are needed

For long sequences of 0s and 1s only shift operations are For long sequences of 0s and 1s only shift operations are needed:needed:

• For 0s – it is obvious from the previous methodFor 0s – it is obvious from the previous method• For a sequence of 1s: For a sequence of 1s:

Examples: 1111 = 10000 -1; Examples: 1111 = 10000 -1; 11.1111 = 100.000 – 111.1111 = 100.000 – 1

• A sequence of 1s can be changed into a sequence of 0sA sequence of 1s can be changed into a sequence of 0s• Only transitions from 0 to 1 or 1 to 0 needs adding or subtract Only transitions from 0 to 1 or 1 to 0 needs adding or subtract

operations as follows:operations as follows:• If two consecutive bits in the second operand are:If two consecutive bits in the second operand are:

• 0 and 0 - shift the partial result to the right0 and 0 - shift the partial result to the right• 0 and 1 – add second operand and shift the partial result to the right0 and 1 – add second operand and shift the partial result to the right• 1 and 0 – subtract the second operand and shift the partial result to the 1 and 0 – subtract the second operand and shift the partial result to the

rightright• 1 and 1 - shift the partial result to the right1 and 1 - shift the partial result to the right

DivisionDivision Multiple solutions:Multiple solutions:

Compare and subtractCompare and subtract• Hard to compare on different positionsHard to compare on different positions

Subtract and restore the partial result (if necessary)Subtract and restore the partial result (if necessary)• Subtract the second operand from the most significant part of the Subtract the second operand from the most significant part of the

first operand and first operand and If the result is positive than its ok (quotient gets a 1),If the result is positive than its ok (quotient gets a 1), Else restore the result by adding back the second operand (quotient Else restore the result by adding back the second operand (quotient

gets a 0) gets a 0) Drawback: some steps require 2 arithmetical operations (subtract and Drawback: some steps require 2 arithmetical operations (subtract and

adding)adding) Subtract without restoring the partial resultSubtract without restoring the partial result

• try to subtract B from the partial rest R’=R-Btry to subtract B from the partial rest R’=R-B• If a wrong subtraction was made in the previous step the correction If a wrong subtraction was made in the previous step the correction

is made in the next step by adding the second operand instead of is made in the next step by adding the second operand instead of subtracting itsubtracting it

• With correction: ((R-B) With correction: ((R-B) +B+B)*2 - B = R*2 - B ; A shifted one position )*2 - B = R*2 - B ; A shifted one position to the leftto the left

• Without correctionWithout correction(R – B)*2 (R – B)*2 ++ B = R*2 – B B = R*2 – B• Advantage: in a step at most one subtraction or adding is neededAdvantage: in a step at most one subtraction or adding is needed

Division circuit for the second Division circuit for the second method – restoring the partial resultmethod – restoring the partial result

Adding, SubtractionCommand unit

X

Q0Q1Q n-1 . . .

B0B1Bn-1 . . .BS

A0A1An-1 . . .AS

Q S

Y

Add / Sub

Division algorithm – with restoring Division algorithm – with restoring the partial resultthe partial result

1. Load first operand in A and Q; Load second operand in B2. Write AS + BS in QS.

If AS = 1, complement A, Q If BS = 1, complement B

3. Tests:1. A ≥ B, overflow2. B = 0, division with 03. A = 0 and Q < B, rezult = 0

4. Shift A, Q to the left and put 0 in Q0

5. Subtract B from A and put the result in A. if AS = 0 (positive rest) , shift A, Q to the left and put 1 in Q0 else (AS = 1 negative rest), add B to A, shift A, Q to the left and put 0 in Q0

Go to step 5 n times Rounding the result. If A ≥ B, add 1 to the Qth complement If QS = 1 complement register Q

Multiply with look-up tablesMultiply with look-up tables Principle: all the results are pre-computed and memorized in a non-Principle: all the results are pre-computed and memorized in a non-

volatile memoryvolatile memory Multiply is a simple reading from the memoryMultiply is a simple reading from the memory Operands form the address of the location where the result is storedOperands form the address of the location where the result is stored Problem: the dimension of the memory must be 2Problem: the dimension of the memory must be 22n2n

Examples: Examples: • 8*8 bits => 16 address lines => 28*8 bits => 16 address lines => 21616 = 64KB = 64KB• 16*16 bits => 32 address lines => 216*16 bits => 32 address lines => 23232 = 4GB (TOO MUCH) = 4GB (TOO MUCH)

Solution:Solution:• Multiply 8*8 bits in multiple steps to obtain multiply on 16, 32 or 64 bitsMultiply 8*8 bits in multiple steps to obtain multiply on 16, 32 or 64 bits• Example:Example:X= XX= X15,815,8 X X7,0 7,0 Y= YY= Y15,815,8 Y Y7,07,0

P = X*Y = XP = X*Y = X7,07,0*Y*Y7,0 7,0 + X+ X15,815,8*Y*Y7,0 7,0 *2*28 8 + X+ X7,07,0*Y*Y15,8 15,8 *2*28 8 + X+ X15,815,8*Y*Y15,8 15,8 *2*216 16

Observation: multiplies with 2Observation: multiplies with 28 8 and 2and 21616 are achieved by placing the result in a are achieved by placing the result in a proper binary position; also the first and the last partial products may be proper binary position; also the first and the last partial products may be combined in a single 32 bit register with no adding requiredcombined in a single 32 bit register with no adding required

Multiply with look-up tableMultiply with look-up table

X15,0

Y15,0

X15,8

Y15,8

Y7,0

X7,0

A15,0 D15,0Memory

Look-up table

MUX

MUX

MUX

Accumulator

AdderControl unit

XX15

,815

,8*Y*Y

15,8

15,8

XX7,

07,

0*Y*Y

7,0

7,0

XX15

,815

,8*Y*Y

7,0

7,0

XX7,

07,

0*Y*Y

15,8

15,8

Sel1 Sel0

Sel2

WrX

WrY

WrAcc

WrP1,2 WrP0 WrP3

Multiply with look-up tableMultiply with look-up tableStepStep WrWrXX WrWrYY WrWrP0P0 WrWrP1,2P1,2 WrWrP3P3 WrWrAccAcc SelSel00 SelSel11 SelSel22 DescriptionDescription

11 11 11 00 00 00 00 00 00 00 Load operandsLoad operands

22 00 00 11 00 00 00 00 00 00 Write P0Write P0

33 00 00 00 00 11 00 11 11 00 Write P3Write P3

44 00 00 00 11 00 00 11 00 00 Write P1Write P1

55 00 00 00 00 00 11 00 11 00 Acc=P0+ P3 +P1Acc=P0+ P3 +P1

66 00 00 00 11 00 00 00 11 00 Write P2Write P2

77 00 00 00 00 00 11 00 00 11 Acc=Acc+P2Acc=Acc+P2

Multiply with look-up table requires only 7 steps instead of 16-20 Multiply with look-up table requires only 7 steps instead of 16-20 it can be further optimizedit can be further optimized

Arithmetical operations in Arithmetical operations in floating point (FP) representationfloating point (FP) representation

Floating point representation of a number:Floating point representation of a number: Used in case of very big or very small numbersUsed in case of very big or very small numbers 3 fields for representation: 3 fields for representation:

• SignSign• Exponent – magnitude of the numberExponent – magnitude of the number• Mantissa – some significant figures (digits) of the numberMantissa – some significant figures (digits) of the number

IT IS NOT THE REPRESENTATION OF REAL IT IS NOT THE REPRESENTATION OF REAL NUMBERS from mathematics !!!!!NUMBERS from mathematics !!!!!

A lots of anomalies and precision problems:A lots of anomalies and precision problems:• Operating with numbers having different magnitudes may Operating with numbers having different magnitudes may

generate errors caused by rounding: generate errors caused by rounding: M+m-M = 0 ; M-M+m = mM+m-M = 0 ; M-M+m = m

• Number with decimal parts, in most cases have no precise Number with decimal parts, in most cases have no precise FP representationFP representation

Example: 0.3 has no precise representation in floating pointExample: 0.3 has no precise representation in floating point

Floating point adder/ subtracterFloating point adder/ subtracter

Add & subtractCompareControl unit

exponent mantissaS

mantissaexponentS

Inc/DecShift right

Inc/DecShift right

<=>

Add/Sub

X

Y

Adding floating point numbersAdding floating point numbers1.1. Load the operandsLoad the operands2.2. Compare exponentsCompare exponents (5 cases):(5 cases):

eexx = e = eyy, , add mantissas and copy the exponentadd mantissas and copy the exponenteexx > e > eyy andand (e (exx – e – eyy) < ) < number of bits in the mantissanumber of bits in the mantissa, , than the than the my my mantissa is mantissa is

aligned by shifting it with aligned by shifting it with ex-ey ex-ey positions to the right; positions to the right; eexx >> e >> eyy andand (e (exx – e – eyy) ≥ ) ≥ number of bits in the mantissanumber of bits in the mantissa, , than X is copied in the than X is copied in the

result (Y is too small); go to step 4result (Y is too small); go to step 4eexx < e < eyy andand (e (eyy – e – exx) < ) < number of bits in the mantissanumber of bits in the mantissa, , than the than the mmxx mantissa is mantissa is

aligned by shifting it with aligned by shifting it with eeyy-e-ex positions to the right; than mantissas are x positions to the right; than mantissas are addedadded

eexx << e << eyy andand (e (eyy – e – exx) ≥ ) ≥ number of bits in the mantissanumber of bits in the mantissa, , than Y is copied in the than Y is copied in the result (X is too small); go to step 4result (X is too small); go to step 4

Add mantissasAdd mantissas Realign the result if necessaryRealign the result if necessary. . Shift the resulting mantissa to the Shift the resulting mantissa to the

right or to the left until the integer part is 0 and the first bit after the right or to the left until the integer part is 0 and the first bit after the decimal point is 1; in the same time increment or decrement the decimal point is 1; in the same time increment or decrement the exponent in accordance with the shifting operationexponent in accordance with the shifting operation

Multiply and division in floating Multiply and division in floating point representationpoint representation

Multiply:Multiply: Add the exponentsAdd the exponents Multiply the mantissasMultiply the mantissas Adjust the result (shift mantissa to the left and Adjust the result (shift mantissa to the left and

decrement the exponent if necessary)decrement the exponent if necessary) Division:Division:

Subtract the exponentsSubtract the exponents Divide the mantissasDivide the mantissas Adjust the result (if necessary)Adjust the result (if necessary)

Add and Subtract with saturationAdd and Subtract with saturation Idea: if there is an overflow or underflow after an adding or subtraction the result Idea: if there is an overflow or underflow after an adding or subtraction the result

should be the maximum or the minimum possible value should be the maximum or the minimum possible value example:example:

unsigned 8 bit representationunsigned 8 bit representationNormal adding (wraparound)Normal adding (wraparound) With saturationWith saturation80h+90h = 10h (error, overflow)80h+90h = 10h (error, overflow) 80h+90h = FFh (maximum value)80h+90h = FFh (maximum value)80h-90h = F0h (underflow)80h-90h = F0h (underflow) 80h-90h = 00h (minimum value)80h-90h = 00h (minimum value)

signed (2th complement) 8 bit representationsigned (2th complement) 8 bit representationNormal adding (wraparound)Normal adding (wraparound) With saturationWith saturation70h+20h = 90h (error, negative)70h+20h = 90h (error, negative) 70h+20h = 7Fh (maximum value)70h+20h = 7Fh (maximum value)80h-20h = 60h (error, positive)80h-20h = 60h (error, positive) 80h-20h = 80h (minimum value)80h-20h = 80h (minimum value)(-128-32 = 96)(-128-32 = 96)

Used in case of:Used in case of: signal processingsignal processing multimedia processingmultimedia processing

Typical signal processing operation: amplification Typical signal processing operation: amplification UUee = U = Uii *A *A

Supply: +10V;-10V, USupply: +10V;-10V, U ii=0.05 V; A=100 =>U=0.05 V; A=100 =>Uee = 5V = 5V UUii=1.00 V; A=100 =>U=1.00 V; A=100 =>Uee = 10V !!! – upper saturation = 10V !!! – upper saturation

1

2

R

RA

UUiiUUee

R2

R1

Add and Subtract with saturationAdd and Subtract with saturation

MUX

Add&Sub

FF 00

3 2 1 0

Add/Sub

S1

S0

X7,0 Y7,0

S7,0

Carry

CC Add/Add/SubSub

OperationOperation ResultResult SS11 SS00

00 00 addingadding Correct X+YCorrect X+Y 11 XX

00 11 subtractsubtract Correct X-YCorrect X-Y 11 XX

11 00 addingadding Overflow FFhOverflow FFh 00 11

11 11 subtractsubtract Underflow 00hUnderflow 00h 00 00

Add and subtract with saturation for unsigned 8 bit representationAdd and subtract with saturation for unsigned 8 bit representation the result is selected with a multiplexer:the result is selected with a multiplexer:

Carry (C) = 0 => result correctCarry (C) = 0 => result correct C=1 and adding => overflow, result=FFhC=1 and adding => overflow, result=FFh C=1 and subtract => underflow, result=00hC=1 and subtract => underflow, result=00h

homework: do it for 2th complementhomework: do it for 2th complement

SS00 00 11

00 XX XX

11 11 00

Add/Sub

C

SS11 00 11

00 11 11

11 00 00

Add/Sub

C