stt-ram feasibility study
DESCRIPTION
STT-RAM Feasibility Study. Amr Amin UCLA Jan 2010. Outline. Introduction Memory Cell Cell Area Calculation Write Current Limitations Reading Techniques and Limitations Effect of Process Variations and Mismatch MTJ Feasible Region Area Minimization. Introduction. - PowerPoint PPT PresentationTRANSCRIPT
STT-RAM Feasibility Study
Amr Amin
UCLA
Jan 2010
Outline
• Introduction• Memory Cell• Cell Area Calculation• Write Current Limitations• Reading Techniques and Limitations• Effect of Process Variations and Mismatch• MTJ Feasible Region• Area Minimization
Introduction
• The need for a universal memory
• Brief history of magnetic device memories
• Description of the MTJ device
• Literature survey
• …
• …
• Summary of the paper flow
STT-RAM Cell
• Schematic diagram
• Anti-parallelizing / Parallelizing currents
• Read disturb problem
• Cell layout
• Basic cell area vs. access device width
Effective Cell Area
• This takes into account the overhead of:– Column MUX– Row decoder– Sense Amp– I/O circuits
• Area optimization should also consider:– Optimum memory partitioning– Access transistor vs. column MUX areas
Write Current Limitations
• MOS drain current equation and fitting
• Maximum allowed RP and RAP for certain write current(s)
• Column MUX design (justification for using T-gates instead of P-transistors)
• Effect of each of the four MUX devices on the maximum allowed resistances
NMOS Drain Current
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-200
0
200
400
600
800
1000
1200
1400
1600
Vds (V)
Id (
A)
NMOS Simple Theoritical Model
Vgs=0.8VVgs=0.9V
Vgs=1.0V
Vgs=1.1V
Vgs=1.2VVgs=1.3V
Vgs=1.4V
Vgs=1.5VVgs=1.6V
Vgs=1.7V
Vgs=1.8V
Vgs=1.9VVgs=2.0V
PMOS Drain Current
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-100
0
100
200
300
400
500
600
700
Vds (V)
Id (
A)
PMOS Simple Theoritical Model
Vgs=0.8VVgs=0.9V
Vgs=1.0V
Vgs=1.1V
Vgs=1.2VVgs=1.3V
Vgs=1.4V
Vgs=1.5VVgs=1.6V
Vgs=1.7V
Vgs=1.8V
Vgs=1.9VVgs=2.0V
Maximum RAP
VG
VG
VG
VDD
RAP
X
IP
MN2
MP1
MN1
MP2
Ma
0 500 1000 1500 20000
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
RA
P,M
AX (
)
Maximum Antiparallel Resistance (RAP
)
Analytic
Simulation
Maximum RP
VG
VG
VDD
X
MN1
MP2
MN2
MP1
VG
IAP
Ma
RP
0 500 1000 1500 20000
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
RP,
MA
X (
)
Maximum Parallel Resistance (RP)
Analytic
Simulation
Constant ‘Read’ Signal Contours• Current Sensing • Voltage Sensing
0 500 1000 1500 20000
200
400
600
800
1000
1200
1400
1600
1800
2000
RP ()
RA
P (
)
Contours of Constant Read Current Signal
IR = 0 A
IR = 20 A
IR = 40 A
IR = 60 A
IR = 80 A
IR = 100 A
IR = 120 A
0 500 1000 1500 20000
200
400
600
800
1000
1200
1400
1600
1800
2000
RP ()
RA
P (
)
Contours of Constant Read Voltage Signal
VR = 0 mV
VR = 20 mV
VR = 40 mV
VR = 60 mV
VR = 80 mV
VR = 100 mV
VR = 120 mV
Process Variations
• MOS variations:– Min K and max VT
– Reduce the maximum allowed RP and RAP
– Decrease the ‘read’ signal (decreasing IR or VR)
• Mismatch:– Degrades sensitivity of the SA– Higher nominal read signal is required
• MTJ variations:– MgO thickness and area variations– Distort the nominal feasible region of the MTJ
Process Variations nomMgORAnom ttKRARA
0 500 1000 1500 20000
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
RP,
MA
X (
)
Maximum Parallel Resistance (RP)
Nominal
/w 25%-K and 100mV-VT
/w 0.5Ao MgO Variation
Nominal: Sim
0 500 1000 1500 20000
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
RA
P,M
AX (
)
Maximum Antiparallel Resistance (RAP
)
Nominal
/w 25%-K and 100mV-VT
/w 0.5Ao MgO Variation
Nominal: Sim
nomMgOTMRnom ttKTMRTMR
MgOnom
RA
P
P tRA
K
R
R
MgO
nom
TMR
nom
RA
AP
AP tTMR
K
RA
K
R
R
1
MTJ Feasible Region
• What is the MTJ feasible region in the RP RAP plan given the following:
– Desired write current– Desired basic cell area– Column MUX width– Certain technology– Certain variations (Yield)– Matching parameters (Yield)
Dec-2009 Tape-out• IBM-90nm-CMOS• VWL = VDD = 1 V• IWR = 500 μA• Wa=2.56 μm• WP,MUX=16 μm• WN,MUX=8 μm• MOS K varies +/- 20%• MOS VT varies +/- 50mV• MTJ: RA = 2 Ω.μm2
• MTJ: KRA = 34 Ω.μm2/nm• MTJ: TMR = 100% • MTJ: KTMR = 200 %/nm• MTJ: ΔtMgO = 0.2 Ao
• Current Sensing: VR= 600 mV• Current Sensing: ΔIR= 20 μA 0 500 1000 1500 2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
RP ()
RA
P (
)
MTJ Feasible Region
Typical
MOS Variations
MOS & MTJ Variations
SRAM-Area Constraint
Flash-Area Constraint
DRAM-Area Constraint
Area Minimization Problem
• Minimize: Effective cell area• Subject to:
– MTJ resistances and write current value– MTJ variations– Parallelizing/Anti-parallelizing Write current equations– MOS variations and matching parameters– Speed must come into picture to constrain the
optimum memory partitioning
• May be able to formulate this into a standard optimization problem form that can be solved efficiently
Remaining Issues
• Analyzing Read/Write Speed and adding this as a constraint in the optimization problem
• The same with power
• More analysis is needed for the minimum required sensing signal (current or voltage)– CMOS mismatches and offset– Signal degradation due to MgO thickness variation– Possible signal degradation due to CMOS process variation
(dependant on the SA implementation)
• Regenerating all results for different technologies