study 45nmmosfet

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NANOSCIENCE & MICROElECTRONICSNANOTECHNOLOGY 1 OALISCO B) &MEMS (JAUSCOO

[NSN-52] Wave propagation in periodic [MEM-14] Characterization of a

15:20 ~odic structures. Jose Luis Arag6n differential variable capacitor build on[ D] P.oLYMUMPS process. Ivan Javier Munoz

Cano, Juan Luis Ibarra, Jose Mireles Jr.

[NSN-39]SPI.oNs the future for cancer [MEM-06] A data ac'}.uisition system fornanotherapy. Jaime Santoyo Salazar integrated biosensor m 0.5 um CM.oS

15:40 techDolojP'. Juan Manuel G6mez Cruz,Zaid MOiSes Morales Martinez, AnnelKrisali Hurtado .orozco, Esteban MartinezGuerrero

[MEM-12] Simulation and

16:00characterization of a parallel t/ate variablecapacitor fabricated with SU MiTV

[NSN-44] Effect of m~etite and ftocess. Juan Luis Ibarra D., Ivan Munoz,maghernite nanopartic es on radish ustavo Lara, Jose Mireles Jr.Kirmination. Nicolaza Pariona, Arturo I. [MEM-07] Modeling and simulationartinez, Roman Castro- Rodriguez of micro£luids in microchannels for

16:20 ctlications in micro fuel cells. Casimiroomez Gonzalez, Sonia Lizeth Ramos

Pedr6n

16:40 COFFEE

[NSN-27] Effect of e1ectror,inning [MEM-03] Study of 45 nmPD SOlvol~ on the formation 0 micro bers M.oSFET under forward bias using 2DofPo:fo:inJt.l{'yrrolidone. Jose Alfredo simulation. Abimael Jimenez P., Roberto

17:00 Pesca or 0jas, Jose Francisco Sanchez c. Ambrosio L., Jose Mireles G., KarimRamirez, Alejandro Bautista Hernandez, Monfil L., Zurika BlancoEmesto Chigo Anota, JesUs AntonioFuentes Garda

[NSN-17] Reinforcement with [MEM-17] Pressure microsensor onnanopartides of a liquid aluminum based integrated optics. Marco Antonio

17:20 alloy. Salom6n Rojas Trevino, Ana Maria Ramirez Barrientos, Aurelio HoracioArizmendi Mor,;echo, Roberto Martinez Heredia Jimenez, Laura Josefina Castro YSanchez, Ser~io arda Villarreal, Fernandez del CampoA1ejandra C avez Valdez

[NSN-07] Modification of Multi- Walled [MEM-IO] .ostimization and exr,erimentCarbon Nanotubes Usin~ Acetic Acid rocedure of eep dry etchin~ 0 siliconand Aniline by U1trasomc Radiation. or MEMS development in exico. Jose

17:40 Christian Javier Cabello Alvarado, Aide Mireles Jr., HoraclO Estrada, RobertoSaenz Galindo, Catalina Perez Berumen, Carlos Ambrosio, Abimael Juimenez, JuanL1uvia L6pez L6p~ Leticia Barajas Luis Ibarra, Ivan Javier MunozBermudez, Carlos Avila .orta, JanettValdez Garza

[NSN-05] H2 ads0d:tion and storage [MEM-08] The electrical thermal andinside and outside e C120 nanotorus mechanical response of a:CH filmeffect of Be, Sc and Ca, atoms on the t,ezoresistor for tensile stress. Luiz

18:00 molecular hydrogen adsor£tion. Juan tonio RasiaSalvador Arellano, Arman 0 Cruz- Torres,Jaime .ortiz- L6£ez, Fray de LandaCastillo- A1vara 0

PLENARY 9 (JALISCO A)

18:20Innovative Design Concepts in Nanocomposite Coatings for

Ali Erdemir

19:00 BANQUET

I I

COURSE 7 (JALISCO - A)

EllipsometryJuan Antonio Zapien

COFFEE

EllipsometryJuan Antonio Zapien

Extreme Tribological Applications

Study of 45nm PD-SOI MOSFETsunder Forward Bias Using 2D Simulation

A. Jimeneza

R. Ambrosioa, K. Monfila, C. Martineza, J. Munozb, Z. Blanco.aUniversidad Autonoma de Ciudad Juarez.

bUniversidad de Guadalajara.

September, 2011

Abimael Jimenez Perez IV International Conference on Surfaces, Materials and Vacuum 1/ 16

Overview

Motivation and Background

Objectives

Simulation Details

Results

Conclusions


Moore’s Law

Figure: 90nm, 65nm, 45nm, 32nm technology nodes

Revolutionary technologies on a chip

Strained silicon and hafnium-based gate-last high-k metal gate, in-troduced in the 45nm process.


Moore’s Law

Figure: Structure and technology innovation for MOSFETs

CMOS technology

• The limit for SIO2 → 1 nm

• Dielectrics with high k = HfO2, ZrO2

• Polysilicon → metal


Partially Depleted - Silicon On Insulator

SOI transistor is known as a substitute for conventional silicontechnology.Disadvantage instability, such as hysteresis and self-heatingeffect.Several techniques for body-contact have been developed.PD-SOI Dynamic Threshold MOSFET (DTMOS) results in ahigher current drive than that of bulk CMOS.PD-SOI DTMOS is made by connecting the MOSFET gate toits floating body.

Figure: PD-SOI DTMOS Structure


Applications

?

Figure: DTMOS Based Low Power High SpeedInterconnects for FPGA. Kureshi A. K. and Mohd H.,Journal of Computers, Vol 4, No 10 (2009), 921-926.

Figure: The proposed diodes use DTMOStransistors. The idea of their operation is based onthe connection of the gate, the drain and the bulk ofthe transistor together in order to obtain diodes withlow-threshold voltage. Integrated power harvestingsystem including a MEMS generator and a powermanagement circuit, Marzencki, M., et. al.,International Solid-State Sensors, Actuators andMicrosystems Conference, pp. 887-890, 2007.


Objective

General objective

Analysis and simulation of PD-SOI MOSFETs under forward bias, in-corporating HfO2 dielectrics and metal gates. The analysis is basedon a physical study and 2D simulation, paying special attention tothe correct modeling of the principal parameters of MOSFET.


Simulation Details

Synopsys TCAD simulation

NA = 1.6x1018 cm−3, Tbox = 400nm and Tox = 15nm. Thestructure shows a body contact used for forward biasing the body.


Results

VBS was swept from 0 to0.8 V.

For VBS = 0.8V theSource SBJ turns on anda large quantity of mobilecharge is injected to thedepletion region. 0.0 0.2 0.4 0.6 0.8 1.0

0

10

20

30

40

0

VBS

Dra

in C

urre

nt,

A

VGS

, V

Lg=45nm

0.8

DTMOS operation

DTMOS normally requires gate to body voltages below 0.7 V. Theinjection of mobile carriers should be considered.


Results

0.0 0.2 0.4 0.6 0.80.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

Lg = 45nm Lg = 0.5 m

VT

H,

V

VBS, V

Linear Extrapolation Method Drain Current Method

The drain current methodpredicts the lowest VTH.

However both methodspresent the square rootbehavior and shortchannel effects reductionas forward bias isincreased.

Threshold Voltage

One of the key design parameters in CMOS technology is the thresh-old voltage (VTH).


Results

0.0 0.2 0.4 0.6 0.8 1.010-9

10-8

10-7

10-6

10-5

10-4

0

10

20

30

40

50

60

70

80

90

gm,

A

/V

Log

(ID

S),

A

VGS, V

VBS

0.8 V

0 V

0.8 V

0 VVBS

Lg = 45 nmW = 0.5 m

gm = ∂IDS∂VGS

As expected, curvefamilies shift to the left asVBS increases in theforward direction.

For an increasing forwardsubstrate bias we observea lower threshold voltageas well as theimprovement of thetransistor gain.

Transconductance

The perpendicular electric field and the mobility degradation arereduced as forward body bias is increased as a result of this, thebehavior of gm and fT are improved.


Results

As the channel lengthshortens and the VDSincreases, the barrierlowering between thesource and φsmin(y0)increases, thus the DIBLeffect is increased.

Nevertheless, underforward bias DIBL effectis reduced compared witha MOSFET.

Potential

The DIBL effect is present in short channel devices when VDS affectsthe channel potential profile, lowering the barrier at the Source-Bodyjunction.


Results

-qVGB

n+ poly-Si p substrate

(a) Inversion (b) Accumulation

qVGB

e-

e-h+

n+ poly-Si p substrate

h+

e-

e-

h+

IG

The higher gate current not only increases the standby power con-sumption of a highly integrated CMOS circuit, but also can adverselyaffect MOSFET performance.


Conclusions

Conclusions

• We have investigated the performance of short PD-SOIMOSFETs with Poly/SiO2 and Ti/HfO2 gate stacks.

• The forward biasing voltage can be kept to values below 0.6 Vsince the SBJ turns on for higher values; nevertheless, ahigher VBS may be desirable in order to further improve thetransistor gain, then setting a trade-off between theseparameters.

• As the actual dielectric thickness is decreased, the direct gatetunneling current increases.

• The current circuital models must be improved by consideringthe effects of the actual surface potential and the mobilecharge density.


References

1 M. Maymandi-Nejad and M. Sachdev, DTMOS Technique for Low- Voltage Analog Circuits, IEEETransactions on Very Large Scale Inte- gration (VLSI) Systems, vol. 14, no. 10, pp.1151-1156, 2006.

2 S. L. Jang and Ch. F. Lee, A Low Voltage and Power LC VCO Imple- mented With Dynamic ThresholdVoltage MOSFETS, IEEE Microwave and Wireless Components Letters, vol. 17, no. 5, pp.376-378, 2007.

3 H. Singh, R. Rao, K. Agarwal, D. Sylvester and R. Brown, Dynamically Pulsed MTCMOS With BusEncoding for Reduction of Total Power and Crosstalk Noise, IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, vol. 18, no. 1, pp. 166 - 170, 2010.

4 F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, Ping K. Ko, and Ch. Hu, A Dynamic Threshold VoltageMOSFET (DTMOS) for Ultra-Low- Voltage Operation, IEEE Electron Device Lett., vol. 15, no.12, pp.510- 512, 1994.

5 D. Kumar, P. Kumar and M. Pattanaik, Performance Analysis of Dynamic Threshold MOS (DTMOS)Based 4-Input Multiplexer Switch for Low Power and High Speed FPGA Design, Proceedings of the 23rdSymposium on Integrated Circuits and System Design, NY, USA, 2010.

6 W. C. H. Lin and J. B. Kuo, Low-Voltage SOI CMOS DT- MOS/MTCMOS Circuit Technique for DesignOptimization of Low- Power SOC Applications, Proceedings of 2010 IEEE International Sym- posium onCircuits and Systems (ISCAS), pp. 3833 - 3836, Paris, 2010.

7 V. Niranjan and M. Gupta, An Analytical Model of the Bulk-DTMOS Transistor, Journal of ElectronDevices, vol. 8, pp. 329-338, 2010.


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study 45nmmosfet

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