study of cmos rectifiers for wireless energy scavenging

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Study of CMOS Rectifiers for Wireless EnergyScavenging

Examensarbete utfört i Elektroniska komponentervid Tekniska högskolan i Linköping

av

Aiysha Ali Khalifa

LiTH-ISY-EX--10/4359--SE

Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Study of CMOS Rectifiers for Wireless EnergyScavenging

Examensarbete utfört i Elektroniska komponentervid Tekniska högskolan i Linköping

av

Aiysha Ali Khalifa


Handledare: Atila Alvandpourisy, Linköpings universitet

Examinator: Atila Alvandpourisy, Linköpings universitet

Linköping, 21 November, 2010

Avdelning, InstitutionDivision, Department

Division of Electronic DevicesDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

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2010-11-21

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URL för elektronisk versionhttp://www.ek.isy.liu.se

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TitelTitle

Trådlös Energi SophanteringStudy of CMOS Rectifiers for Wireless Energy Scavenging

FörfattareAuthor

Aiysha Ali Khalifa

SammanfattningAbstract

In recent years, there has been recent increase in the deployment of wireless sensornetworks. These sensors are typically powered by a battery which has limitedlife span. This problem can be overcomed by using energy scavenging or powerharvesting which is the process of converting ambient energy from the environmentinto usable electrical energy. It can be used in applications such as remote patientmonitoring, implantable sensors, machinery/equipment monitoring and so on. Thethesis presents the RF scavenging system and mainly focuses on the study of therectifier architectures which is one of the key components in the RF scavengingsystem. The thesis also provides the design challenges while implementing thedifferent rectifier structures, which are PMOS bridge rectifier, CMOS differentialrectifier and charge pump. The functionality of the rectifier structures are studiedby simulation using RF signal of 900 MHz and implemented in 0.35µm and 65 nmtechnologies to compare the results. The simulation results shows that there is atradeoff between high output DC voltage and high power efficiency.

Maximum DC output voltage of 1 V is obtained from input amplitude level of0.16 V using 7-stage charge pump rectifier. In the other hand maximum powerefficiency of 23 % is obtained using CMOS differential rectifier.

NyckelordKeywords Energy Scavenging, Rectifier

AbstractIn recent years, there has been recent increase in the deployment of wireless sensornetworks. These sensors are typically powered by a battery which has limitedlife span. This problem can be overcomed by using energy scavenging or powerharvesting which is the process of converting ambient energy from the environmentinto usable electrical energy. It can be used in applications such as remote patientmonitoring, implantable sensors, machinery/equipment monitoring and so on. Thethesis presents the RF scavenging system and mainly focuses on the study of therectifier architectures which is one of the key components in the RF scavengingsystem. The thesis also provides the design challenges while implementing thedifferent rectifier structures, which are PMOS bridge rectifier, CMOS differentialrectifier and charge pump. The functionality of the rectifier structures are studiedby simulation using RF signal of 900 MHz and implemented in 0.35µm and 65 nmtechnologies to compare the results. The simulation results shows that there is atradeoff between high output DC voltage and high power efficiency.

Maximum DC output voltage of 1 V is obtained from input amplitude level of0.16 V using 7-stage charge pump rectifier. In the other hand maximum powerefficiency of 23 % is obtained using CMOS differential rectifier.

v

Acknowledgments

Firstly, I would like to thank Allah for giving me the strength and blessings tocarry out this study.I would like to express my sincere gratitude to my examiner and supervisor AtilaAlvandpour for offering me this opportunity and giving me valuable guidance andencouragement throughout the work.I am grateful to Sara Qazi for been a great friend and supporter all along themaster studies.I am very thankful to my parents who have supported me unconditionally through-out my life.Finally, I express my gratitude to all who supported me in any respect during thecompletion of the master thesis.

vii

Contents

1 Introduction 31.1 Motivation for Energy Scavenging . . . . . . . . . . . . . . . . . . 31.2 Generic Block Diagram for Energy Scavenging . . . . . . . . . . . 41.3 Energy Scavenging Techniques . . . . . . . . . . . . . . . . . . . . 5

1.3.1 Piezoelectric energy scavenging . . . . . . . . . . . . . . . . 51.3.2 Solar energy scavenging . . . . . . . . . . . . . . . . . . . . 61.3.3 Thermoelectric energy scavenging . . . . . . . . . . . . . . . 61.3.4 Electrostatic energy scavenging . . . . . . . . . . . . . . . . 61.3.5 Electromagnetic energy scavenging . . . . . . . . . . . . . . 71.3.6 RF energy scavenging . . . . . . . . . . . . . . . . . . . . . 9

1.4 Comparison of Energy Scavenging Methods . . . . . . . . . . . . . 101.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . 11

2 RF Scavenging System 132.1 Near and Far Field Propagation . . . . . . . . . . . . . . . . . . . . 132.2 RF Power Transmission . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Link budget . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 System Overview of RF Scavenging System . . . . . . . . . . . . . 162.4 Rectification- RF to DC Conversion . . . . . . . . . . . . . . . . . 172.5 Critical Issues in RF Scavenging System . . . . . . . . . . . . . . . 18

2.5.1 Threshold of the scavenger . . . . . . . . . . . . . . . . . . 182.5.2 Power conversion efficiency . . . . . . . . . . . . . . . . . . 18

3 RF CMOS Rectifier Architectures 213.1 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.1 Conventional CMOS rectifier . . . . . . . . . . . . . . . . . 223.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.1 Dickson charge pump . . . . . . . . . . . . . . . . . . . . . 273.2.2 Voltage multiplier . . . . . . . . . . . . . . . . . . . . . . . 27

4 Simulation and Evaluation Results 314.1 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 Effect of input amplitude on output voltage and PCE . . . 324.1.2 Effect of transistor size on output voltage and PCE . . . . 334.1.3 Effect of frequency on PCE . . . . . . . . . . . . . . . . . . 35

ix

x Contents

4.1.4 Effect of load resistance on output voltage and PCE . . . . 364.2 Differential CMOS Rectifier . . . . . . . . . . . . . . . . . . . . . . 38

4.2.1 Effect of input amplitude on output voltage and PCE . . . 394.2.2 Effect of transistor size on output voltage and PCE . . . . 404.2.3 Effect of load resistance on output voltage and PCE . . . . 424.2.4 Effect of frequency on PCE . . . . . . . . . . . . . . . . . . 43

4.3 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.3.1 Effect of transistor size on output voltage and PCE . . . . 474.3.2 Effect of number of stages on output voltage and PCE . . . 484.3.3 Effect of frequency on output voltage and PCE . . . . . . . 49

5 Comparison of Results and Conclusion 51

Bibliography 53

List of Figures1.1 General block diagram of an energy harvesting system. . . . . . . . 41.2 Piezoelectric power generation [12]. . . . . . . . . . . . . . . . . . . 51.3 Diagram of electromagnetic power generator. . . . . . . . . . . . . 8

2.1 Communication link between base station ans sensor in passivelypowered sensor network. . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Block diagram illustrating the RF-DC power conversion system ina passively powered sensor. . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Diode-connected PMOS transistor. . . . . . . . . . . . . . . . . . . 17

3.1 Diode bridge rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 CMOS bridge rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . 223.3 MOS transistor transient equivalent circuits. . . . . . . . . . . . . . 223.4 Conventional CMOS rectifier circuit[21]. . . . . . . . . . . . . . . . 233.5 External-Vth-cancellation CMOS rectifier circuit[17]. . . . . . . . . 243.6 Self-Vth-cancellation CMOS rectifier circuit[21]. . . . . . . . . . . . 243.7 Differential-drive CMOS rectifier[21]. . . . . . . . . . . . . . . . . . 253.8 Rectifier formed by cascading N rectifying cells in series[14]. . . . . 263.9 Dickson charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 273.10 cascade charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 283.11 Single stage charge pump. . . . . . . . . . . . . . . . . . . . . . . . 28

4.1 PMOS bridge rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . 314.2 Output voltage dependence on input amplitude. . . . . . . . . . . . 324.3 PCE dependence on input amplitude. . . . . . . . . . . . . . . . . 334.4 Output voltage dependence on transistor size. . . . . . . . . . . . . 344.5 PCE dependence on transistor size . . . . . . . . . . . . . . . . . . 344.6 PCE dependence on operating frequency. . . . . . . . . . . . . . . 354.7 Output voltage dependence on load resistance. . . . . . . . . . . . 364.8 PCE dependence on load resistance. . . . . . . . . . . . . . . . . . 374.9 Schematic of differential CMOS rectifier. . . . . . . . . . . . . . . . 384.10 Output voltage dependence on input amplitude. . . . . . . . . . . . 394.11 PCE dependence on input amplitude. . . . . . . . . . . . . . . . . 404.12 Output voltage dependence on transistor size. . . . . . . . . . . . . 414.13 PCE dependence on transistor size. . . . . . . . . . . . . . . . . . . 414.14 Output voltage dependence on load resistance. . . . . . . . . . . . 424.15 PCE dependence on load resistance. . . . . . . . . . . . . . . . . . 434.16 PCE dependence on input amplitude at various frequencies. . . . . 444.17 7-stage charge pump test bench. . . . . . . . . . . . . . . . . . . . 464.18 Output voltage generated with and without load resistance. . . . . 464.19 Output voltage dependence on transistor size. . . . . . . . . . . . . 474.20 Output voltage for different number of stages. . . . . . . . . . . . . 48

5.1 Input amplitude vs output voltage for different rectifier architectures. 515.2 Input amplitude vs PCE for different rectifier architectures. . . . . 52

2 Contents

List of Tables1.1 Power density of different types of energy scavenging[22] . . . . . . 101.2 Comparison of the mechanical converters . . . . . . . . . . . . . . 11

4.1 Summary of the achieved result of the output voltage and PCE fordifferent values in 65 nm technology. . . . . . . . . . . . . . . . . . 37

4.2 Summary of the achieved result of the output voltage and PCE fordifferent values in 0.35 µm technology. . . . . . . . . . . . . . . . . 38

4.3 Summary of the achieved result of the output voltage and PCE fordifferent values in 65 nm technology . . . . . . . . . . . . . . . . . 45

4.4 Summary of the achieved result of the output voltage and PCE fordifferent values in 0.35 µ m technology. . . . . . . . . . . . . . . . . 45

4.5 Summary of the achieved result of the output voltage and PCE fordifferent values in 65 nm technology. . . . . . . . . . . . . . . . . . 49

4.6 Summary of the achieved result of the output voltage and PCE fordifferent values in 0.35 µm technology. . . . . . . . . . . . . . . . . 49

Chapter 1

Introduction

1.1 Motivation for Energy ScavengingThe vast advancement of wireless technology and low power electronics have in-creased the deployment of wireless sensor nodes. Batteries have been the primarysource of power for the wireless sensor. As the technology scales down, it is ex-pected that the size of the battery decreases. However, the battery technology hasevolved very slowly compared to electronic devices [18]. The limited life time andlarge physical dimension introduce an unwanted maintenance burden of replace-ment or recharging. The greatest potential however, lies in a new class of devicesthat will be battery-free and thus enable applications that would have been pro-hibitively expensive due to the maintenance cost and repeated battery replacement[18]. It is highly desirable to have an alternate power sources which overcome theabove limitation. This limitation can be solved through energy harvesting.

Power harvesting or energy scavenging is the process of acquiring ambient en-ergy from the surrounding environment (vibration, thermal energy, light energy orRF radiation) and converting it to a usable electrical energy. The potential benefitof energy harvesting mechanism is that the life time of the electronic sensor is notlimited by the life time of the energy source. However, most of the harvestableenergy sources are not continuous due to the variation of the environmental con-ditions. Thus the amount of energy harvested may not be sufficient to power theelectronic sensor node. Hence, it is necessary to accumulate the energy for furtheruse and also the electronic device should have low power consumption. The com-bination of an energy harvester with a small-sized rechargeable battery or otherstorage device is the best approach to power electronic sensor node over the entirelifetime.

3

4 Introduction

1.2 Generic Block Diagram for Energy Scaveng-ing

Figure 1.1. General block diagram of an energy harvesting system.

The four main building blocks of an energy harvesting system:

• Transducer

The transducer converts a harvestable energy which can be in the form of solarenergy, thermal energy, vibration or RF energy into electrical energy, through anantenna, solar cell, a piezoelectric device, or other various forms. The producedoutput from the transducer can be in a DC form or in AC form depending on theenergy source.

• Power conversion

The power conversion circuit can be a rectifier or DC-DC converter which canconverts the obtained energy into a usable DC voltage. The efficiency of thecircuit is an important factor which indicates the amount of the useful energy thatcan be utilized by the application.

• Power management

Depending on the application and the voltage available at the power conversioncircuit, the output voltage of the power conversion circuit can be regulated toa stable DC voltage using buck or boost converter or it can limited by voltagelimiter. The power management circuit controls the conduction path between thedevice and energy harvester [5].

• Charge storage

The charge storage is used to hold the charge and store it in a capacitor or arechargeable battery or other storage element. When selecting a rechargeable ele-ment, it is important to consider the ability of the battery/capacitor to withstand

1.3 Energy Scavenging Techniques 5

a high number of charge/discharge cycles and maintain its performance character-istics. Super-capacitors, traditional capacitors, and thin film batteries are knownfor their ability to retain performance even after a high number of charge/dischargecycles [22].

1.3 Energy Scavenging Techniques

Energy scavengers can be obtained from different energy sources, then convertedto the usable electrical energy using specific circuits. In this section some of theenergy scavengers are discussed:

1.3.1 Piezoelectric energy scavenging

Piezoelectric energy scavenger is one of the promising energy scavenging techniquesfor micro-power generators, which generates an electric charge as the result of aforce exerted on a piezoelectric material. Before subjecting the material to someexternal stress, its internal structure is in neutral. While exerting some pressure onthe material, its internal structure can be deformed which causes polarization of thematerial and hence, generates an electric field. Piezoelectric effect is the conversionof mechanical energy such as vibration into electrical energy. Piezoelectric effectis a reversible process where it also produces mechanical strain when electricalenergy is applied to the piezoelectric material. Due to these bi-directional effects,piezoelectric materials are widely used for making sensors and actuators [12]. Thewidely used piezoelectric material is Lead Zirconate Titanate (PZT).

Figure 1.2. Piezoelectric power generation [12].

The figure above shows the mechanical setup of a piezoelectric generator witha cantilever and proof mass, where the piezoelectric material is mounted on along thin cantilever beam and directly connected between the mass and the frame.When the beam/mass structure oscillates, the piezoelectric structure deforms andcauses a charge to be displaced across the capacitor electrodes positioned on thetop and bottom surfaces of the piezoelectric elements, a voltage then appears acrossthe capacitor and a current will flow through the load. The power generated fromthis system is proportional to the proof mass, to the square of acceleration, andinversely proportional to the resonant and excitation untitled folder frequency [12].

6 Introduction

Most conventional power supplies have low internal impedance, but the piezo-electric generator has high impedance. This restricts the amount of the outputcurrent which relatively reduces the output voltage, hence makes it challenging indesigning power conversion circuitry.

1.3.2 Solar energy scavengingPhotovoltaics(PV) is the direct conversion of light into electricity. Some mate-rials exhibit a property known as the photoelectric effect, that causes them toabsorb photons of light and release electrons. Movement of these free electrons re-sults in an electric current. PV cells are made of semiconductor materials such ascrystalline which behave as a voltage limited current source. The output currentdepends on the extent of light radiation, the size of the PV cell and on the timevarying load impedance as the PV cell has current source-like behavior. PV con-version has potentially long life time, higher output level (10mW/cm2) comparedto other types of energy harvesting. However, the varying light intensity affectsthe output power.

1.3.3 Thermoelectric energy scavengingThermoelectric energy scavenger makes use of the thermal energy that is ubiqui-tous in the environment. To harvest thermal energy, thermoelectric devices arerequired to convert the temperature difference between two junctions to electric-ity. The direct conversion of temperature difference to electric voltage and viceversa is called as thermoelectric effect. There are three kinds of thermoelectric ef-fects which include: the Seebeck effect, the Peltier effect and the Thomson effect.The Seebeck effect is responsible for the production of a voltage by a temperaturegradient.

By applying a temperature difference across the junctions of a conductingmaterial, a voltage V will be generated in the circuit,

V = αabδT (1.1)

where δT = (TH − TC) is the temperature difference across the two junctions andαab is the Seebeck coefficient. The generated voltage is proportional to the temper-ature difference across the junction, hence large thermal gradient is necessary toobtain reasonable voltage. The most attractive feature of a thermoelectric deviceis its capability of converting body heat into electricity which can power medicalimplants, wireless devices and other electronics devices. A successful example inthis attempt is the thermoelectric wristwatch developed by Seiko [2] and Citizen[1] are successful examples of thermoelectric generator which convert heat fromthe wrist into electrical energy. The thermoelectric generator produces a power ofat least 1.5µW when the temperature difference is in the range of 1◦C to 3◦C [15].

1.3.4 Electrostatic energy scavengingElectrostatic energy scavenger converts a mechanical energy into electrical energyby moving a part the pre-charged plate of capacitors. There are two possible


energy conversion cycles, charge constrained conversion and voltage constrainedconversion [16]. The conversion is based on which property (charge or voltage) isheld constant during the conversion process while the other changes in responseto a varying capacitance.

In charge constrained, the charge is held constant. Moving apart the capacitorplates due to the applied vibration decreases the capacitance, this necessarilyincreases the voltage across the device to maintain constant charge.

Qconst =12CV (1.2)

Increase in the voltage increases the net energy stored in the capacitor, as shownin the equation below,

E =12CV 2 (1.3)

However, the increased voltage can be very large compared to the breakdownlimit of the CMOS technology, for instance, a 100-to-1 pF variation produces a2.7-to-270 V change across the capacitor [16]

In the voltage-constrained method, the voltage across the capacitor is heldconstant. When the capacitance decreases due to separation of the plates of thecapacitor, the charge flows out of the capacitor.

Q =12CVconst (1.4)

Mechanical energy is required to move the capacitor plates, and thereby the chargethat flow out of the capacitor is harvested and stored for further use. However, tomaintain constant voltage in the capacitor, a voltage source is required, which isnot optimal,

1.3.5 Electromagnetic energy scavengingElectromagnetic energy harvesting is based on Faraday’s electromagnetic induc-tion. It converts mechanical energy into electrical energy. A coil is attached to anoscillating mass which traverses magnetic field produced by a stationary magnetas shown in the figure below:

When a coil travels through a varying magnetic flux, a voltage is induced. Sim-ilarly, a voltage is induced when the coil is kept fixed and the magnetic structure ismoved. The voltage or electromotive force (emf) induced in the circuit is directlyproportional to the time rate of change of flux linkage of the circuit.

V = −dφ

dt(1.5)

where, V is the induced voltage and Φ is the flux linkage. In this implementation,the circuit consists of a coil of multiple turns and permanent magnet which createsthe magnetic field. The voltage induced in N turns coil is given as:

V = −NdΦdt

(1.6)

8 Introduction

Figure 1.3. Diagram of electromagnetic power generator.

Φ = NBA (1.7)

where, N is the number of turns in a coil, B is the magnetic field flux densityover the area A. The voltage induced can also be expressed as the product of fluxlinkage and the velocity,

V = −NdΦdt

= −NdΦdt

dx

dt(1.8)

The power can be extracted by connecting the coil terminal to load resistanceRL and allowing the current to flow through it. The interaction between the fieldfrom the induced current and the magnetic field give rise to a force which opposesthe motion. By acting against the electromagnetic force Fem, the mechanicalenergy is converted to electrical energy. The electromagnetic force is expressed asthe product of electromagnetic damping Dem and velocity.

Fem = Demdx

dt(1.9)

The power extracted from the electromagnetic force is the product of the electro-magnetic force and the velocity.

P = Femdx

dt(1.10)

The power dissipated in the coil and load impedance is given as:

P =V 2

RL + Rc + jwLc(1.11)

where, Rc is the coil resistance and Lc is the coil inductance. Using equation 1.8,1.9, and 1.10 the electromagnetic damping can be given as:

Dem =N2(dφ

dt )2

RL + Rc + jwLc(1.12)


From the above equations, it is shown that to extract maximum power, theelectromagnetic damping must be increased, that is by maximizing the flux linkageand minimizing the coil impedance.

1.3.6 RF energy scavengingRF energy scavenger is one of the most popular power extraction methods for pas-sively powered devices. It harvest power from propagating radio frequency (RF)signals [6], which can be generated by cellular phones, local area network andother wireless devices. RF powered devices are often part of telemetry systemsto remotely measure and report data back to a central processing unit [6]. It isalso used in applications such as structural monitoring, access control, equipmentmonitoring and personal identification. Devices powered by propagating RF wavesare most often used in passive radio frequency identification (RFID) or passive RFtag[6][9]. The harvested power depends on the distance of the harvester from thepower source, another phenomenon like multipath fading, reflection and absorp-tion affect significantly the RF input power level. RF energy scavenging will bediscussed in detail in the later sections.

10 Introduction

1.4 Comparison of Energy Scavenging MethodsThe main performance metrics that are commonly considered when selecting anenergy harvester are:

• Power density

The harvestable energy source tends to provide highly fluctuating amount of en-ergy, hence, it is characterized by its power density as it depends on how longthe source is in operation [9]. The power density determines the life span of thedevice.

• Efficiency

The efficiency measures the effectiveness of the energy scavenging system in con-verting the environmental energy into electrical energy.

• Integration

It is the ability of the energy harvester to be integrated on a chip.

A comparison of different types of energy harvesting is given in Table 1.1.

Table 1.1. Power density of different types of energy scavenging[22]

Energy Source Characteristics Power Density Efficiency IntegrationRadio Frequency GSM 900 MHz 0.1µW/cm2 50% Easy

WiFi 2.4 GHz 1nW/cm2

Light Outdoor 100mW/cm2 10-50% PossibleIndoor 100 µW/cm2

Vibration Humans-Hz 6 µW/cm2 25-50% DifficultMachines-KHz 800 µW/cm2

Thermal Human 60 µW/cm2 0.1% DifficultIndustrial 100 mW/cm2 3%

The power density obtained from the solar energy has the maximum powerdensity, but it decreases with the variation of environmental condition. Since thepower density of the harvestable energy is not constant, it is necessary to storesignificant amount of the harvested energy to make it a feasible power source.

From the above harvestable energy, piezoelectric, electromagnetic and electro-static energy require mechanical energy (vibration) to provide electrical energy.The comparison of those mechanical converters is given in the table below.

1.5 Organization of the Thesis 11

Table 1.2. Comparison of the mechanical converters

Mechanism Advantage DisadvantagePiezoelectric No voltage source is required More diffcult to in-

tegrate in micro-systems

Electrostatic Easy to integrate in micro-systems Separate voltagesource is required

Electromagnetic No voltage source is required Difficult to operateat optimum condi-tion when the size isscaled down

1.5 Organization of the ThesisThe thesis discusses the design and study of RF-DC converter architectures andpresents some of the various energy scavenging methods. Chapter 2 discusses theRF scavenging system and how it is possible to transmit RF energy wirelessly. Italso discusses the parameters that affect the RF transmission and estimates theavailable RF energy required for harvesting using link budget.Chapter 3 discusses about rectification and the main parameters of the rectifier.Chapter 4 provides the various rectifier architectures and their analysis.Chapter 5 presents the simulation results of the rectifier architectures and theeffects of various parameters on the output voltage and on the power conversionefficiency of the rectifier.Chapter 6 provides the conclusions of this work.

Chapter 2

RF Scavenging System

In the earlier chapter various forms of harvestable energy have been discussed.One of the most popular power extraction methods for passively powered devicesis to harvest power from propagating radio frequency (RF) signals [6].

2.1 Near and Far Field Propagation

RF energy harvesting is widely used in passive RFID (Radio Frequency Iden-tification) system. Passive RFID stores and retrieve data via electromagnetictransmission to a radio-frequency compatible integrated circuit without using abattery. Energy transfer is the way by which passive RF devices are powered [3].The energy transfer mechanism is based on near-field propagation and far-fieldpropagation of electromagnetic waves. Near field propagation employ inductiveand capacitive coupling, where, inductive coupling is the transfer of energy be-tween two electronic circuits due to mutual inductance between them. Similarly,capacitive coupling is the transfer of energy between two electronic circuits due tomutual capacitance between them [3].

Inductive coupling uses the magnetic field produced by the information signalto induce current in a coiled antenna. The current induced charges the capacitorto provide the operating voltage and power for the device. Near field couplinggenerally operates in the LF (Low Frequency) and HF (High Frequency) bandwith relatively short reading distance. It has been used in transformers, electricmotors, medical telemetry, RFID and so on.

In far field coupling the antenna is comparable in size to the wavelength. Itis applicable for longer reading distances as it operates in UHF and microwavebands. In far field system, the propagation energy drops off rapidly with distance.

2.2 RF Power Transmission

RF powered devices harvest their power from RF wave radiation transmited from aradiant source or base station. Fig 2.1 illustrates the communication link between

13

14 RF Scavenging System

Figure 2.1. Communication link between base station ans sensor in passively poweredsensor network.

the radiating source which transmit RF signal and the multiple sensors. Themaximum power transmitted decreases as the distance from the transmitter andthe receiver increases. The operating range vary with the power contained in thewave transmitted, sensitivity of the receiving equipment, environment throughwhich the wave travels and presence of interferences. The transmitting station forRFID typically operates in the ISM band (industrial, scientific or medical) whichis controlled by FCC (Federal Communications Commission). FCC regulationslimit the amount of power that can be transmitted.

2.2.1 Link budgetTo estimate the available energy that can be carried by a RF signal and how muchof its energy can be harvested by the wireless device, it is essential to calculatethe power budget. Link budget accounts for all the gains and losses from thetransmitter through the medium to the receiver. Generally the received power iscalculated as,

received power[dBm] = Transmitted power[dBm]−Losses[dB]+Gains[dB] (2.1)

The amount of power that can be transmitted between 902 and 928 MHz ISMband is 30 dBm before the antenna according to FCC regulations. If 6 dB gain ofantenna is added, then the maximum allowed power is 36 dBm which correspondto 4 W. However, most of the power is lost in the transmission medium, which iscalled free space loss. The free space loss is governed by Friis transmission equationwhich gives an ideal estimate of the received powered, provided the transmittedpower and the operating distance from the transmitter to the receiver are known.

Pr = PtGrGt(λ

4πR)2 (2.2)

where, Pr and Pt are the received and the transmitted power respectively, Gr andGt are the antenna gain of the receiving and transmitting antenna respectively,

2.2 RF Power Transmission 15

λ is the wavelength of the transmitted signal and R is the distance between thetransmitter and the receiver. From the Friis formula, the free space loss is givenas:

FSL = (4πRf

c)2 (2.3)

For example if 900 MHz frequency and 10 m operating distance are used, then thefree space loss is found to be 51.52 dB. Thus the received power calculated fromthe above equation is -15.5 dBm corresponding to 28 µW. The estimated voltagethat can be received is less than 74 mV, if 50 ohm antenna is used.


2.3 System Overview of RF Scavenging System

Figure 2.2. Block diagram illustrating the RF-DC power conversion system in a pas-sively powered sensor.

Block diagram of the RF scavenging system is shown in figure 2.2. It illustratesthe method of conversion of ambient RF energy emitted by various sources suchas TV signal, wireless radio networks, base stations onto a feasible DC voltage.

The main components of RF energy scavenging system are:

• Antenna

The antenna design is critical in designing RF scavenging system since it mustcaptures RF signals generated by multiple RF sources. The antenna is designed tohave high gain and small return loss over wide range of frequencies. The antennashould also have a small size so it can be integrated on a chip.

• Matching network

As the received RF signal is very small, impedance matching between theantenna and the input of the rectifier circuit is required to obtain the maximumachievable power. Passive voltage amplification is also achieved by using high Qimpedance matching.

2.4 Rectification- RF to DC Conversion 17

• Rectifier

The harvested RF signal is converted into a DC voltage by using RF-to-DC con-verter (rectifier). It will be discussed in detail in later sections.

• Power Storage and Management

The ambient RF signal source is not always readily available, hence, it cannotprovide steady power all the time. Therefore, power management is required toprovide a regulated output voltage. The DC-DC converter is often used to providea regulated voltage or to boost the voltage level. The obtained DC voltage can bestored in a battery or a super capacitor for later use.

2.4 Rectification- RF to DC Conversion

An efficient power conversion system is required to convert power from the incidentelectromagnetic waves to a DC voltage. The rectifier is the basic part of the DCvoltage generation circuit, which comprises mainly of a diode. Large losses in therectifier must be avoided, because the typical output power of the energy harvester(antenna) is in the micro-watt range. It is also obvious that with decrease in powerlevel, the input voltage also decreases. Hence, it is challenging to build a rectifierthat extract very low level of power from the incident EM radiation.

In this thesis the focus is on CMOS rectifier. Diode is the main componentin a rectifier, which allows one-way flow of electrons. PN junction diode has athreshold voltage of 0.7 V, thus the input must exceed the threshold voltage tooperate the rectifier. Hence, this is not suitable for rectifying low level signals.Whereas, schottky diode has low threshold voltage, low conduction resistance,low junction capacitance, and large saturation current. However, Schottky diodeis incompatible with standard CMOS circuits. While implementation of CMOSrectifier, the diode is replaced by a diode-connected transistor i.e connecting thegate and the drain terminal. When considering a diode-connected PMOS, the

Figure 2.3. Diode-connected PMOS transistor.

substrate is connected to its source. When the source has a higher voltage thanthe drain, there will be a current flowing from source to drain, which means thatthe diode turns on when it is forward-biased. On the other hand, when drain hasa higher voltage than the source, the diode is reverse-biased. By connecting thesubstrate of PMOS to the highest voltage and substrate of NMOS to the lowestvoltage, the leakage currents and latch up can be avoided.


2.5 Critical Issues in RF Scavenging System

2.5.1 Threshold of the scavengerIn a CMOS rectifier circuit, the typical threshold voltage of a MOS transistorranges between 0.2-0.6 V. The power required to overcome the threshold voltagewith typical 50 ohm input impedance can be calculated from the equation below.

P =V 2

rms

R(2.4)

The power required to turn on the transistor translates to 0.4 mW to 3.6 mW,which corresponds to the dead zone of the rectifier. The minimum power requiredto overcome the rectification dead zone is called the power-up threshold of theharvester [4].

According to Friis equation, to obtain the required power to turn on the tran-sistor, the distance of operation is calculated to be 2.65 m-0.88 m at 900 MHzfrequency. Those distances are considered to operate in the near field. In orderto harvest power for longer operating distances, the threshold voltage should beminimized.

From the previous section, the maximum input voltage that can be receivedfrom 3.6 mW input power is 0.074 V, which is very small to turn on the CMOStransistor. There is also some other solutions used to reduce the threshold voltagewhich are the floating gate devices[13]. Impedance transformation boosts thevoltage level of the input signal, by employing matching network between theantenna and the rectifier circuit.

2.5.2 Power conversion efficiencyPower conversion efficiency (PCE) is defined as the ratio of the power dissipatedby the load to the total energy consumed by whole circuit. It can also defined asthe ratio of output DC power to the input RF power.

PCE =Pout

Pin∗ 100 (2.5)

The RF power available for extraction is in the range of micro-watt, thus it isrequired to utilize the power without losses. But according to maximum powertransfer theorem, half of the power is available for delievery to the load undermatched input conditions. Impedance matching network between the antennaand the rectifier increases the PCE of the system.

Chapter 3

RF CMOS RectifierArchitectures

The RF rectifier is a key component in a wireless sensor networks and RFIDapplications. It converts the input RF signal into DC voltage to power up thesystem. Rectifiers can be broadly categorized in two types, half wave rectifierand full wave rectifier. The simplest of all the rectifier circuits is the half-waverectifier which uses a single diode that conducts current in one direction. It isinefficient as it just uses one half of each complete sine wave of the RF signal toconvert it to a DC voltage. In the other hand, full wave rectifier makes use of thewhole input signal to deliver a DC signal. There are several ways of connectingdiodes to make a rectifier, but bridge rectifier is the most popular version. In thissection conventional CMOS bridge rectifiers and voltage multiplier are going to bediscussed.

3.1 Bridge Rectifier

A full wave bridge rectifier along with a capacitor converts both polarities of theinput signal to a DC signal. The arrangement requires four diodes as shown in fig3.1, whereby, a pair of diodes is responsible for rectification of each signal cycle.When the input voltage is higher than the output, a diode conducts to deliverpower to the load and the other regulates the current path from the load to theground [8]. This structure benefits from high power efficiency and smaller outputripple compared to half wave rectifier. However, threshold voltage drop of twodiodes are lost in each signal cycle.

The rectified output voltage is given by,

Vout = 2Vin − 2Vth (3.1)

As the MOS transistor is the main part of the rectifier structure, it is worthto analyze the equivalent circuit of the MOS transistor. The power consuming

19

20 RF CMOS Rectifier Architectures

Figure 3.1. Diode bridge rectifier. Figure 3.2. CMOS bridge rectifier.

Figure 3.3. MOS transistor transient equivalent circuits.

elements in the equivalent circuit are mainly substrate-drain diode, substrate-source diode and channel resistor. So most of the power is consumed by thechannel resistance which is the resistance between the source and the drain, MOSdiodes and the load resistance. To increase the power efficiency of the rectifier, theturn on voltage of the transistor should be small and the channel resistance alsoshould be decreased. To obtain small channel resistance, larger transistor size isrequired which contribute to large CMOS diodes and parasitic capacitances whichcan introduce greater leakage current and parasitic losses.

3.1.1 Conventional CMOS rectifier

A variety of conventional full wave rectifier have been addressed in [8][23] [7] [20][10] [21] [11]. A conventional CMOS rectifier circuit [11], which is composed ofseries connection of diode-connected NMOS and PMOS transistors is shown below.The RF input is applied through the coupling capacitor Cc. During the positive

3.1 Bridge Rectifier 21

Figure 3.4. Conventional CMOS rectifier circuit[21].

half cycle of the RF voltage signal, forward current flows to the output load. Whennegative half cycle of the RF voltage signal is applied, almost no current flows.The output voltage that is developed across the load is given as,

Vout = 2Vrf − Vdrop (3.2)

Most of the power losses of the integrated rectifier circuit originate from theon-resistance of the transistor. The PCE of the rectifier circuit is affected bycircuit topology, diode parameters, and input RF signal level [20][10]. Small ON-resistance and small reverse leakage current are the main parameters of the MOSdiode which can increase the PCE of the rectifier. Generally, small on-resistanceof the MOS-diode is achieved by small turn on voltage of the transistor that is thethreshold voltage of the transistor. It is thus desirable for the threshold voltageof the transistor to be as small as possible to decreases the losses in the rectifiercircuit. The voltage drop across a MOS diode is given as,

δV = Vth +

√2LI

CoxWµ(3.3)

where, W and L are the width and length of the transistor, I is the current flowingand Cox is process related product and Vth is the threshold voltage of the transis-tor. The voltage drop not only related to the threshold voltage, but also dependon the overload voltage, which linearly increases with square root of the current.As the threshold voltage is the main parameter which can degrade the perfor-mance of the rectifier, appropriate Vth-cancellation mechanism is applied, whichare External-Vth-cancellation (EVC) scheme [21], Self-Vth-cancellation (EVC)scheme [11] [20], and Internal-Vth-cancellation (IVC) scheme [17].

External-Vth-cancellation (EVC) scheme

The output voltage that can be obtained from conventional rectifier as discussedabove is given as:

Vout = 2 ∗ (Vrf − Vth) (3.4)

Maximum output voltage is obtained when threshold voltage is negligible. Inthis scheme a bias voltage is added between the gate and drain of the transistor.


Figure 3.5. External-Vth-cancellation CMOS rectifier circuit[17].

Thereby the threshold voltage changes to Vth − Vbias. The output voltage can berewritten as:

Vout = 2 ∗ (Vrf − Vth + Vbias) (3.5)

The threshold voltage is expected to reduce to zero when Vth is nearly equal toVbias, then the output voltage can be approximated as,

Vout = 2Vrf (3.6)

Therefore, it is possible to rectify small RF signals with this structure. However,it is not optimal due to the additional batteries used.

Self-Vth-cancellation (SVC) scheme

The developed self-Vth-cancellation (SVC) CMOS rectifier circuit [11] [20] is shownfigure 3.6. In self-Vth-cancellation rectifier, the gate of the NMOS and PMOStransistors are cross-connected such that the NMOS transistor and The transistors

Figure 3.6. Self-Vth-cancellation CMOS rectifier circuit[21].

are connected to the output terminal and ground terminal respectively as shownin the figure. This connection increases the gate-source voltage of the transistorwhich equivalently decreases the threshold voltage.


This scheme is simple and does not require any additional power circuitry.Gate-source voltages of the NMOS and PMOS transistors are statically biasedusing the output DC voltage, thus reducing the effective Vth of the MOS transis-tors [20], which result in large PCE. In this configuration, the energy loss mostlydepends on the on-resistance of the transistor. When the threshold voltage is toosmall, it may cause reverse leakage current which will reduce the PCE. Hence it isnot possible to achieve small on-resistance and small leakage current in self-Vth-cancellation rectifier. As a result, PCE of the SVC rectifier circuit will first increasewith the increase in input power, but then decrease with the further increase ininput power, exhibiting some peak value in between [10].

CMOS differential rectifier

According to SVC scheme rectifier it is not possible to achieve small on-resistanceand small leakage current simultaneously. In order to solve the problem differential-

Figure 3.7. Differential-drive CMOS rectifier[21].

drive CMOS rectifier circuit has been developed [20] [10]. It consist of a cross-coupled differential CMOS with a bridge structure. In this differential structure,the gate of the transistor is biased by a differential signal. From the figure, Vx andVy are the differential input RF signal. When Vx is negative then the transistorMN1 is forward biased and when Vy is positive which correspond to positive gatevoltage bias of MN1 transistor, which decreases the threshold voltage of the tran-sistor. This results in small on-resistance. Whereas, when Vx is positive and Vy

is negative, the transistor is reversed biased and the gate voltage decreases whichincrease the threshold voltage, resulting in reduction in reverse leakage current.

This kind of rectifier performs better than the MOS-diode based rectifier. Itis also called four-transistor cell according to [14] and called negative voltageconverter according to [19]. The structure consists of combination of two cross-connected gate structure which provide complimentary bridge rectifier. In thecircuit, the PMOS transistor delivers highest voltage to the load, whereas theNMOS-transistor provide the lowest voltage. The transistor operates in the triod


region which behaves as a switch, thereby having smaller voltage drop comparedto MOS-diode. The output voltage is given as,

VDC = 2VRF − Vdrop (3.7)

where, VRF is the amplitude of the differential signals and Vdrop is the lossesdue to swich resistance and reverse conduction. The maximum output voltage islimited to 2VRF . To increase the output voltage, N cells of the structure can becascaded. Differentials signal of the first stage is directly connected to to the RFsource whereas, the proceeding stages are capacitivly coupled to the RF source.This structure behaves as a charge pump voltage multiplier [14], as the expectedoutput voltage at the N’th stage is VDC = N(2VRF − Vdrop) but in practice theoutput voltage is lower because the Vdrop increases with the increase of the numberof cells due to increase of the body bias of the transistor.

Figure 3.8. Rectifier formed by cascading N rectifying cells in series[14].

3.2 Charge Pump 25

3.2 Charge Pump

3.2.1 Dickson charge pump

Charge pump circuit generates higher output voltage from lower input signal.It has been widely used in non-volatile memories such as EEPROM and flashmemories. The basic charge pump architecture is proposed by Dickson in 1976.

Figure 3.9. Dickson charge pump

This kind of charge pump consists of diodes and two non-overlapping pumpingclocks φ1φ2, whose amplitude is the supply voltage Vφ and is capacitively coupledto alternate nodes along the diode chain. It is operated by pumping chargesthrough the diodes and thereby charging the capacitors each clock cycle. At eachnode the voltage increases progressively from the input to the output of the diodechain by Vφ. However, the total output voltage is affected by a voltage drop VD

of the diode. The output voltage of a dickson charge pump is given as:

Vout = Vin + N(Vφ − VD)− VD (3.8)

where, N is the number of stages of the charge pump. The extra VD in theequation is because of the last diode available out of the chain. This kind ofcharge pump implementation is not optimal for passive wireless devices, as itrequire clock generation module which consume more power and area. To avoidthe clock generation module, the RF input signal is used to pump the chargesthrough the circuit where it rectifies the AC signal and increases the DC level.

3.2.2 Voltage multiplier

The N-stage voltage multiplier or cascade charge pump is based on the dicksoncharge pump except that, it does not require a clock signals. The N-stage voltagemultiplier consists of a cascade of peak-to-peak detectors as shown in the figurebelow. A peak detector is a series connection of a diode and a capacitor whichoutputs a DC voltage equal to the peak value of the applied AC signal.


Figure 3.10. cascade charge pump

To describe the operation of the charge pump, a single stage charge pump isanalyzed. During the negative half cycle of the RF signal, when Vn−1 > Vin +Vth,

Figure 3.11. Single stage charge pump.

the transistorMn−1 turns on while transistor Mn turns off as Vc < VN and thecharge transfers from capacitor CV (N−1) to capacitor Cc. At this cycle the nodevoltage at Vc is given as Vin +Vn−1−Vth. When the input changes to the positivehalf cycle the transistor Mn−1 turns off while transistor Mnturns on and the chargetransfer from Cc to capacitor Cn. The available voltage at Cn is given as

Vn = Vn−1 + 2Vin − 2Vth (3.9)

3.2 Charge Pump 27

The maximum voltage that can be achieved in a single stage charge pump is twicethe RF amplitude minus twice the threshold voltage of the MOS diode. The outputvoltage of N’th stage charge pump is given as:

Vn = 2N(Vin − Vth) (3.10)

From the above equation it is obvious that the threshold voltage has a drasticeffect on the the output voltage. To obtain a decent voltage from small input RFsignal, the threshold voltage must be minimized. Other way to increase the outputvoltage is by increasing the number of stages. However, increasing the number ofstages causes to degradation of power dissipation and power conversion efficiency.The threshold voltage also increases linearly with the increase of number of stagesdue to the body effect, thus limiting the number of stages that can be cascaded.

The MOS transistor in the charge pump operate in saturation region due tothe short connection between gate and darin, the drain current in this region isgiven as:

ID =β

2.(VGS − Vt)2 (3.11)

β = µn.Cox.W

L(3.12)

According to the equation to ensure pumping of low input voltage, low thresholdvoltage and small on-resistance of the transistor are required. To obtain smallresistance of the transistor, large transistors have to be used, leading to largerparasitic capacitance and thereby increasing the leakage current. In the otherhand, if the transistor size is too small, then the charge transfer is incompletewhich leads to small output voltage and hence low efficiency. Hence to obtainmaximum output voltage and high efficiency, low threshold voltage and optimaltransistor size should be selected.

Chapter 4

Simulation and EvaluationResults

In this section RF rectifiers are simulated in cadence environment using 0.35 µmand 65 nm technology. The results have been analyzed, and effect of variousparameters on the output voltage and power conversion efficiency.

4.1 Bridge RectifierAs discussed in section 3, the full wave bridge rectifier consists of four diode con-nected MOS-transistors connected in bridge form. The transistors can be NMOSor PMOS, however, PMOS transistor is preferred to reduce the variation of thresh-old voltage due to body effect. The bridge rectifier suffers from low voltage andefficiency not only because of the threshold voltage drop of two diode connectedtransistor, in addition to the leakage current of two MOS diodes at every halfcycle. The effect of different parameters on the output voltage and on the powerconversion efficiency is given below.

Figure 4.1. PMOS bridge rectifier.

29

30 Simulation and Evaluation Results

4.1.1 Effect of input amplitude on output voltage and PCEAccording to the simulation results, it is shown that increasing the input voltageincreases the output voltage linearly as shown in figure 4.2. Similarly, the PCEincreases for larger input voltage as shown in figure 4.3.

Figure 4.2. Output voltage dependence on input amplitude.


Figure 4.3. PCE dependence on input amplitude.

4.1.2 Effect of transistor size on output voltage and PCEIt is noticed from the graph 4.4 and 4.5 that the output voltage increases with thetransistor size since larger transistor size has small channel resistance. Similarly,the PCE increases with larger transistor size.


Figure 4.4. Output voltage dependence on transistor size.

Figure 4.5. PCE dependence on transistor size


4.1.3 Effect of frequency on PCEThe PCE decreases with higher frequency ranges. This rectifier structure is notsuitable for higher frequency as it suffer from lower PCE wit increasing the fre-quency.

Figure 4.6. PCE dependence on operating frequency.


4.1.4 Effect of load resistance on output voltage and PCE

Figure 4.7. Output voltage dependence on load resistance.

It is shown from the figure 4.7 and 4.8 that the PCE goes up with the loadresistance, but still the PCE cannot be very high for larger load resistance. Thisis because of the increased power consumption. However, larger load resistancegives higher output voltage.


Figure 4.8. PCE dependence on load resistance.

Summary of the achieved result of the output voltage and PCE for differentvalues of input amplitude for 0.35 µ m and 65 nm technology is given below:

Table 4.1. Summary of the achieved result of the output voltage and PCE for differentvalues in 65 nm technology.

Input amplitude (V) Output voltage (V) Power conversionefficiency(%)

0.4 0.152 15.630.35 0.104 12.170.3 0.064 8.30.25 0.034 4.6


Table 4.2. Summary of the achieved result of the output voltage and PCE for differentvalues in 0.35 µm technology.

Input amplitude (V) Output voltage (V) Power conversionefficiency(%)

1 0.387 0.60.8 0.218 0.3290.65 0.1 0.160.6 0.056 0.1

4.2 Differential CMOS Rectifier

The schematic of differential CMOS rectifier or four transistor cell rectifier is shownbelow and it has been simulated in 0.35 µm and 65 nm technology. Differentialinput signal with a 50 ohm resistance as of the antenna is used. The output voltageobtained when input signal amplitude of 0.25 V is applied at 900 MHz frequency.Capacitance of 10 pF and resistance of 8 k ohm are used as a filter which reducesthe ripple voltage to obtain a smoother output.

Figure 4.9. Schematic of differential CMOS rectifier.

Higher efficiency is obtained comparing to PMOS bridge rectifier. This isbecause when the diode connected transistor is reversed biased, the source appearconnected to the gate. A large leakage current is available at Vgs =0. Whereas,when a pair of cross connected transistor is reversed biased, the leakage currentproduced is very small.

4.2 Differential CMOS Rectifier 37

4.2.1 Effect of input amplitude on output voltage and PCEFrom figure 4.10, increasing the input voltage level increases the output voltage.However, figure 4.11 shows that the PCE increases first and decreases with furtherincrease of the input voltage. The reason behind the decrease in PCE for higherinput voltage level is that higher input voltage level increases the VGS which causesdecrease in threshold voltage. In this case, reverse leakage current of the rectifierincreases which causes extra energy dissipation.

Figure 4.10. Output voltage dependence on input amplitude.


Figure 4.11. PCE dependence on input amplitude.

4.2.2 Effect of transistor size on output voltage and PCEThe output voltage increases with the increase of the transistor size accordingto figure 4.12. This is due to increase of transistor size decreases the channelresistance of the transistor and hence increases the output voltage. However, largertransistor sizes lead to larger parasitic capacitance which will lead to parasiticlosses. Hence, the PCE decreases for larger transistor sizes as it has been shownin the figure 4.13.



Figure 4.13. PCE dependence on transistor size.


4.2.3 Effect of load resistance on output voltage and PCEFigure 4.14 shows the output voltage increases linearly with the load resistance.However, figure 4.15 shows that with larger load resistance, the Peak PCE canbe obtained at a smaller input power. The peak PCE increases slightly with theincrease of the load resistance.

Figure 4.14. Output voltage dependence on load resistance.


Figure 4.15. PCE dependence on load resistance.

4.2.4 Effect of frequency on PCEThe dependence of the PCE on the operating frequency is illustrated in figure4.16. As the operating frequency increases, the PCE decreases. This is becausewith the increase of the frequency, the energy loss increases due to increase of thereactance component.


Figure 4.16. PCE dependence on input amplitude at various frequencies.


Summary of the achieved result of the output voltage and PCE for differentvalues of input amplitude for 0.35 µ m and 65 nm technology is given below

Table 4.3. Summary of the achieved result of the output voltage and PCE for differentvalues in 65 nm technologyInput amplitude (V) Output voltage (V) Power conversion efficiency(%)

0.4 0.297 11.560.35 0.262 14.140.3 0.224 17.90.25 0.18 230.2 0.124 26.78

Table 4.4. Summary of the achieved result of the output voltage and PCE for differentvalues in 0.35 µ m technology.

Input amplitude (V) Output voltage (V) Power conversion efficiency(%)0.55 0.309 9.90.5 0.222 6.30.45 0.122 2.40.4 0.047 0.5


4.3 Charge PumpFrom the previous section, it was shown that as the number of stages in the chargepump is increased, the output voltage is also increased, but this will also resultsincrease in internal impedance thereby decreasing the output drive current. Toincrease the output current, the capacitance and the size of the transistor can beincreased, but these contribute to parasitic capacitance. Hence optimal numberof stages of the charge pump should be chosen. In the simulation, 7-stage chargepump is used. The simulation setup has been shown in the figure below:

Figure 4.17. 7-stage charge pump test bench.

A sinusoidal signal is applied to the charge pump with a 50 ohm resistance as ofthe antenna. A load resistance of 1 M ohm is used to represent a transmitter withhigh impedance connected to the charge pump. The output voltage obtained from7-stage charge pump using 0.15 V input amplitude of the signal is given below:

Figure 4.18. Output voltage generated with and without load resistance.

4.3 Charge Pump 45

The generated output voltage is nearly 1 V but when output load of 1 M ohmis connected 0.25 V output voltage is obtained, however, this voltage can varywith various parameter like transistor size, number of stages of the charge pump,capacitance value, load resistance.

4.3.1 Effect of transistor size on output voltage and PCEHow the transistor size can affect the output voltage and PCE can be noticedfrom figure 4.18. It is seen that as the transistor size increases the output voltage


increases. This is due to the fact that large transistor sizes cause small resistanceof the transistor and thereby increasing the output current. Similarly, the powerconversion efficiency can be improved with large transistor size but not signifi-cantly.


4.3.2 Effect of number of stages on output voltage and PCE

Figure 4.20. Output voltage for different number of stages.

As the number of stages of the charge pump increases the output voltage alsoincreases as shown in equation 3.10 and figure 4.20. However, as the numbers ofstages increases, the source voltage of the transistor increases, thereby increasingthe VSB voltage. Thereby increasing the threshold voltage, which can lead todegradation of the power conversion efficiency.

Vth = Vtho + (√|2ΦF + VSB | −

√|2ΦF |) (4.1)

where, VSB is the source-bulk potential difference, φ is the body effect coefficient.

4.3 Charge Pump 47

4.3.3 Effect of frequency on output voltage and PCETo increase the output voltage, the number of stages need to be increased asdiscussed earlier but this increases the internal impedance as represented in theequation below.

Rs =N

C ∗ f(4.2)

where, Rs is the internal impedance, N is the number of stages, C is the capacitanceand f is the operating frequency of the charge pump. The optional way to achievehigher output voltage is to increase the frequency or the capacitance as increas-ing them reduces the internal impedance. A larger capacitor allow more chargeto be transferred and thus increases the output voltage, but larger capacitanceintroduces parasitic capacitance, this can lead to a higher power consumption,P = CfV 2. Hence, the power efficiency of the charge pump decreases with theincreased output voltage.

Summary of the achieved result of the output voltage and PCE for differentvalues of input amplitude for 0.35 µm and 65 nm technology is given below:

Table 4.5. Summary of the achieved result of the output voltage and PCE for differentvalues in 65 nm technology.Input amplitude (V) Output voltage without load (V) PCE with 1 M ohm RL(%)

0.37 2.7 13.30.16 1 2.80.1 0.5 0.780.06 0.22 -

Table 4.6. Summary of the achieved result of the output voltage and PCE for differentvalues in 0.35 µm technology.Input amplitude (V) Output voltage without load (V) PCE with 1 M ohm RL(%)

1 1.375 0.30.8 0.743 0.10.7 0.446 0.080.6 0.226 -

Chapter 5

Comparison of Results andConclusion

The choice of rectifier structure depends on the application in use. Charge pumpand the differential CMOS rectifier are the most promising. Charge pump issuitable to generate the preferred output voltage level from too low input voltage,but it suffers from low power efficiency due to the more stages incorporated whichincreases the power consumption.

Figure 5.1. Input amplitude vs output voltage for different rectifier architectures.

49

50 Comparison of Results and Conclusion

Figure 5.2. Input amplitude vs PCE for different rectifier architectures.

On the other hand, to achieve better PCE the differential CMOS rectifier orNMOS-PMOS cross-coupled structure is suitable but requires larger input voltagecompared to charge pump. It is also noticed that the differential CMOS rectifierhas higher efficiency for lower input voltage, but the PCE decreases for largerinput voltage.

The comparison between PMOS-bridge rectifier, differential CMOS rectifier,and the charge pump are shown in Figure 5.1 and 5.2. It is noticed from the figurethat the charge pump can achieve the highest output voltage of 2.7 V using inputamplitude of 0.35 V. However, the maximum PCE is achieved using differentialCMOS rectifier of 23% at 0.25 V input amplitude. On the other hand, the PMOS-bridge rectifier has the lowest output voltage and PCE.

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