study of multistage oscilloscope trigger circuit

Study of Multistage Oscilloscope Trigger Circuit

S. Sakurai, S. Takigami, T. Ida, Y. Ozawa,

N. Tsukiji, Y. Kobori, H. Kobayashi, R. Shiota

Gunma University, Socionext Inc.

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ISPACS 2017

Nov. 9 NP-L2 Paper ID 11,

http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700

http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700

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Outline

1. Research Objective

2. Analysis of Trigger Circuit

3. Multistage Trigger Circuit

4. Application to SAR-TDC

5. Summary

3/40

Outline





5. Summary

4/40

Oscilloscope Trigger Circuit

c

Track&Hold

Track&Hold

Σ

Input

to

Output

to

sinωt

Track&Hold

sin(ωt+2π/3)

+

+

+

－

－

－

sin(ωt+4π/3)

F1

F2

F3

S1

S2

S3

Track&Hold

Track&Hold

Σ

Trigger

Input

to

Output

sinωt

cosωt

𝑉𝑜_3

𝑉𝑜_2

Two stage

Three stage

Application Trigger Circuit

Sequential Sampling

Oscilloscope

Δt 2Δt 4Δt3Δt

Time

Δt=T_delay

Trigger

5/40

Research Motivation

Brain A lot of neurons

Large number Good performance

Each transistor has only simple capability

Smart Each neuron has low capability

6/40

Research Objective

1. Analysis of basic trigger circuits

(two-stage and three-stage)

2. Extension to an N-stage trigger circuit, and

its output formula.


for one-shot timing measurement

7/40

Outline



T/H Circuit, Gilbert Analog Multiplier

Basic Trigger Circuit



5. Summary

8/40

Trigger Circuit Configuration

Sinusoidal wave based on time 𝑡0Output signal with zero phase

Signal sourceT/H circuitMultiplier

Construction with

Track&Hold

Track&Hold

Σ

Trigger

Input

to

Output

sinωt

cosωt

to

Trigger Time

ON

OFF

Output

Trigger

9/40

Track / Hold Circuit

SW

ON

SW

OFF

Vin

Vout=VcVout=Vin

VcVin

10/40

Gilbert Analog Multiplier

𝑉𝑖𝑛

𝑉𝑂𝑢𝑡1𝐼𝑜 ഥ𝐼𝑜𝑉1

ഥ𝑉1

𝑉2𝑉2

𝑉𝑂𝑢𝑡1 = 𝑉𝑐𝑐 − 𝑅ഥ𝐼𝑜𝑉𝑂𝑢𝑡2 = 𝑉𝑐𝑐 − 𝑅𝐼𝑜

𝑉𝑂𝑢𝑡1 − 𝑉𝑂𝑢𝑡2 = 𝑅 𝐼𝑜 − ഥ𝐼𝑜 = 𝑅𝐼𝑇 ∗ tanh𝑉1 − ഥ𝑉12𝑉𝑇

∗ tanh𝑉2 − 𝑉22𝑉𝑇

≅ 𝑉1 ∗ 𝑉2

11/40

Analysis of Two-stage Trigger Circuit.

・Track mode

𝑉𝑜 𝑇𝑟𝑎𝑐𝑘 = cos 𝜔𝑡 cos 𝜔𝑡 + cos 𝜔𝑡 +𝜋

2cos 𝜔𝑡 +

𝜋

2= cos2 𝜔𝑡 + sin2 𝜔𝑡= 1

・Hold mode𝑉𝑜 𝐻𝑜𝑙𝑑 = cos 𝜔𝑡 cos 𝜔𝑡0 + sin 𝜔𝑡 sin 𝜔𝑡0

= cos 𝜔 𝑡－𝑡0

※ Trigger time:t0

𝑉𝑜_2Track&Hold

Track&Hold

Σ

Trigger

Input

to

Output

sinωt

cosωt

12/40

Two-stage CMOS Trigger Circuit

T/H Circuit

13/40

Two-stage CMOS Trigger Circuit

T/H Circuit Gilbert Multiplier

14/40

Simulation of Two-stage Trigger Circuit

Input signal(sin,cos)

Input trigger signal

Output signal

Voltag

e [V

]

15mV

-15mV

4.0

0.0

2.7mV

0mV

0.0 1.0us 2.0us 3.0us 4.0us

Time [sec]

15/40

c

Track&Hold

Track&Hold

Σ

Input

to

Output

to

sinωt

Track&Hold

sin(ωt+2π/3)

+

+

+

－

－

－

sin(ωt+4π/3)

F1

F2

F3

S1

S2

S3

Three-stage Trigger Circuit

𝑉𝑜_3

𝑆1 = sin𝜔𝑡，𝑆2 = sin 𝜔𝑡 +2𝜋

3，𝑆3 = sin 𝜔𝑡 +

4𝜋

3

𝐹1 = sin𝜔𝑡0 ，𝐹2 = sin 𝜔𝑡0 +2𝜋

3，𝐹3 = sin 𝜔𝑡0 +

4𝜋

3

Signal source

Triggered signal

16/40

Analysis of Three-stage Trigger Circuit

𝑉𝑜ℎ𝑜𝑙𝑑 = 𝑆1 𝐹2 − 𝐹3 + 𝑆2 𝐹3 − 𝐹1 + 𝑆3 𝐹1 − 𝐹2

=3 3

2sin 𝜔(𝑡 − 𝑡0 )

𝑉𝑜𝑡𝑟𝑎𝑐𝑘 = 𝑆1 𝑆2 − 𝑆3 + 𝑆2 𝑆3 − 𝑆1 + 𝑆3 𝑆1 − 𝑆2

= 0 (Constant)



4𝜋

3

𝐹1 = sin𝜔𝑡0 ，𝐹2 = sin 𝜔𝑡0 +2𝜋

3，𝐹3 = sin 𝜔𝑡0 +

4𝜋

3

Signal source

Triggered T/H circuit output

・Track mode

・Hold mode

17/40

Three-stage CMOS Trigger Circuit

Trigger

input

Vout

sin(ωt) sin(ωt+2π/3) sin(ωt+4π/3)+ － + － + －

Vdd

18/40

Simulation of Three-stage Trigger Circuit

Input signal

Input trigger signal

Output signal

Voltag

e [V

]

15mV

-15mV

4.0

0.0

1.75mV

0mV

0.0 1.0us 2.0us 3.0us 4.0us

19/40

Spectrum Comparison of Two-stage, Three-stage

Cancellation of the third harmonicsdue to three-stage structure.

Red ：3 stageBlack ：2 stage

-200

-160

-120

-80

-40

100K 1M 10M 100M

Gai

n[d

B]

Frequency[Hz]

-50dB

20/40

Outline





5. Summary

21/40

Configuration of N-stage Trigger Circuit

Track&Hold

Track&Hold

Σ

Input

Output

sinωt

Track&Hold

sin(ωt+θ)

+

+

+sin(ωt+2θ)

F1

F2

F3

S1

S2

S3

Track&Hold

Sn

sin(ωt+nθ)

Σ

Σ

Σ

･･･

･･･

･･･

Fn ･･･

Σ+

Vo_N

･･･

to

22/40

Consideration of N-stage Trigger Circuit

𝑆1 𝐹2 − 𝐹3 + 𝑆2 𝐹3 − 𝐹1 + 𝑆3 𝐹1 − 𝐹2

𝑆1 𝐹2 − 𝐹3 − 𝐹4 −⋯− 𝐹𝑁−1 − 𝐹𝑁+𝑆2 𝐹3 − 𝐹4 − 𝐹5 −⋯− 𝐹𝑁 − 𝐹1+⋯+𝑆𝑁 𝐹1 − 𝐹2 −⋯−𝐹𝑁−2 − 𝐹𝑁−1

Extension to N-stage

Output of three-stage

Same calculation

c

Track&Hold

Track&Hold

Σ

sinωt

Track&Hold

sin(ωt+2π/3)

+

+

+

－

－

－

sin(ωt+4π/3)

F1

F2

F3

S1

S2

S3

Track&Hold

Track&Hold

Σ

Input

Output

sinωt

Track&Hold

sin(ωt+θ)

+

+

+sin(ωt+2θ)

F1

F2

F3

S1

S2

S3

Track&Hold

Sn

sin(ωt+nθ)

Σ

Σ

Σ

･･･

･･･

･･･

Fn ･･･

Σ+

Vo_N

･･･

to

23/40

Consideration of N-stage Trigger Circuit

c

Track&Hold

Track&Hold

Σ

sinωt

Track&Hold

sin(ωt+2π/3)

+

+

+

－

－

－

sin(ωt+4π/3)

F1

F2

F3

S1

S2

S3

𝑆𝑛 = sin 𝜔𝑡 + 𝑛 − 1 𝜃 ， 𝜃 =2𝜋

𝑁



4𝜋

3

𝜃1 = 0 𝜃2 =2𝜋

3𝜃3 =

4𝜋

3

Signal source of three-stage

Signal source of N-stage

Track&Hold

Track&Hold

Σ

Input

Output

sinωt

Track&Hold

sin(ωt+θ)

+

+

+sin(ωt+2θ)

F1

F2

F3

S1

S2

S3

Track&Hold

Sn

sin(ωt+nθ)

Σ

Σ

Σ

･･･

･･･

･･･

Fn ･･･

Σ+

Vo_N

･･･

to

25/40

Derivation of N-stage Output

𝑥𝑘 = 𝑉𝑘+1 − 𝑉𝑘

= 𝐹𝑘+1 𝑆𝑘 −

𝑙=1

𝑘−1

𝑆𝑙 − 2𝑆𝑘𝐹1 + 𝑆𝑘+1 𝐹1 −

𝑚=2

𝑘−1

𝐹𝑚

Using difference sequence

𝑉𝑁 = 𝑆1𝐹2 + 𝑆2𝐹1 +

𝑘=2

𝑁−1

𝐹𝑘+1 𝑆𝑘 −

𝑙=1

𝑘−1

𝑆𝑙 − 2𝑆𝑘𝐹1 + 𝑆𝑘+1 𝐹1 −

𝑚=2

𝑘−1

𝐹𝑚

N-stage Output

3stage → 4stage → 5stage → … → N-1stage → Nstage

Increment when increasing the stage number

𝑥3 𝑥4 𝑥𝑁−1・・・𝑥5 𝑥𝑁−2

26/40

Confirmation of N-stage Output

Matching with Three-stage

𝑉𝑜_𝑁 = 𝑎2 +

𝑘=2

𝑁−1


𝑙=1

𝑘−1

𝑆𝑙 − 2𝑆𝑘𝐹1 + 𝑆𝑘+1 𝐹1 −

𝑚=2

𝑘−1

𝐹𝑚

𝑉𝑜_3 = 𝑆1𝐹2 + 𝑆2𝐹1 +

𝑘=2

2


𝑙=1

1

𝑆𝑙 − 2𝑆𝑘𝐹1 + 𝑆𝑘+1 𝐹1 −

𝑚=2

1

𝐹𝑚

= 𝑆1𝐹2 + 𝑆2𝐹1 + 𝐹3 𝑆2 − 𝑆1 − 2𝑆2𝐹1 + 𝑆3 𝐹1 − 𝐹2

= 𝑆1 𝐹2 − 𝐹3 + 𝑆2 𝐹3 − 𝐹1 + 𝑆3 𝐹1 − 𝐹2

𝑉𝑜_3 = 𝑆1 𝐹2 − 𝐹3 + 𝑆2 𝐹3 − 𝐹1 + 𝑆3 𝐹1 − 𝐹2 Match

27/40

Output of Five-stage Trigger Circuit

28/40

-200

-160

-120

-80

-40

100K 1M 10M 100M

Gai

n[d

B]

Frequency[Hz]

Output Spectrum Comparison

Third harmonic cancellation

Second harmonic reduction by 30%

Third harmonic

Red ：Five-stageBlue ：Three-stage

29/40

-160

-120

-80

-40

100K 1M 10M 100M

Gai

n[d

B]

Frequency[Hz]

Multistage Configuration Merit

-18dB

Red ：Five-stageBlue ：Three-stage

Third harmonic cancellation

Second harmonic reduction by 30%

30/40

Outline





5. Summary

31/40

Time Digitizer Circuit

Time-to-Digital Converter (TDC）Measure time difference between Start and Stop signals.

Measure Digital outputTime

difference

32/40

ΔT ΔT ΔT

CLK1

CLK2

ΔT

SAR-TDC Configuration

Need cycle clock for measurement

Reference[5]

Y. Ozawa, T. Ida, S. Sakurai, R. Jiang, H. Kobayashi, R.

Shiota, “SAR ADC Architecture for One-Shot Timing

Measurement with Full Digital Implementation,”

33/40

Problem of SAR-TDC and Remedy

Voltage signal can be held.

Timing signal cannot be held.

Timing signal can be held !

Our argument

Myth

34/40

One-shot Timing Measurement Using Trigger Circuit

2017/11/17

Oscillate with initial phase

at input timing

Input START,STOP signal

It can hold the time difference using two trigger circuits.

1step 2step 3step 4step 5step 6step 7step

Suggestion

Δ𝑇 Δ𝑇

35/40

One-shot Timing Measurement Configuration

START

STOP

w1

w2

ck1

ck2

ΔT ΔT ΔT ΔT

36/40

One-Shot Timing Measurement Simulation

37/40

Outline





5. Summary

38/40

Summary

• Investigation of CMOS trigger circuit

• Extension to N-stage trigger circuit, and

its confirmation with SPICE simulated

sinusoidal output power spectrum.

Harmonics reduction

• Proposal of one-shot timing measurement

with trigger circuits and SAR-TDC.

39/40

Future works

• Harmonics suppression analysis

based on derived formula.

• Circuit configuration

that reduces Gilbert cell nonlinearity

• Implementation consideration

including SAR-TDC.

40/40

Outline

1. Research objective

2. Analysis of Trigger circuit


4. Applying to SAR-TDC

5. Summary

41/40

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study of multistage oscilloscope trigger circuit

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