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INF4420 RepetitionTuesday 26th of May, 2009, 9:15

Snorre Aunet, sa@ifi.uio.noNanoelectronics Group, Dept. of Informatics

Office 3432

Subjects from the book by Johns & Martin

• Chapter 2 Processing and Layout • Chapter 8 Sample and Holds, Voltage References,

and Translinear Circuitsand Translinear Circuits• Chapter 9 Discrete-Time Signals• Chapter 10 Switched-Capacitor Circuits• Chapter 11 Data Converter Fundamentals• Chapter 12 Nyquist-Rate D/A Converters• Chapter 13 Nyquist-Rate A/D ConvertersChapter 13 Nyquist Rate A/D Converters• Chapter 14 Oversampling Converters• Chapter 16 Phase-Locked Loops

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Subjects from the book by Johns & Martin that have been treated in the lectures, or are relevant even though they were

not treated in detail• Chapter 2 Processing and Layout • Chapter 8 Sample and Holds, Voltage References, and Translinear Circuits; 8.1 performance, 8.2 MOS S/H

basics, 8.5 Bandgap voltage reference basics, 8.6 Circuits for bandgap references • Chapter 9 Discrete-Time Signals; 9.1 Overview of some signal spectra, 9.2 Laplace transforms of discrete-time

signals, 9.3 Z-transform, 9.4 Downsampling and upsampling, 9.5 Discrete-time filters, 9.6 Sample-and-Hold response

• Chapter 10 Switched-Capacitor Circuits; 10.1 Basic Building Blocks, 10.2 Basic operation and analysis, 10.3 First-order filters, 10.4 Biquad filters, 10.5 charge injection, 10.7 correlated double-sampling techniques

• Chapter 11 Data Converter Fundamentals; 11.1 Ideal D/A converter, 11.2 Ideal A/D converter, 11.3 Quantization noise, 11.4 Signed codes, 11.5 Performance limitations

• Chapter 12 Nyquist-Rate D/A Converters; 12.1 Decoder-based converters, 12.2 Binary-scaled converters, 12.3 Thermometer-code converters, 12.4 Hybrid converters,

• Chapter 13 Nyquist-Rate A/D Converters; 13.1 Integrating converters, 13.2 Successive-approximation converters, 13.3 Algorithmic (or cyclic) A/D converter, 13.4 Flash (or paralell) converters, 13.5 Two-step converters, 13.6 Interpolating A/D converters, 13.7 Folding A/D converters, 13.8 Pipelined converters, 13.9 Time-Interleaved A/D converters

• Chapter 14 Oversampling Converters; 14.1 Oversampling without noise shaping, 14.2 Oversampling with noise shaping14.3 System architectures, 14.4 Digital decimation filters, 14.5 Higher-order modulators, 14.7 Practical considerations, 14.8 Multi-bit Oversampling Converters (example, IEEE paper)

• Chapter 16 Phase-Locked Loops; 16.1 Basic Loop Architecture, 16.2 PLLs with charge-pump phase comparators, 16.3 Voltage-controlled oscillators, (16.4 Computer Simulations of PLLs)

Chapter 8 Sample-and-Holds, Voltage References, Translinear Circuits

• Samples an analog signal andstores it for some time

• Often limiting the performancefor Analog-to-Digital Converters

Vin Vout1

φclk

C

Q1 V′

g g• Performance limitations: hold step,

feedthrough, bandwidth (sample mode) and slew rate, droop rate, aperture jitter

• Charge injection• We have seen different topologies, having different input

impedance operational speed susceptibility to clock

Chld

impedance, operational speed, susceptibility to clock feedthrough, slewing properties, signal dependent charge injection etc.

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Bandgap reference - Basic principleIB

VBE

• The voltage VBE is CTAT• The voltage is PTAT• is scaled by K to get the same slope as VBE

VBEΔ

VBEΔ

PTAT Generator K

VBEΔ

V ref VBE K VBEΔ+=

is scaled by K to get the same slope as VBE• By adding VBE and K , the output Vref

becomes independent of temperatureVBEΔ

VBEΔ

Theory• Collector current

• Solved with respect to VBE:

IC IseV

BEkT( ) q⁄( )⁄=

p BE

- The collector current density is related to the current:- The difference between two junctions biased at different

densities:IC AEJC=

VBE VG0 1 TT0------–

⎝ ⎠⎛ ⎞ VBE0

TT0------ mkT

q------------ ln

T0T------⎝ ⎠⎛ ⎞ kT

q------- ln

JC

JC0--------⎝ ⎠⎜ ⎟⎛ ⎞

+ + +=

VBEΔ V2 V1– kTq

------- lnJ2J1----⎝ ⎠⎜ ⎟⎛ ⎞= =

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Theory• Assuming that:

• Vref can then be written as:

JiJi0------ T

T0------=

Vref can then be written as:

• For a given temperature this equation may be independent of changes in the temperature if a proper

Vref VBE2 K VBEΔ+=

VG0TT0------ VBE0-2 VG0–( ) m 1–( )

kTq

------- lnT0T------⎝ ⎠⎛ ⎞ KkT

q------- ln

J2J1----⎝ ⎠⎜ ⎟⎛ ⎞

+ + +=

vaule of K is assigned

Theory• The change in Vref with respect to the temperature is:

• For zero temperature dependence at the

Vref∂T∂

------------ 1T0------ VBE0-2 VG0–( ) Kk

q--- ln

J2J1----⎝ ⎠⎛ ⎞ m 1–( )

kq--- ln

T0T------ 1–⎝ ⎠⎜ ⎟⎛ ⎞+ +=

T T0=p pfollowing applies:

• Solving with respect to K gives:

0

VBE0-2 KkT0

q--------- ln

J2J1----⎝ ⎠⎜ ⎟⎛ ⎞+ VG0 m 1–( )

kT0q

---------+=

KVG 0 m 1–( )

kT0q

--------- VB E0-2–+ 1,24 VB E0-2–K q

kT 0q

--------- lnJ2J1----⎝ ⎠⎜ ⎟⎛ ⎞

--------------------------------------------------------------------

0,0258 lnJ2J1----⎝ ⎠⎜ ⎟⎛ ⎞

---------------------------------= =

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Chapter 9 Discrete-Time Signals

• Understanding theory and methods concerning Discrete-Time Signals are important in IC design:important in IC-design:

• The design of Switch-Capacitor filters and their analysis are based on discrete-time signal processing

• Discrete-time signal processing are necessary during analysis and design of oversampled data converters (Delta Sigma) used in for exampleconverters (Delta-Sigma) used in for example audio and instrumentation

• Digital filter design is also related to concepts from this chapter

Overview of signal spectra – conceptual and physical realizations

convert todiscrete-time

sequenceDSP

convert toimpulse

trainhold

analoglow-pass

filter

xc t( )

s t( )

xs t( )

x n( ) xc nT( )= y n( ) ys t( ) ysh t( )

yc t( )

• An anti-aliasing filter (not shown) is assumed to band limit the continous time signal, xc(t).

DSPA/D

converter

sample analoglow-pass

filterandhold

D/Aconverterwith hold

xc t( )

xsh t( ) x n( ) xc nT( )= y n( )ysh t( )

yc t( )

band limit the continous time signal, xc(t).• DSP (”discrete-time signal processing”) may be

accomplished using fully digital processing or discrete-time analog circuits (ex.: SC-circ.)

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Signals in time, and frequency spectra• S(t): periodic impulse

train with period T (T=1/fs)

• xs(t) has the same frequency spectrum as xc(t), but the baseband spectrum repeats every fs (assuming no aliasing)

• x(n) has the same frequency spectrum as xc(t), but the sampling frequency is normalized to 1Th f t• The frequency spectrum of xsh(t) is equal to that of xs(t) multiplied by the sin(x)/x response of the S/H.

Aliasing and potential degrading of signal / noise

• Figure from W. Kester et. Al.: ”Mixed-Signal Seminar”, Analog Devices, 1991., in S. Aunet: ”BiCMOS sample-and-hold for satellitt-kommunikasjon”, Cand. Scient. Thesis, University of Oslo, 1993.

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Chapter 10 Switched-Capacitor Circuits

10.1 Basic building blocks10.2 Basic operation and analysisp y10.3 First-order filters10.4 Biquad filters10.5 Charge injection10.6 SC gain circuits10.7 Correlated double sampling techniques10.8 Other SC circ.

SC Resistor Equivalentφ2φ1

C1

V1 V2V1 V2

Req

Req

TC

1------=

ΔQ C1

V1

V2–( ) every clock period=

IeqV1 V2–

Req-------------------=

The current through an equivalent resistor is given by:

Combining the previous equation with Iavg:

ReqTC1------ 1

C1fs----------= =

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Transfer function for simple discrete time integrator in chapter 10.2

•

Chapter 11 Data Converter Fundamentals

•

A/D D/A

B V1Vin

VQ– +

Quantizationnoise

VinVQ

1in

V1

(Time)

12---VLSB

12---VLSB–

Tt

(Time)t

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Main data converter types:

• Nyquist rate converters:• Nyquist-rate converters:• Each value has a one-to-one correspondencewith a single

input• The sample-rate must be at least equal to twice the signal

frequency (Typically somewhat higher)• Oversampled converters:

• The sample-rate is much higher than the signal frequency, typically 20 512 timestypically 20 – 512 times.

• The extra samples are used to increase the SNR

11.5 performance limitations• Resolution• Offset and gain error• Accuracy• Integral nonlinearity (INL) error• Differential nonlinearity (DNL) error• Monotonicity• Missing codes• A/D conversion time and sampling rate• D/A settling time and sampling rate• Sampling time uncertainty• Dynamic range• Dynamic range• NB!! Different meanings and definitions of performance parameters

sometimes exist. Be sure what’s meant in a particular specification or scientific paper.. There are also more than those mentioned here.

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Chapter 12 Nyquist Rate D/A Converters

1

VoutVref-------------

2 bit DAC

0100 10 110

1

1/2

1/4

3/4

(100)

VLSBVref

---------------- 14--- 1 LSB= =

B

2-bit DAC

0100 10 11 (100) Bin

VLSBVref

2N----------≡ 1 LSB 12N------=

Nyquist Rate D/A Converters• 12.1 Decoder-based converters

resistor string conv.folded resistor string conv.multiple R-string converters

• 12.2 Binary-Scaled convertersbinary-weighted resistor convertersreduced resistance-ratio laddersR-2R-based converterscharge-redistribution switched-capacitor conv.current-mode conv.

• 12.3 Thermometer-code convertersthermometer-code current-mode D/A converterssingle-supply positive-output converterssingle supply positive output convertersdynamically matched current sources

• 12.4 Hybrid convertersresistor-capacitor hybrid converterssegmented converters

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Chapter 13 Nyquist A/D converters

Energy, conversion and ENOB (Carsten Wulff, NTNU, 2008)

• By Carsten Wulff, NTNU, 2008

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Integrating Converters (13.1)

ControlCounter

b1b2b3

S2

S1Vin–

Vref

S1S2⎝ ⎠⎛ ⎞

R1

C1

Vx

Comparator

• Vx(t) = Vin t / RC (Vx ramp derivative depending on Vin )• High linearity and low offset/gain error

(Vin is held constant during conversion.)

logic 3

bN

Clock

fclk1

Tclk-----------=

Bout

• High linearity and low offset/gain error• Small amount of circuitry• Low conversion speed

• 2N+1 * 1/Tclk (Worst case)

Resistor-Capacitor Hybrid• First all capacitors are charged to

Vin before the comparator is being reset.

• Next a succ. approx. Conversion is performed to find the two adjacentperformed to find the two adjacent resistor nodes having voltages larger and smaller than Vin

• One bus will be connected to one node while the other is connected to the other node

• Then a successive approximation• Then a successive approximationusing the capacitor-array network is done, starting with the largest capacitor…

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Speed estimate for charge-redistribution converters• Often major limitation• Individual time constant due to

the 2C cap.: (Rs1+R+Rs2)2C • (R ; bit line)(R ; bit line)• Taueq=(Rs1+R+Rs2)2NC, for the

circuit in fig. 13.12• For better tha 0.5 LSB accuracy:

e-T/Taueq < 1/2N+1, T = charging time

• T > Tau (N+1) ln2 =T > Taueq (N+1) ln2 0.69(N+1)Taueq

• 30 % higher than from Spice simulations (”J & M”)

Time-Interleaved – best compromise between complexity and sampling rate – may be used for different architectures [Elbjornsson ’05]

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Chapter 14 Oversampling converters

14.2 Oversampling with noise shaping

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Second-order noise shaping

OSR, modulator order and Dynamic Range• 2 X increase

in M (6L+3)dB or (L+0.5) bit increase in DR.

• L: sigma-delta order

• Oversampling and noiseand noise shaping

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Phase-locked loops (chapter 16)

Phasedetector

Outputvoltage

Average voltage proportional to phase difference

VinVpd

Klp

GainLow-pass

filter

Hlp s( )Vlp

• Clock multiplication:• The input signal is reference oscillator with fixed frequency• The PLL output is a signal with frequency N times the input frequency where N is an integer

• Data recovery and clock resynchronization:• The input signal is a digital signal containing data• The output is digital data at a certain clock rate• The system clock is recovered from the digital input signal

VCOVcntl

Vosc(voltage controlled oscillator)

• The system clock is recovered from the digital input signal• Frequency synthesis (ex: to select channels in television or wireless communication systems):

• The input signal is reference oscillator with fixed frequency• The PLL output is a signal with frequency N times the input frequency where N may be a fractional

number• FM demodulation:

• The input is a FM signal (IF)• The output is the demodulated baseband signal

Subjects from the book by Johns & Martin that have been treated in the lectures, or are relevant even though they were not treated in detail

• Chapter 2 Processing and Layout • Chapter 8 Sample and Holds, Voltage References, and Translinear Circuits; 8.1 performance, 8.2 MOS

S/H basics, 8.5 Bandgap voltage reference basics, 8.6 Circuits for bandgap references • Chapter 9 Discrete-Time Signals; 9.1 Overview of some signal spectra, 9.2 Laplace transforms of

discrete-time signals, 9.3 Z-transform, 9.4 Downsampling and upsampling, 9.5 Discrete-time filters, 9.6 Sample-and-Hold responseSample-and-Hold response

• Chapter 10 Switched-Capacitor Circuits; 10.1 Basic Building Blocks, 10.2 Basic operation and analysis, 10.3 First-order filters, 10.4 Biquad filters, 10.5 charge injection, 10.7 correlated double-sampling techniques

• Chapter 11 Data Converter Fundamentals; 11.1 Ideal D/A converter, 11.2 Ideal A/D converter, 11.3 Quantization noise, 11.4 Signed codes, 11.5 Performance limitations

• Chapter 12 Nyquist-Rate D/A Converters; 12.1 Decoder-based converters, 12.2 Binary-scaled converters, 12.3 Thermometer-code converters, 12.4 Hybrid converters,

• Chapter 13 Nyquist-Rate A/D Converters; 13.1 Integrating converters, 13.2 Successive-approximation converters, 13.3 Algorithmic (or cyclic) A/D converter, 13.4 Flash (or paralell) converters, 13.5 Two-step converters 13 6 Interpolating A/D converters 13 7 Folding A/D converters 13 8 Pipelined convertersconverters, 13.6 Interpolating A/D converters, 13.7 Folding A/D converters, 13.8 Pipelined converters, 13.9 Time-Interleaved A/D converters

• Chapter 14 Oversampling Converters; 14.1 Oversampling without noise shaping, 14.2 Oversampling with noise shaping14.3 System architectures, 14.4 Digital decimation filters, 14.5 Higher-order modulators, 14.7 Practical considerations, 14.8 Multi-bit Oversampling Converters (example, IEEE paper)

• Chapter 16 Phase-Locked Loops; 16.1 Basic Loop Architecture, 16.2 PLLs with charge-pump phase comparators, 16.3 Voltage-controlled oscillators, (16.4 Computer Simulations of PLLs)

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Exam 2008, page 1-2

26. mai 2009 33

Exam 2008, page 3-4

26. mai 2009 34

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Exam 2008, page 5

26. mai 2009 35

Exam, Thursday 4th of June• Individual written exam, counts 60 % (proj.:40 %)• 3 hours. 14:30 at “Store fysiske lesesal”, Physics Building• Questions based on material from the book, and from lectures, including

written material.• You may bring any written material like for example books, papers and

lecture notes.• Consider writing at least something reasonable even if you feel that you

don’t know much about a given problem, as no answer means 0 points. A blank answer may have a bad impact on the average score.

• Read through all problems in the beginning. Your subconscious mind may work on the problems while you don’t notice…

• Parts of what I thought was important in the lectures, I probably think is important for the exam..

• Snorre will visit after about 1 hour

• Thanks for now, and good luck!