subroutines and interrupts
TRANSCRIPT
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SUB ROUTINES
Instead of repeating same program segments at all locations, they are written and stored separately;
Each such block of instructions which carries out a specific and well defined task is called a ‘Subroutine’.
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SUB ROUTINES
Halt the main program
Provide returning to the same point.
Transfer control to the subroutine.
Execute the subroutine.Revert to the main routine.
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MOVWFCALL bb
aa-2
aa-1
aa
aa+1
aa+2
bb-1
bb
bb+1
cc-1
cc
cc+1
RETURN
Mai
n R
outin
eS
ub R
outin
e
2
3aa+1
1
4
Program Memory
PC ContentSubroutine operations
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Stack contents should remain undisturbed during the execution of the subroutine.Registers used in the main pgm and those in the subroutine are not to be mixed up.While using Goto statement, ensure that program control is brought back to the subroutine (using RETURN)CALL statement has to specify the subroutine address;13 bits PC is generated with 11 bits of address and PCLATH<4:3> as MS bits.
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SUB ROUTINE NESTINGCalling of one subroutine inside
another aa-1
aa
aa+1
bb
dd
dd+1
cc-1
cc
aa+1
dd+1
ee
ff
1 2
4
5
3
7
6
9
7
8
9
CALL bb
CALL ee
RETURN
RETURN
stack
PC content
Programmemory
Main
pro
gram
segm
ent
Subr
outin
e 1
segm
ent
Subr
outin
e 2
segm
ent
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CALL bb[Subroutine 1]
aa CALL bb
PC
aa+1
stack
bb aa+1
CALL ee[Subroutine 2]
Return fromSubroutine 2
Return fromSubroutine 1
dd CALL ee
aa+1
PC
dd+1
ee
stack
dd+1RETURN
aa+1
PC
dd+1
stack
RETURN
PC
stack
aa+1
Sequence of operation during Subroutine nesting….
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Regular operation of the processor is interrupted
and a priority activity is carried out;
once the same is completed,
the regular operation is resumed
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Increment PC
Fetch & execute next instruction
Interrupt Flag
Save return address in stack
Attend to Interrupt (Carry out ISR)
Retrieve return address from Stack
reset
set
Processor Operation while interrupted
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Call occurs at specific and predetermined locations in the main routine.
Can ask for service without any prior notice.Hardware initiated.
Software initiated.Request can come expectedly.
Request can come unexpectedly; may have to carry out some emergency activities-like saving the status of scratch pad registers.
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Any of the peripherals associated with PIC can interrupt the microcontroller.
External Peripherals can also interrupt the processor.
Each interrupt has an associated Interrupt Flag.
Interrupt can be masked by resetting its Interrupt Enable Flag.
Three conditions are to be satisfied for a source to interrupt
The interrupt flag has to be set by the Interrupt Request(IRQ) going high.
The interrupt has to be enabled by the microcontroller by setting the concerned Interrupt Enable Flag.
The GIE flag has to be set-again by the controller.
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PIC 16F877A has 10 sources of interrupt:External Interrupt
TMR0 Over Flow InterruptPORT B Change InterruptComparator InterruptUSART Interrupt TX
USART Interrupt RX
CCP Interrupt
TMR1 Over Flow Interrupt
TMR2 Match Interrupt
Data EEPROM Interrupt
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INTE RBIE T0IF INTFT0IEGIE PEIE RBIFB4 B3 B2 B1B5B7 B6 B0
INTCON REGISTER
GIE GLOBAL INTERRUPT ENABLE BIT
PIE PERIPHERAL INTERRUPT ENABLE BIT
T0IE TMER 0 OVERFLOW INT ENABLE BIT
INTE RB0/INT EXT INT ENABLE BIT
RBIE RB PORT CHANGE INT ENABLE BIT
T0IF TMR0 OVERFLOW INT FLAG BIT
INTF RB0/INT EXT INT FLAG BIT
RBIF RB PORT CHANGE INT FLAG BIT
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TMR1IETMR1IF
TMR2IETMR2IF
CCPIECCPIF
CMIECMIF
TXIETXIF
RXIERXIF
EEIEEEIF
TMR0IETMR0IF
INTFINTE
RBIFRBIE
PEIE
GIE
INT
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Interrupt to CPU
TXIF
1
23
TMR2 IF
EEIF
RCIF
1
23
INTF
TXIE
INTE
1
23
1
23
1
23
RBIFEEIERBIE
TMR1 IE
1
23
1
23
TMR1 IF
TMR2 IE
RCIE
1
23
1
23
PEIE
1
23
1
23
1
23
CCP IF
T0IE
GIE
T0IF
CMIE
1
23
CCP IECMIF
1
23
INTERRUPT LOGIC
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Interrupt Request and Response – Sequence of Activities
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Positioning of ISR in Program Memory
The PIC has the provision to start the ISR at location 0X004HThe location 0X04H can have a simple GOTO ISR instruction.
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0x04h
Interrupt from
source AService routine
A
Service routine B
yes
no
004h BTFSS PIR,A GOTO SRB --------------- --[ISR A]---- ---------------- RETFIESRB : ---[ISR B]--- ------------- RETFIE
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Stores the W register
Stores the Status register
Executes the ISR code
Restores the Status
Restores the W register
The common memory area with addresses 70h to 7Fh can be used to store such data.It eliminates the need to switch banks back and forth to access data during interrupt service.
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Scratchpad register assignment and status saving for each service routine have to be done with care to avoid any mix up.
While using Goto statement, ensure that program control is brought back to the subroutine (using RETFIE)
The return addresses of subroutines as well as those of interrupt services are saved in the same stack.
The service routine can complete the more prioritized task of one source, enable GIE(to allow IRQ from source B) and then take up the second (non priority)task.
If more interrupts which exceeds the 8 level stack, are involved; assign a different processor.
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