Super Sequencer withVoltage Readback ADC

Data Sheet ADM1064

Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Complete supervisory and sequencing solution for up to

10 supplies 10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C <1.0% accuracy across all voltages and temperatures

5 selectable input attenuators allow supervision of supplies to 14.4 V on VH 6 V on VP1 to VP4 (VPx)

5 dual-function inputs, VX1 to VX5 (VXx) High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V General-purpose logic input

10 programmable driver outputs, PDO1 to PDO10 (PDOx) Open-collector with external pull-up Push/pull output, driven to VDDCAP or VPx Open collector with weak pull-up to VDDCAP or VPx Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only) SE implements state machine control of PDO outputs

State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus

12-bit ADC for readback of all supervised voltages 2 auxiliary (single-ended) ADC inputs Reference input (REFIN) has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin More accurate external reference for improved ADC

performance Device powered by the highest of VPx, VH for improved

redundancy User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPx = 1.2 V Available in 40-lead LFCSP and 48-lead TQFP packages

APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies

FUNCTIONAL BLOCK DIAGRAM

0463

3-00

1

PDO7

PDO8

PDO9

PDO10

PDOGND

VDDCAPVDD

ARBITRATOR

GNDVCCP

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

AGND

PROGRAMMABLERESET

GENERATORS

(SFDs)

DUAL-FUNCTION

INPUTS

(LOGIC INPUTSOR

SFDs)

SEQUENCINGENGINE

CONFIGURABLEOUTPUTDRIVERS

(LV CAPABLEOF DRIVING

LOGIC SIGNALS)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

SDA SCL A1 A0

SMBusINTERFACE

REFOUTREFINAUX2AUX1 REFGND

VREF

12-BITSAR ADC

MU

X

EEPROM

ADM1064

CONFIGURABLEOUTPUTDRIVERS

(HV CAPABLE OFDRIVING GATES

OF N-FET)

Figure 1.

GENERAL DESCRIPTION The ADM1064 Super Sequencer® is a configurable supervisory/ sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1064 integrates a 12-bit ADC that can be used to accurately read back up to 12 separate voltages.

The device also provides up to 10 programmable inputs for moni-toring undervoltage faults, overvoltage faults, or out-of-window faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables. Six of these programmable outputs can provide up to a 12 V output for driving the gate of an N-FET that can be placed in the path of a supply.

For more information about the ADM1064 register map, refer to the AN-698 Application Note.

ADM1064 Data Sheet

Rev. E | Page 2 of 31

TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Detailed Block Diagram .................................................................. 4 Specifications ..................................................................................... 5 Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 11 Powering the ADM1064 ................................................................ 14

Slew Rate Consideration ............................................................ 14 Inputs ................................................................................................ 15

Supply Supervision ..................................................................... 15 Programming the Supply Fault Detectors ............................... 15 Input Comparator Hysteresis .................................................... 15 Input Glitch Filtering ................................................................. 16 Supply Supervision with VXx Inputs ....................................... 16 VXx Pins as Digital Inputs ........................................................ 17

Outputs ............................................................................................ 18 Supply Sequencing Through Configurable Output Drivers ...... 18

Default Output Configuration .................................................. 18 Sequencing Engine ......................................................................... 19

Overview ..................................................................................... 19 Warnings...................................................................................... 19 SMBus Jump (Unconditional Jump) ........................................ 19 Sequencing Engine Application Example ............................... 20 Fault and Status Reporting ........................................................ 21

Voltage Readback............................................................................ 22 Supply Supervision with the ADC ........................................... 22

Applications Diagram .................................................................... 23 Communicating with the ADM1064 ........................................... 24

Configuration Download at Power-Up ................................... 24 Updating the Configuration ..................................................... 24 Updating the Sequencing Engine ............................................. 25 Internal Registers ........................................................................ 25 EEPROM ..................................................................................... 25 Serial Bus Interface ..................................................................... 25 SMBus Protocols for RAM and EEPROM .............................. 28 Write Operations ........................................................................ 28 Read Operations ......................................................................... 30

Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31

Data Sheet ADM1064

Rev. E | Page 3 of 31

REVISION HISTORY 1/15—Rev. D to Rev. E Changed Round-Robin Circuit to ADC Round-Robin ....................................................... Throughout Moved Revision History ................................................................... 3 Moved Absolute Maximum Ratings Section ................................. 8 Changes to Figure 3, Figure 4, and Table 4 .................................... 9 Added Slew Rate Consideration Section ...................................... 14 Added VP1 Glitch Filtering Section ............................................. 16 Added SCL Held Low Timeout Section and False Start Detection Section ............................................................................ 26 Updated Outline Dimensions ........................................................ 31 Changes to Ordering Guide ........................................................... 31 6/11—Rev. C to Rev. D Changes to Serial Bus Timing Parameter in Table 1 .................... 4 Change to Figure 3 ............................................................................ 7 Added Exposed Pad Notation to Outline Dimensions .............. 29 Changes to Ordering Guide ........................................................... 29 5/08—Rev. B to Rev. C Changes to Table 1 ............................................................................ 4 Changes to Powering the ADM1064 Section ............................. 13 Changes to Table 5 .......................................................................... 14 Changes to Default Output Configuration Section .................... 16 Changes to Sequence Detector Section ........................................ 18 Changes to Configuration Download at Power-Up Section ..... 22 Changes to Table 10 ........................................................................ 23 Changes to Figure 41 and Error Correction Section .................. 28 Changes to Ordering Guide ........................................................... 29

10/06—Rev. A to Rev B Changes to Features .......................................................................... 1 Changes to Figure 2 .......................................................................... 3 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 7 Changes to Table 3 ............................................................................ 9 Added Table 4 .................................................................................... 9 Changes to Inputs Section ............................................................. 14 Changes to Outputs Section .......................................................... 17 Added Default Output Configuration Section ............................ 18 Changes to Fault Reporting Section ............................................. 22 Changes to Voltage Readback Section .......................................... 23 Changes to Identifying the ADM1064 on the SMBus Section.. 27 Changes to Figure 31 and Figure 32 ............................................. 28 Changes to Figure 43 Caption ....................................................... 32 Change to Ordering Guide ............................................................ 32 1/05—Rev. 0 to Rev A Changes to Figure 1 .......................................................................... 1 Changes to Absolute Maximum Ratings Section ......................... 8 Change to Supply Sequencing through Configurable Output Drivers Section .................................................................. 16 Changes to Figure 33 ...................................................................... 21 Change to Table 9 ............................................................................ 24 10/04—Revision 0: Initial Version

ADM1064 Data Sheet

Rev. E | Page 4 of 31

The logical core of the device is a sequencing engine (SE). This state machine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs.

The device is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc.

DETAILED BLOCK DIAGRAM

0463

3-00

2

GPI SIGNALCONDITIONING

SFD

GPI SIGNALCONDITIONING

SFD

SFD

SFD

SELECTABLEATTENUATOR

SELECTABLEATTENUATOR

DEVICECONTROLLER

OSC

EEPROM

SDA SCL A1 A0

SMBusINTERFACE

REFOUTREFIN

AUX1AUX2 REFGND

VREF

12-BITSAR ADC

ADM1064

CONFIGURABLEOUTPUT DRIVER

(HV)PDO1

PDO2

PDOGND

PDO3

GND

PDO4

PDO5

PDO8

PDO9

CONFIGURABLEOUTPUT DRIVER

(HV)PDO6

CONFIGURABLEOUTPUT DRIVER

(LV)PDO7

CONFIGURABLEOUTPUT DRIVER

(LV)PDO10

SEQUENCINGENGINE

VX2

VX3

VX4

VP2

VP3

VP4

VH

VP1

VX1

AGND

VX5

VDDARBITRATOR

REG 5.25VCHARGE PUMP

VDDCAP

VCCP

Figure 2.

Data Sheet ADM1064

Rev. E | Page 5 of 31

SPECIFICATIONS VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of VH, VPx pins VPx 6.0 V Maximum VDDCAP = 5.1 V, typical VH 14.4 V VDDCAP = 4.75 V VDDCAP 2.7 4.75 5.4 V Regulated LDO output CVDDCAP 10 μF Minimum recommended decoupling capacitance

POWER SUPPLY Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, ADC off Additional Currents

All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each, PDO7 to PDO10 off

Current Available from VDDCAP 2 mA Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP

ADC Supply Current 1 mA Running round-robin loop EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS VH Pin

Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Midrange and high range Detection Ranges

High Range 6 14.4 V Midrange 2.5 6 V

VPx Pins Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Low range and midrange Detection Ranges

Midrange 2.5 6 V Low Range 1.25 3 V Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins Input Impedance 1 MΩ Detection Ranges

Ultralow Range 0.573 1.375 V No input attenuation error Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator offset error

+ input attenuation error Threshold Resolution 8 Bits Digital Glitch Filter 0 μs Minimum programmable filter length 100 μs Maximum programmable filter length

ANALOG-TO-DIGITAL CONVERTER Signal Range 0 VREFIN V The ADC can convert signals presented to the VH,

VPx, and VXx pins; VPx and VH input signals are attenuated depending on the selected range; a signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input.

Input Reference Voltage on REFIN Pin, VREFIN 2.048 V Resolution 12 Bits INL ±2.5 LSB Endpoint corrected, VREFIN = 2.048 V Gain Error ±0.05 % VREFIN = 2.048 V

ADM1064 Data Sheet

Rev. E | Page 6 of 31

Parameter Min Typ Max Unit Test Conditions/Comments Conversion Time 0.44 ms One conversion on one channel 84 ms All 12 channels selected, averaging enabled Offset Error ±2 LSB VREFIN = 2.048 V Input Noise 0.25 LSB rms Direct input (no attenuator)

REFERENCE OUTPUT Reference Output Voltage 2.043 2.048 2.053 V No load Load Regulation −0.25 mV Sourcing current 0.25 mV Sinking current Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability PSRR 60 dB DC

PROGRAMMABLE DRIVER OUTPUTS High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance 500 kΩ VOH 11 12.5 14 V IOH = 0 μA 10.5 12 13.5 V IOH = 1 μA IOUTAVG 20 μA 2 V < VOH < 7 V

Standard (Digital Output) Mode (PDO1 to PDO10)

VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA 4.5 V VPU to VPx = 6.0 V, IOH = 0 mA VPU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA VOL 0 0.50 V IOL = 20 mA IOL

2 20 mA Maximum sink current per PDOx pin

ISINK2 60 mA Maximum total sink for all PDOx pins

RPULL-UP 16 20 29 kΩ Internal pull-up ISOURCE (VPx)2 2 mA Current load on any VPx pull-ups, that is, total source

current available through any number of PDOx pull-up switches configured onto any one VPx pin

Three-State Output Leakage Current 10 μA VPDO = 14.4 V Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1) Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V Input High Current, IIH −1 μA VIN = 5.5 V Input Low Current, IIL 1 μA VIN = 0 Input Capacitance 5 pF Programmable Pull-Down Current, IPULL-DOWN 20 μA VDDCAP = 4.75 V, TA = 25°C, if known logic state is

required SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Output Low Voltage, VOL

2 0.4 V IOUT = −3.0 mA SERIAL BUS TIMING3

Clock Frequency, fSCLK 400 kHz Bus Free Time, tBUF 1.3 μs Start Setup Time, tSU;STA 0.6 μs Stop Setup Time, tSU;STO 0.6 μs Start Hold Time, tHD;STA 0.6 μs SCL Low Time, tLOW 1.3 μs SCL High Time, tHIGH 0.6 μs SCL, SDA Rise Time, tR 300 ns SCL, SDA Fall Time, tF 300 ns

Data Sheet ADM1064

Rev. E | Page 7 of 31

Parameter Min Typ Max Unit Test Conditions/Comments Data Setup Time, tSU;DAT 100 ns Data Hold Time, tHD;DAT 5 ns Input Low Current, IIL 1 μA VIN = 0 V

SEQUENCING ENGINE TIMING State Change Time 10 μs

1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Timing specifications are guaranteed by design and supported by characterization data.

ADM1064 Data Sheet

Rev. E | Page 8 of 31

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Voltage on VH Pin 16 V Voltage on VPx Pins 7 V Voltage on VXx Pins −0.3 V to +6.5 V Voltage on A0, A1 Pins −0.3 V to +7 V Voltage on REFIN, REFOUT Pins 5 V Voltage on VDDCAP, VCCP Pins 6.5 V Voltage on PDOx Pins 16 V Voltage on SDA, SCL Pins 7 V Voltage on AUX1, AUX2 Pins −0.3 V to +5 V Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature,

Soldering Vapor Phase, 60 sec 215°C ESD Rating, All Pins 2000 V

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance Package Type θJA Unit 40-Lead LFCSP 25 °C/W 48-Lead TQFP 50 °C/W

ESD CAUTION

Data Sheet ADM1064

Rev. E | Page 9 of 31

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

0463

3-00

3

NOTES1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.2. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM. THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS PAD SHOULD BE SOLDERED TO THE BOARD FOR IMPROVED MECHANICAL STABILITY.

ADM1064TOP VIEW

(Not to Scale)

GN

D

40V

DD

CA

P39

AU

X1

38

AU

X2

37

SD

A

36

SC

L

35

A1

34

A0

33

VC

CP

32

PD

OG

ND

31

AG

ND

11

RE

FG

ND

12

RE

FIN

13

RE

FO

UT

14

NC

15

NC

16

NC

17

NC

18

NC

19

NC

20

VX1 1

VX2 2

VX3 3

VX4 4

VX5 5

VP1 6

VP2 7

VP3 8

VP4 9

VH 10

PDO130

PDO229

PDO328

PDO427

PDO526

PDO625

PDO724

PDO823

PDO922

PDO1021

PIN 1INDICATOR

Figure 3. 40-Lead LFCSP Pin Configuration

0463

3-00

4

NOTES1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

NC

48

GN

D

47

VD

DC

AP

46

AU

X1

45

AU

X2

44

SD

A

43

SC

L

42

A1

41

A0

40

VC

CP

39

PD

OG

ND

38

NC

37

NC

13

AG

ND

14

RE

FG

ND

15

RE

FIN

16

RE

FO

UT

17

NC

18

NC

19

NC

20

NC

21

NC

22

NC

23

NC

24

NC 1

VX1 2

VX2 3

VX3 4

VX4 5

VX5 6

VP1 7

VP2 8

VP3 9

VP4 10

VH 11

NC 12

NC36

PDO135

PDO234

PDO333

PDO432

PDO531

PDO630

PDO729

PDO828

PDO927

PDO1026

NC25

ADM1064TOP VIEW

(Not to Scale)

PIN 1INDICATOR

Figure 4. 48-Lead TQFP Pin Configuration

Table 4. Pin Function Descriptions Pin No.

Mnemonic Description 40-Lead LFCSP

48-Lead TQFP

15 to 20 1, 12, 13, 18 to 25, 36, 37, 48

NC No Connect. Do not connect to this pin.

1 to 5 2 to 6 VX1 to VX5 (VXx)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9 7 to 10 VP1 to VP4 (VPx)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to these pins, the output of which connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and from 0.573 V to 1.375 V.

10 11 VH High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.

11 14 AGND1 Ground Return for Input Attenuators. 12 15 REFGND Ground Return for On-Chip Reference Circuits. 13 16 REFIN Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.

The on-board reference can be used by connecting the REFOUT pin to the REFIN pin. 14 17 REFOUT1 Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be connected

between this pin and REFGND. A 10 μF capacitor is recommended for this purpose. 21 to 30 26 to 35 PDO10 to

PDO1 Programmable Output Drivers.

31 38 PDOGND1 Ground Return for Output Drivers. 32 39 VCCP Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin

and GND. A 10 μF capacitor is recommended for this purpose. 33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address. 34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address. 35 42 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up. 36 43 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up. 37 44 AUX2 Auxiliary, Single-Ended ADC Input.

ADM1064 Data Sheet

Rev. E | Page 10 of 31

Pin No.

Mnemonic Description 40-Lead LFCSP

48-Lead TQFP

38 45 AUX1 Auxiliary, Single-Ended ADC Input. 39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.

Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for this purpose.

40 47 GND1 Supply Ground. N/A2 EPAD Exposed Pad. The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this

pad should be soldered to the board for improved mechanical stability. 1 In a typical application, all ground pins are connected together. 2 N/A is not applicable.

Data Sheet ADM1064

Rev. E | Page 11 of 31

TYPICAL PERFORMANCE CHARACTERISTICS 6

0

1

2

3

4

5

0 654321

0463

3-05

0

VVP1 (V)

VV

DD

CA

P (

V)

Figure 5. VVDDCAP vs. VVP1

6

0

1

2

3

4

5

0 161412108642

0463

3-05

1

VVH (V)

VV

DD

CA

P (

V)

Figure 6. VVDDCAP vs. VVH

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 1 2 3 4 5 6

0463

3-05

2

VVP1 (V)

I VP

1 (m

A)

Figure 7. IVP1 vs. VVP1 (VP1 as Supply)

180

160

140

120

100

80

60

40

20

00 1 2 3 4 5 6

0463

3-05

3

VVP1 (V)

I VP

1 (

µA

)

Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 161412108642

0463

3-05

4

VVH (V)

I VH

(m

A)

Figure 9. IVH vs. VVH (VH as Supply)

350

300

250

200

150

100

50

00 654321

0463

3-05

5

VVH (V)

I VH

(µ

A)

Figure 10. IVH vs. VVH (VH Not as Supply)

ADM1064 Data Sheet

Rev. E | Page 12 of 31

14

12

10

8

6

4

2

00 15.012.510.07.55.02.5

0463

3-05

6

ILOAD (µA)

CH

AR

GE

-PU

MP

ED

VP

DO

1 (

V)

Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 654321

0463

3-05

7

ILOAD (mA)

VP

DO

1 (V

)

VP1 = 5V

VP1 = 3V

Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 605040302010

0463

3-05

8

ILOAD (µA)

VP

DO

1 (

V)

VP1 = 5V

VP1 = 3V

Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

40001000 2000 30000

0463

3-06

6

CODE

DN

L (

LS

B)

Figure 14. DNL for ADC

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0 4000300020001000

0463

3-06

3

CODE

INL

(L

SB

)

Figure 15. INL for ADC

12000

10000

8000

6000

4000

2000

0204920482047

0463

3-06

4

CODE

HIT

S P

ER

CO

DE

81

9894

25

Figure 16. ADC Noise, Midcode Input, 10,000 Reads

Data Sheet ADM1064

Rev. E | Page 13 of 31

2.058

2.038

2.043

2.048

2.053

–40 –20 0 20 40 60 10080

0463

3-06

1

TEMPERATURE (C)

RE

FO

UT

(V

) VP1 = 3.0V

VP1 = 4.75V

Figure 17. REFOUT vs. Temperature

ADM1064 Data Sheet

Rev. E | Page 14 of 31

POWERING THE ADM1064 The ADM1064 is powered from the highest voltage input on either the positive-only supply inputs (VPx) or the high voltage supply input (VH). This technique offers improved redundancy because the device is not dependent on any particular voltage rail to keep it operational. The same pins are used for supply fault detection (see the Supply Supervision section). A VDD arbitrator on the device chooses which supply to use. The arbitrator can be considered an OR’ing of five low dropout regulators (LDOs) together. A supply comparator chooses the highest input to provide the on-chip supply. There is minimal switching loss with this architecture (~0.2 V), resulting in the ability to power the ADM1064 from a supply as low as 3.0 V. Note that the supply on the VXx pins cannot be used to power the device.

An external capacitor to GND is required to decouple the on-chip supply from noise. This capacitor should be connected to the VDDCAP pin, as shown in Figure 18. The capacitor has another use during brownouts (momentary loss of power). Under these conditions, when the input supply (VPx or VH) dips transiently below VDD, the synchronous rectifier switch immediately turns off so that it does not pull VDD down. The VDD capacitor can then act as a reservoir to keep the device active until the next highest supply takes over the powering of the device. A 10 μF capacitor is recommended for this reservoir/decoupling function.

The VH input pin can accommodate supplies up to 14.4 V, which allows the ADM1064 to be powered using a 12 V backplane supply. In cases where this 12 V supply is hot swapped, it is recommended that the ADM1064 not be connected directly to the supply. Suitable precautions, such as the use of a hot swap controller, should be taken to protect the device from transients that could cause damage during hot swap events.

When two or more supplies are within 100 mV of each other, the supply that first takes control of VDD keeps control. For example, if VP1 is connected to a 3.3 V supply, VDD powers up to approximately 3.1 V through VP1. If VP2 is then connected to another 3.3 V supply, VP1 still powers the device, unless VP2 goes 100 mV higher than VP1.

SUPPLYCOMPARATOR

IN

EN

OUT4.75VLDO

IN

EN

OUT4.75VLDO

IN

EN

OUT4.75VLDO

IN

EN

OUT4.75VLDO

IN

EN

OUT4.75VLDO

VH

VP4

VP3

VP2

VP1VDDCAP

INTERNALDEVICESUPPLY

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Figure 18. VDD Arbitrator Operation

SLEW RATE CONSIDERATION When the ambient temperature of operation is less than approximately −20°C, and in the event of a power loss where all supply inputs fail for less than a few hundreds of milliseconds (for example, due to a system supply brownout), it is recommended that the supply voltage recover with a ramp rate of at least 1.5 V/ms or less than 0.5 V/ms.

Data Sheet ADM1064

Rev. E | Page 15 of 31

INPUTS SUPPLY SUPERVISION The ADM1064 has 10 programmable inputs. Five of these are dedicated supply fault detectors (SFDs). These dedicated inputs are called VH and VPx (VP1 to VP4) by default. The other five inputs are labeled VXx (VX1 to VX5) and have dual functionality. They can be used either as SFDs with functionality similar to VH and VPx, or as CMOS-/TTL-compatible logic inputs to the device. Therefore, the ADM1064 can have up to 10 analog inputs, a minimum of five analog inputs and five digital inputs, or a combination thereof. If an input is used as an analog input, it cannot be used as a digital input. Therefore, a configuration requiring 10 analog inputs has no available digital inputs. Table 6 shows the details of each input.

PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1064 can have up to 10 SFDs on its 10 input channels. These highly programmable reset generators enable the supervision of up to 10 supply voltages. The supplies can be as low as 0.573 V and as high as 14.4 V. The inputs can be configured to detect an undervoltage fault (the input voltage drops below a prepro-grammed value), an overvoltage fault (the input voltage rises above a preprogrammed value), or an out-of-window fault (the input voltage is outside a preprogrammed range). The thresholds can be programmed to an 8-bit resolution in registers provided in the ADM1064. This translates to a voltage resolution that is dependent on the range selected.

The resolution is given by

Step Size = Threshold Range/255

Therefore, if the high range is selected on VH, the step size can be calculated as follows:

(14.4 V − 6.0 V)/255 = 32.9 mV

Table 5 lists the upper and lower limits of each available range, the bottom of each range (VB), and the range itself (VR).

Table 5. Voltage Range Limits Voltage Range (V) VB (V) VR (V) 0.573 to 1.375 0.573 0.802 1.25 to 3.00 1.25 1.75 2.5 to 6.0 2.5 3.5 6.0 to 14.4 6.0 8.4

The threshold value required is given by

VT = (VR × N)/255 + VB

where: VT is the desired threshold voltage (undervoltage or overvoltage). VR is the voltage range. N is the decimal value of the 8-bit code. VB is the bottom of the range.

Reversing the equation, the code for a desired threshold is given by

N = 255 × (VT − VB)/VR

For example, if the user wants to set a 5 V overvoltage threshold on VP1, the code to be programmed in the PS1OVTH register (as discussed in the AN-698 Application Note) is given by

N = 255 × (5 − 2.5)/3.5

Therefore, N = 182 (1011 0110 or 0xB6).

INPUT COMPARATOR HYSTERESIS The UV and OV comparators shown in Figure 19 are always monitoring VPx. To avoid chatter (multiple transitions when the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can be programmed up to the values shown in Table 6.

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+

–

+

–

UVCOMPARATOR

VREF

FAULT TYPESELECT

OVCOMPARATOR

FAULTOUTPUT

GLITCHFILTER

VPx

MID

LOW

RANGESELECT

ULTRALOW

Figure 19. Supply Fault Detector Block

The hysteresis is added after a supply voltage goes out of tolerance. Therefore, the user can program the amount above the under-voltage threshold to which the input must rise before an undervoltage fault is deasserted. Similarly, the user can program the amount below the overvoltage threshold to which an input must fall before an overvoltage fault is deasserted.

Table 6. Input Functions, Thresholds, and Ranges Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (μs) VH High Voltage Analog Input 2.5 to 6.0 425 mV 13.7 0 to 100 6.0 to 14.4 1.02 V 32.9 0 to 100 VPx Positive Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100 1.25 to 3.00 212 mV 6.8 0 to 100 2.5 to 6.0 425 mV 13.7 0 to 100 VXx High-Z Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100 Digital Input 0 to 5.0 N/A N/A 0 to 100

ADM1064 Data Sheet

Rev. E | Page 16 of 31

The hysteresis value is given by

VHYST = VR × NTHRESH/255

where: VHYST is the desired hysteresis voltage. NTHRESH is the decimal value of the 5-bit hysteresis code.

Note that NTHRESH has a maximum value of 31. The maximum hysteresis for the ranges is listed in Table 6.

INPUT GLITCH FILTERING The final stage of the SFDs is a glitch filter. This block provides time-domain filtering on the output of the SFD comparators, which allows the user to remove any spurious transitions such as supply bounce at turn-on. The glitch filter function is in addition to the digitally programmable hysteresis of the SFD compara-tors. The glitch filter timeout is programmable up to 100 μs.

For example, when the glitch filter timeout is 100 μs, any pulse appearing on the input of the glitch filter block that is less than 100 μs in duration is prevented from appearing on the output of the glitch filter block. Any input pulse that is longer than 100 μs appears on the output of the glitch filter block. The output is delayed with respect to the input by 100 μs. The filtering process is shown in Figure 20.

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t0 tGF t0 tGF

t0 tGF t0 tGF

INPUT

INPUT PULSE SHORTERTHAN GLITCH FILTER TIMEOUT

INPUT PULSE LONGERTHAN GLITCH FILTER TIMEOUT

OUTPUT

PROGRAMMEDTIMEOUT

PROGRAMMEDTIMEOUT

INPUT

OUTPUT

Figure 20. Input Glitch Filter Function

VP1 Glitch Filtering

If the ADC round-robin is used, it is recommended to enable glitch filtering on VP1 because the ADC input mux is connected to VP1 when the ADC round-robin stops. When the ADC round-robin stops, a small internal glitch on the VP1 monitor rail occurs, and if the rail is close to the UV threshold, it may be enough to trip the VP1 UV comparator. Use any value of glitch filter greater than 0 μs to avoid false UV triggers. For more information about the ADC round-robin, see the Voltage Readback section.

SUPPLY SUPERVISION WITH VXx INPUTS The VXx inputs have two functions. They can be used as either supply fault detectors or digital logic inputs. When selected as analog (SFD) inputs, the VXx pins have functionality that is very similar to the VH and VPx pins. The primary difference is that the VXx pins have only one input range: 0.573 V to 1.375 V. Therefore, these inputs can directly supervise only the very low supplies. However, the input impedance of the VXx pins is high, allowing an external resistor divide network to be connected to the pin. Thus, potentially any supply can be divided down into the input range of the VXx pin and supervised, enabling the ADM1064 to monitor other supplies, such as +24 V, +48 V, and −5 V.

An additional supply supervision function is available when the VXx pins are selected as digital inputs. In this case, the analog function is available as a second detector on each of the dedi-cated analog inputs, VPx and VH. The analog function of VX1 is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is mapped to VH. In this case, these SFDs can be viewed as secondary or warning SFDs.

The secondary SFDs are fixed to the same input range as the primary SFDs. They are used to indicate warning levels rather than failure levels. This allows faults and warnings to be gener-ated on a single supply using only one pin. For example, if VP1 is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can be set to output a warning at 3.1 V. Warning outputs are available for readback from the status registers. They are also OR’ed together and fed into the SE, allowing warnings to generate interrupts on the programmable driver outputs (PDOs). Therefore, in this example, if the supply drops to 3.1 V, a warning is generated, and remedial action can be taken before the supply drops out of tolerance.

Data Sheet ADM1064

Rev. E | Page 17 of 31

VXx PINS AS DIGITAL INPUTS As discussed in the Supply Supervision with VXx Inputs section, the VXx input pins on the ADM1064 have dual functionality. The second function is as digital logic inputs to the device. Therefore, the ADM1064 can be configured for up to five digital inputs. These inputs are TTL-/CMOS-compatible. Standard logic signals can be applied to the pins: RESET from reset generators, PWRGD signals, fault flags, manual resets, and so on. These signals are available as inputs to the SE and, therefore, can be used to control the status of the PDOs. The inputs can be configured to detect either a change in level or an edge.

When configured for level detection, the output of the digital block is a buffered version of the input. When configured for edge detection, a pulse of programmable width is output from the digital block once the logic transition is detected. The width is programmable from 0 μs to 100 μs.

The digital blocks feature the same glitch filter function that is available on the SFDs. This enables the user to ignore spurious transitions on the inputs. For example, the filter can be used to debounce a manual reset switch.

When configured as digital inputs, each VXx pin has a weak (10 μA) pull-down current source available for placing the input into a known condition, even if left floating. The current source, if selected, weakly pulls the input to GND.

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DETECTOR

VXx(DIGITAL INPUT)

GLITCHFILTER

VREF = 1.4V

TOSEQUENCINGENGINE

+

–

Figure 21. VXx Digital Input Function

ADM1064 Data Sheet

Rev. E | Page 18 of 31

OUTPUTS SUPPLY SEQUENCING THROUGH CONFIGURABLE OUTPUT DRIVERS Supply sequencing is achieved with the ADM1064 using the programmable driver outputs (PDOs) on the device as control signals for supplies. The output drivers can be used as logic enables or as FET drivers.

The sequence in which the PDOs are asserted (and, therefore, the supplies are turned on) is controlled by the sequencing engine (SE). The SE determines what action is taken with the PDOs, based on the condition of the ADM1064 inputs. Therefore, the PDOs can be set up to assert when the SFDs are in tolerance, the correct input signals are received on the VXx digital pins, no warnings are received from any of the inputs of the device, and at other times. The PDOs can be used for a variety of functions. The primary function is to provide enable signals for LDOs or dc-to-dc converters that generate supplies locally on a board. The PDOs can also be used to provide a PWRGD signal when all the SFDs are in tolerance or a RESET output if one of the SFDs goes out of specification (this can be used as a status signal for a DSP, FPGA, or other microcontroller).

The PDOs can be programmed to pull up to a number of different options. The outputs can be programmed as follows:

Open drain (allowing the user to connect an external pull-up resistor).

Open drain with weak pull-up to VDD. Open drain with strong pull-up to VDD. Open drain with weak pull-up to VPx. Open drain with strong pull-up to VPx. Strong pull-down to GND. Internally charge-pumped high drive (12 V, PDO1 to

PDO6 only).

The last option (available only on PDO1 to PDO6) allows the user to directly drive a voltage high enough to fully enhance an external N-FET, which is used to isolate, for example, a card-side voltage from a backplane supply (a PDO can sustain greater than 10.5 V into a 1 μA load). The pull-down switches can also be used to drive status LEDs directly.

The data driving each of the PDOs can come from one of three sources. The source can be enabled in the PDOxCFG configuration register (see the AN-698 Application Note for details).

The data sources are as follows:

Output from the SE. Directly from the SMBus. A PDO can be configured so that

the SMBus has direct control over it. This enables software control of the PDOs. Therefore, a microcontroller can be used to initiate a software power-up/power-down sequence.

On-chip clock. A 100 kHz clock is generated on the device. This clock can be made available on any of the PDOs. It can be used, for example, to clock an external device such as an LED.

DEFAULT OUTPUT CONFIGURATION All of the internal registers in an unprogrammed ADM1064 device from the factory are set to 0. Because of this, the PDOx pins are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.

As the input supply to the ADM1064 ramps up on VPx or VH, all PDOx pins behave as follows:

Input supply = 0 V to 1.2 V. The PDOs are high impedance. Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND

by a weak (20 kΩ) on-chip pull-down resistor. Supply > 2.7 V. Factory-programmed devices continue to pull

all PDOs to GND by a weak (20 kΩ) on-chip pull-down resistor. Programmed devices download current EEPROM configuration data, and the programmed setup is latched. The PDO then goes to the state demanded by the configuration. This provides a known condition for the PDOs during power-up.

The internal pull-down can be overdriven with an external pull-up of suitable value tied from the PDOx pin to the required pull-up voltage. The 20 kΩ resistor must be accounted for in calculating a suitable value. For example, if PDOx must be pulled up to 3.3 V, and 5 V is available as an external supply, the pull-up resistor value is given by

3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)

Therefore,

RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ

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PDO

SE DATA

CFG4 CFG5 CFG6

SMBus DATA

CLK DATA

10Ω

20kΩ

10Ω

20kΩ

VP1SELVP4

10Ω

20kΩ

VDD

VFET (PDO1 TO PDO6 ONLY)

20kΩ

Figure 22. Programmable Driver Output

Data Sheet ADM1064

Rev. E | Page 19 of 31

SEQUENCING ENGINE OVERVIEW The ADM1064 sequencing engine (SE) provides the user with powerful and flexible control of sequencing. The SE implements a state machine control of the PDO outputs, with state changes conditional on input events. SE programs can enable complex control of boards, including power-up and power-down sequence control, fault event handling, and interrupt generation on warnings. A watchdog function that verifies the continued operation of a processor clock can be integrated into the SE program. The SE can also be controlled via the SMBus, giving software or firmware control of the board sequencing.

The SE state machine comprises 63 state cells. Each state has the following attributes:

Monitors signals indicating the status of the 10 input pins, VP1 to VP4, VH, and VX1 to VX5.

Can be entered from any other state. Three exit routes move the state machine onto a next state:

sequence detection, fault monitoring, and timeout. Delay timers for the sequence and timeout blocks can be

programmed independently and changed with each state change. The range of timeouts is from 0 ms to 400 ms.

Output condition of the 10 PDO pins is defined and fixed within a state.

Transition from one state to the next is made in less than 20 μs, which is the time needed to download a state definition from EEPROM to the SE.

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SEQUENCE

TIMEOUTMONITOR

FAULT STATE

Figure 23. State Cell

The ADM1064 offers up to 63 state definitions. The signals monitored to indicate the status of the input pins are the outputs of the SFDs.

WARNINGS The SE also monitors warnings. These warnings can be generated when the ADC readings violate their limit register value or when the secondary voltage monitors on VPx and VH are triggered. The warnings are OR’ed together and are available as a single warning input to each of the three blocks that enable exiting a state.

SMBus JUMP (UNCONDITIONAL JUMP) The SE can be forced to advance to the next state uncondition-ally. This enables the user to force the SE to advance. Examples of the use of this feature include moving to a margining state or debugging a sequence. The SMBus jump or go-to command can be seen as another input to sequence and timeout blocks to provide an exit from each state.

Table 7. Sample Sequence State Entries State Sequence Timeout Monitor IDLE1 If VX1 is low , go to State IDLE2. IDLE2 If VP1 is okay, go to State EN3V3. EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms,

go to State DIS3V3. If VP1 is not okay, go to State IDLE1.

DIS3V3 If VX1 is high, go to State IDLE1. EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms,

go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.

DIS2V5 If VX1 is high, go to State IDLE1. FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2. FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1. PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.

ADM1064 Data Sheet

Rev. E | Page 20 of 31

SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE. Figure 25 shows how the simple building block of a single SE state can be used to build a power-up sequence for a three-supply system. Table 8 lists the PDOs for each state in the same SE implementation. In this system, a good 5 V supply on VP1 and the VX1 pin held low are the triggers required to start a power-up sequence. The sequence next turns on the 3.3 V supply, then the 2.5 V supply (assuming successful turn-on of the 3.3 V supply). When all three supplies have turned on correctly, the PWRGD state is entered, where the SE remains until a fault occurs on one of the three supplies or until it is instructed to go through a power-down sequence by VX1 going high.

Faults are dealt with throughout the power-up sequence on a case-by-case basis. The following three sections (the Sequence Detector section, the Monitoring Fault Detector section, and the Timeout Detector section) describe the individual blocks and use the sample application shown in Figure 25 to demonstrate the actions of the state machine.

Sequence Detector

The sequence detector block is used to detect when a step in a sequence is complete. It looks for one of the SE inputs to change state and is most often used as the gate for successful progress through a power-up or power-down sequence. A timer block that is included in this detector can insert delays into a power-up or power-down sequence, if required. Timer delays can be set from 10 μs to 400 ms. Figure 24 is a block diagram of the sequence detector.

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SUPPLY FAULTDETECTION

LOGIC INPUT CHANGEOR FAULT DETECTION

WARNINGS

FORCE FLOW(UNCONDITIONAL JUMP)

VP1

VX5

INVERT

SEQUENCEDETECTOR

SELECT

TIMER

Figure 24. Sequence Detector Block Diagram

If a timer delay is specified, the input to the sequence detector must remain in the defined state for the duration of the timer delay. If the input changes state during the delay, the timer is reset.

The sequence detector can also help to identify monitoring faults. In the sample application shown in Figure 25, the FSEL1 and FSEL2 states first identify which of the VP1,VP2, or VP3 pins has faulted, and then they take appropriate action.

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IDLE1

IDLE2

EN3V3

DIS3V3

DIS2V5PWRGD

FSEL1

FSEL2

SEQUENCESTATES

MONITOR FAULTSTATES

TIMEOUTSTATES

VX1 = 0

VP1 = 1

VP1 = 0

(VP1 + VP2) = 0

(VP1 + VP2 + VP3) = 0

(VP1 +VP2) = 0

VP2 = 1

VP3 = 1

VP2 = 0

VX1 = 1

VP3 = 0

VP2 = 0

VP1 = 0

VX1 = 1

VX1 = 1

10ms

20ms

EN2V5

Figure 25. Sample Application Flow Diagram

Table 8. PDO Outputs for Each State PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2 PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1 PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1 PDO3 = FAULT 0 0 0 0 1 1 0 1 1

Data Sheet ADM1064

Rev. E | Page 21 of 31

Monitoring Fault Detector

The monitoring fault detector block is used to detect a failure on an input. The logical function implementing this is a wide OR gate that can detect when an input deviates from its expected condition. The clearest demonstration of the use of this block is in the PWRGD state, where the monitor block indicates that a failure on one or more of the VP1,VP2, or VP3 inputs has occurred.

No programmable delay is available in this block because the triggering of a fault condition is likely to be caused by a supply falling out of tolerance. In this situation, the device needs to react as quickly as possible. Some latency occurs when moving out of this state because it takes a finite amount of time (~20 μs) for the state configuration to download from EEPROM into the SE. Figure 26 is a block diagram of the monitoring fault detector.

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SUPPLY FAULTDETECTION

LOGIC INPUT CHANGEOR FAULT DETECTION

VP1

VX5

MONITORING FAULTDETECTOR

MASKSENSE

1-BIT FAULTDETECTOR

FAULT

WARNINGS

MASK

1-BIT FAULTDETECTOR

FAULT

MASKSENSE

1-BIT FAULTDETECTOR

FAULT

Figure 26. Monitoring Fault Detector Block Diagram

Timeout Detector

The timeout detector allows the user to trap a failure to ensure proper progress through a power-up or power-down sequence.

In the sample application shown in Figure 25, the timeout next-state transition is from the EN3V3 and EN2V5 states. For the EN3V3 state, the signal 3V3ON is asserted on the PDO1 output pin upon entry to this state to turn on a 3.3 V supply. This supply rail is connected to the VP2 pin, and the sequence detector looks for the VP2 pin to go above its undervoltage threshold, which is set in the supply fault detector (SFD) attached to that pin.

The power-up sequence progresses when this change is detected. If, however, the supply fails (perhaps due to a short circuit overloading this supply), the timeout block traps the problem. In this example, if the 3.3 V supply fails within 10 ms, the SE moves to the DIS3V3 state and turns off this supply by bringing PDO1 low. It also indicates that a fault has occurred by taking PDO3 high. Timeout delays of 100 μs to 400 ms can be programmed.

FAULT AND STATUS REPORTING The ADM1064 has a fault latch for recording faults. Two registers, FSTAT1 and FSTAT2, are set aside for this purpose. A single bit is assigned to each input of the device, and a fault on that input sets the relevant bit. The contents of the fault register can be read out over the SMBus to determine which input(s) faulted. The fault register can be enabled/disabled in each state. To latch data from one state, ensure that the fault latch is disabled in the following state. This ensures that only real faults are captured and not, for example, undervoltage conditions that may be present during a power-up or power-down sequence.

The ADM1064 also has a number of status registers. These include more detailed information, such as whether an undervoltage or overvoltage fault is present on a particular input. The status registers also include information on ADC limit faults. Note that the data in the status registers is not latched in any way and, therefore, is subject to change at any time.

See the AN-698 Application Note for full details about the ADM1064 registers.

ADM1064 Data Sheet

Rev. E | Page 22 of 31

VOLTAGE READBACK The ADM1064 has an on-board 12-bit accurate ADC for voltage readback over the SMBus. The ADC has a 12-channel analog mux on the front end. The 12 channels consist of the 10 SFD inputs (VH, VPx, and VXx) and two auxiliary (single-ended) ADC inputs (AUX1 and AUX2). Any or all of these inputs can be selected to be read, in turn, by the ADC. The circuit controlling this operation is called the ADC round-robin. This circuit can be selected to run through its loop of conversions once or continuously. Averaging is also provided for each channel. In this case, the ADC round-robin runs through its loop of conversions 16 times before returning a result for each channel. At the end of this cycle, the results are written to the output registers.

The ADC samples single-sided inputs with respect to the AGND pin. A 0 V input gives out Code 0, and an input equal to the voltage on REFIN gives out full code (4095 decimal).

The inputs to the ADC come directly from the VXx pins and from the back of the input attenuators on the VPx and VH pins, as shown in Figure 27 and Figure 28.

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VXx

2.048V VREF

NO ATTENUATION

12-BITADC

DIGITIZEDVOLTAGEREADING

Figure 27. ADC Reading on VXx Pins

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2.048V VREF

ATTENUATION NETWORK(DEPENDS ON RANGE SELECTED)

12-BITADC

DIGITIZEDVOLTAGEREADING

VPx/VH

Figure 28. ADC Reading on VPx/VH Pins

The voltage at the input pin can be derived from the following equation:

V = 4095

CodeADC × Attenuation Factor × VREFIN

where VREFIN = 2.048 V when the internal reference is used (that is, the REFIN pin is connected to the REFOUT pin).

The ADC input voltage ranges for the SFD input ranges are listed in Table 9.

Table 9. ADC Input Voltage Ranges SFD Input Range (V) Attenuation Factor

ADC Input Voltage Range (V)

0.573 to 1.375 1 0 to 2.048 1.25 to 3.00 2.181 0 to 4.46 2.5 to 6.0 4.363 0 to 6.01 6.0 to 14.4 10.472 0 to 14.41 1 The upper limit is the absolute maximum allowed voltage on the VPx and

VH pins.

The typical way to supply the reference to the ADC on the REFIN pin is to connect the REFOUT pin to the REFIN pin. REFOUT provides a 2.048 V reference. As such, the supervising range covers less than half the normal ADC range. It is possible, however, to provide the ADC with a more accurate external reference for improved readback accuracy.

Supplies can also be connected to the input pins purely for ADC readback, even though these pins may go above the expected supervisory range limits (but not above the absolute maximum ratings on these pins). For example, a 1.5 V supply connected to the VX1 pin can be correctly read out as an ADC code of approxi-mately 3/4 full scale, but it always sits above any supervisory limits that can be set on that pin. The maximum setting for the REFIN pin is 2.048 V.

SUPPLY SUPERVISION WITH THE ADC In addition to the readback capability, another level of supervi-sion is provided by the on-chip, 12-bit ADC. The ADM1064 has limit registers with which the user can program a maximum or minimum allowable threshold. Exceeding the threshold generates a warning that can either be read back from the status registers or input into the SE to determine what sequencing action the ADM1064 should take. Only one register is provided for each input channel. Therefore, either an undervoltage threshold or overvoltage threshold (but not both) can be set for a given channel. The ADC round-robin can be enabled via an SMBus write, or it can be programmed to turn on in any state in the SE program. For example, it can be set to start after a power-up sequence is complete, and all supplies are known to be within expected tolerance limits.

Note that a latency is built into this supervision, dictated by the conversion time of the ADC. With all 12 channels selected, the total time for the round-robin operation (averaging off) is approximately 6 ms (500 μs per channel selected). Supervision using the ADC, therefore, does not provide the same real-time response as the SFDs.

Data Sheet ADM1064

Rev. E | Page 23 of 31

APPLICATIONS DIAGRAM

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8

3.3V OUT

3.3V OUT

VH

PDO8

PDO9

SYSTEM RESETPDO7

SIGNAL VALIDPDO6

PWRGD

PDO2

PDO1

PDO5

PDO4

PDO3

EN OUT

DC-TO-DC1IN

3.3V OUT

3V OUT

5V OUT

12V OUT

EN OUT

DC-TO-DC2IN

2.5V OUT

EN OUT

DC-TO-DC3IN

EN OUT

LDOIN

1.8V OUT

0.9V OUT

1.2V OUT

5V OUT

12V IN

5V IN

3V IN

VP13V OUT VP2

3.3V OUT VP32.5V OUT VP41.8V OUT VX11.2V OUT VX20.9V OUT VX3

POWRONVX4

VX5

10µF

REFIN

10µF

VCCP

10µF

VDDCAP GND

PDO10

ADM1064

REFOUT

RESET

EN OUT

DC-TO-DC4IN

Figure 29. Applications Diagram

ADM1064 Data Sheet

Rev. E | Page 24 of 31

COMMUNICATING WITH THE ADM1064 CONFIGURATION DOWNLOAD AT POWER-UP The configuration of the ADM1064 (undervoltage/overvoltage thresholds, glitch filter timeouts, PDO configurations, and so on) is dictated by the contents of the RAM. The RAM comprises digital latches that are local to each of the functions on the device. The latches are double-buffered and have two identical latches, Latch A and Latch B. Therefore, when an update to a function occurs, the contents of Latch A are updated first, and then the contents of Latch B are updated with identical data. The advantages of this architecture are explained in detail in the Updating the Configuration section.

The two latches are volatile memory and lose their contents at power-down. Therefore, the configuration in the RAM must be restored at power-up by downloading the contents of the EEPROM (nonvolatile memory) to the local latches. This download occurs in steps, as follows:

1. With no power applied to the device, the PDOx pins are all high impedance.

2. When 1.2 V appears on any of the inputs connected to the VDD arbitrator (VH or VPx), the PDOx pins are all weakly pulled to GND with a 20 kΩ resistor.

3. When the supply rises above the undervoltage lockout of the device (UVLO is 2.5 V), the EEPROM starts to download to the RAM.

4. The EEPROM downloads its contents to all Latch As. 5. When the contents of the EEPROM are completely

downloaded to the Latch As, the device controller signals all Latch As to download to all Latch Bs simultaneously, completing the configuration download.

6. At 0.5 ms after the configuration download completes, the first state definition is downloaded from the EEPROM into the SE.

Note that any attempt to communicate with the device prior to the completion of the download causes the ADM1064 to issue a no acknowledge (NACK).

UPDATING THE CONFIGURATION After power-up, with all the configuration settings loaded from the EEPROM into the RAM registers, the user may need to alter the configuration of functions on the ADM1064, such as changing the undervoltage or overvoltage limit of an SFD, changing the fault output of an SFD, or adjusting the rise time delay of one of the PDOs.

The ADM1064 provides several options that allow the user to update the configuration over the SMBus interface. The following three options are controlled in the UPDCFG register:

Option 1

Update the configuration in real time. The user writes to the RAM across the SMBus, and the configuration is updated immediately.

Option 2

Update the Latch As without updating the Latch Bs. With this method, the configuration of the ADM1064 remains unchanged and continues to operate in the original setup until the instruction is given to update the Latch Bs.

Option 3

Change the EEPROM register contents without changing the RAM contents, and then download the revised EEPROM contents to the RAM registers. With this method, the configuration of the ADM1064 remains unchanged and continues to operate in the original setup until the instruction is given to update the RAM.

The instruction to download from the EEPROM in Option 3 is also a useful way to restore the original EEPROM contents if revisions to the configuration are unsatisfactory. For example, if the user needs to alter an overvoltage threshold, the RAM register can be updated, as described in Option 1. However, if the user is not satisfied with the change and wants to revert to the original programmed value, the device controller can issue a command to download the EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1064 to its original configuration.

The topology of the ADM1064 makes this type of operation possible. The local, volatile registers (RAM) are all double-buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves the double-buffered latches open at all times. If Bit 0 is set to 0 when a RAM write occurs across the SMBus, only the first side of the double-buffered latch is written to. The user must then write a 1 to Bit 1 of the UPDCFG register. This generates a pulse to update all the second latches at once. EEPROM writes occur in a similar way.

The final bit in this register can enable or disable EEPROM page erasure. If this bit is set high, the contents of an EEPROM page can all be set to 1. If this bit is set low, the contents of a page cannot be erased, even if the command code for page erasure is programmed across the SMBus. The bit map for the UPDCFG register is shown in the AN-698 Application Note. A flow diagram for download at power-up and subsequent configuration updates is shown in Figure 30.

Data Sheet ADM1064

Rev. E | Page 25 of 31

0463

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5

POWER-UP(VCC > 2.5V)

EEPROM

EEPROMLD

DATA

RAMLD

UPD

SMBus

DEVICECONTROLLER

LATCH A LATCH BFUNCTION

(OV THRESHOLDON VP1)

Figure 30. Configuration Update Flow Diagram

UPDATING THE SEQUENCING ENGINE Sequencing engine (SE) functions are not updated in the same way as regular configuration latches. The SE has its own dedicated 512-byte nonvolatile, electrically erasable, programmable, read-only memory (EEPROM) for storing state definitions, providing 63 individual states, each with a 64-bit word (one state is reserved). At power-up, the first state is loaded from the SE EEPROM into the engine itself. When the conditions of this state are met, the next state is loaded from the EEPROM into the engine, and so on. The loading of each new state takes approximately 10 μs.

To alter a state, the required changes must be made directly to the EEPROM. RAM for each state does not exist. The relevant alterations must be made to the 64-bit word, which is then uploaded directly to the EEPROM.

INTERNAL REGISTERS The ADM1064 contains a large number of data registers. The principal registers are the address pointer register and the configuration registers.

Address Pointer Register

The address pointer register contains the address that selects one of the other internal registers. When writing to the ADM1064, the first byte of data is always a register address that is written to the address pointer register.

Configuration Registers

The configuration registers provide control and configuration for various operating parameters of the ADM1064.

EEPROM The ADM1064 has two 512-byte cells of nonvolatile EEPROM from Register Address 0xF800 to Register Address 0xFBFF. The EEPROM is used for permanent storage of data that is not lost when the ADM1064 is powered down. One EEPROM cell contains the configuration data of the device; the other contains the state definitions for the SE. Although referred to as read-only memory, the EEPROM can be written to, as well as read from, using the serial bus in exactly the same way as the other registers.

The major differences between the EEPROM and other registers are as follows:

An EEPROM location must be blank before it can be written to. If it contains data, the data must first be erased.

Writing to the EEPROM is slower than writing to the RAM. Writing to the EEPROM should be restricted because it has

a limited write/cycle life of typically 10,000 write operations, due to the usual EEPROM wear-out mechanisms.

The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each. Page 0 to Page 6, starting at Address 0xF800, hold the configuration data for the applications on the ADM1064 (such as the SFDs and PDOs). These EEPROM addresses are the same as the RAM register addresses, prefixed by F8. Page 7 is reserved. Page 8 to Page 15 are for customer use.

Data can be downloaded from the EEPROM to the RAM in one of the following ways:

At power-up, when Page 0 to Page 6 are downloaded By setting Bit 0 of the UDOWNLD register (0xD8), which

performs a user download of Page 0 to Page 6

SERIAL BUS INTERFACE The ADM1064 is controlled via the serial system management bus (SMBus) and is connected to this bus as a slave device under the control of a master device. It takes approximately 1 ms after power-up for the ADM1064 to download from its EEPROM. Therefore, access to the ADM1064 is restricted until the download is complete.

Identifying the ADM1064 on the SMBus

The ADM1064 has a 7-bit serial bus slave address (see Table 10). The device is powered up with a default serial bus address. The five MSBs of the address are set to 01001; the two LSBs are determined by the logical states of Pin A1 and Pin A0. This allows the connection of four ADM1064 devices to one SMBus.

Table 10. Serial Bus Slave Address A1 Pin A0 Pin Hex Address 7-Bit Address1 Low Low 0x48 0100100x Low High 0x4A 0100101x High Low 0x4C 0100110x High High 0x4E 0100111x 1 x = Read/Write bit. The address is shown only as the first 7 MSBs.

ADM1064 Data Sheet

Rev. E | Page 26 of 31

The device also has several identification registers (read-only) that can be read across the SMBus. Table 11 lists these registers with their values and functions.

Table 11. Identification Register Values and Functions Name Address Value Function MANID 0xF4 0x41 Manufacturer ID for Analog

Devices REVID 0xF5 0x02 Silicon revision MARK1 0xF6 0x00 Software brand MARK2 0xF7 0x00 Software brand

General SMBus Timing

Figure 31, Figure 32, and Figure 33 are timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which are discussed in the Write Operations and Read Operations sections.

The general SMBus protocol operates as follows:

Step 1

The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data (SDA) line, while the serial clock line (SCL) remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and by holding it low during the high period of this clock pulse.

All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device.

Step 2

Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high could be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This command byte tells the slave device what to expect next.

It may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, sending a command to a slave device during a read operation is not possible. Before a read operation, it may be necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read.

Step 3

When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge (NACK). The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition.

SCL Held Low Timeout

If the bus master holds the SCL low for a time that is a multiple of approximately 30 ms, the ADM1064 bus interface may timeout. If this timeout happens, the in progress transaction is NACKed, and the transaction must be repeated. This behavior is only seen if the I2C bus master is interrupted midtransaction by a higher priority task that delays completion of the transaction.

False Start Detection

The data hold time specification defines the time that data must be valid on the SDA line, following an SCL falling edge. If there are multiple ADM1064 devices on the same bus, one of the ADM1064 devices may see the SCL/SDA transition due to an acknowledge (ACK) from a different device as a start condition because of internal timing skew, which for most transactions, this is not an issue. In a case where the data appearing on the bus after the false start is detected happens to match the address of another ADM1064 on the bus, that device may incorrectly ACK.

A bus master may see this ACK as another bus master talking on the bus, halt the bus transaction, and not produce any more clocks on the SCL. As a result, the ADM1064 device that incorrectly ACKed continues to hold down the SDA line low. To retry the halted bus transaction, the bus master performs a clock flush on the SCL by sending a series of up to 16 clock pulses. The clock flush forces the ADM1064 to release the SDA line.

Data Sheet ADM1064

Rev. E | Page 27 of 31

0463

3-03

6

1 9 91

1 9 91

START BYMASTER

ACK. BYSLAVE

ACK. BYSLAVE

ACK. BYSLAVE

ACK. BYSLAVE

FRAME 2COMMAND CODE

FRAME 1SLAVE ADDRESS

FRAME NDATA BYTE

FRAME 3DATA BYTE

SCL

SDA R/W

STOPBY

MASTER

SCL(CONTINUED)

SDA(CONTINUED)

D7A0A11010 0 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 31. General SMBus Write Timing Diagram

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7

1 9 91

1 9 91

START BYMASTER

ACK. BYSLAVE

ACK. BYMASTER

ACK. BYMASTER NO ACK.

FRAME 2DATA BYTE

FRAME 1SLAVE ADDRESS

FRAME NDATA BYTE

FRAME 3DATA BYTE

SCL

SDA R/W

STOPBY

MASTER

SCL(CONTINUED)

SDA(CONTINUED)

D7A0A11010 0 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 32. General SMBus Read Timing Diagram

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8

SCL

SDA

P S S P

tSU;STO

tHD;STA

tSU;STA

tSU;DATtHD;DAT

tHD;STA tHIGH

tBUF

tLOW

tR tF

Figure 33. Serial Bus Timing Diagram

ADM1064 Data Sheet

Rev. E | Page 28 of 31

SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1064 contains volatile registers (RAM) and nonvolatile registers (EEPROM). User RAM occupies Address 0x00 to Address 0xDF; the EEPROM occupies Address 0xF800 to Address 0xFBFF.

Data can be written to and read from both the RAM and the EEPROM as single data bytes. Data can be written only to unprogrammed EEPROM locations. To write new data to a programmed location, the location contents must first be erased. EEPROM erasure cannot be done at the byte level. The EEPROM is arranged as 32 pages of 32 bytes each, and an entire page must be erased.

Page erasure is enabled by setting Bit 2 in the UPDCFG register (Address 0x90) to 1. If this bit is not set, page erasure cannot occur, even if the command byte (0xFE) is programmed across the SMBus.

WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The following abbreviations are used in Figure 34 to Figure 42:

S = Start P = Stop R = Read W = Write A = Acknowledge A = No acknowledge

The ADM1064 uses the following SMBus write protocols.

Send Byte

In a send byte operation, the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the

write bit (low). 3. The addressed slave device asserts an acknowledge (ACK)

on SDA. 4. The master sends a command code. 5. The slave asserts an ACK on SDA. 6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADM1064, the send byte protocol is used for two purposes:

To write a register address to the RAM for a subsequent single byte read from the same address, or for a block read or a block write starting at that address, as shown in Figure 34.

0463

3-03

9

2 41 3 5 6

SLAVEADDRESS

RAMADDRESS

(0x00 TO 0xDF)S W A A P

Figure 34. Setting a RAM Address for Subsequent Read

To erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page(s) containing those locations must first be erased. EEPROM memory is erased by writing a command byte. The master sends a command code telling the slave device to erase the page. The ADM1064 command code for a page erasure is 0xFE (1111 1110). Note that for a page erasure to take place, the page address must be given in the previous write word transaction (see the Write Byte/Word section). In addition, Bit 2 in the UPDCFG register (Address 0x90) must be set to 1.

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0

2 41 3 5 6

SLAVEADDRESS

COMMANDBYTE(0xFE)

S W A A P

Figure 35. EEPROM Page Erasure

As soon as the ADM1064 receives the command byte, page erasure begins. The master device can send a stop command as soon as it sends the command byte. Page erasure takes approximately 20 ms. If the ADM1064 is accessed before erasure is complete, it responds with a no acknowledge (NACK).

Data Sheet ADM1064

Rev. E | Page 29 of 31

Write Byte/Word

In a write byte/word operation, the master device sends a command byte and one or two data bytes to the slave device, as follows:

1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the

write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code. 5. The slave asserts an ACK on SDA. 6. The master sends a data byte. 7. The slave asserts an ACK on SDA. 8. The master sends a data byte or asserts a stop condition. 9. The slave asserts an ACK on SDA. 10. The master asserts a stop condition on SDA to end the

transaction.

In the ADM1064, the write byte/word protocol is used for three purposes:

To write a single byte of data to the RAM. In this case, the command byte is RAM Address 0x00 to RAM Address 0xDF, and the only data byte is the actual data, as shown in Figure 36.

0463

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1SLAVEADDRESS

RAMADDRESS

(0x00 TO 0xDF)S W A DATAA PA

2 41 3 5 876

Figure 36. Single Byte Write to the RAM

To set up a 2-byte EEPROM address for a subsequent read, write, block read, block write, or page erase. In this case, the command byte is the high byte of EEPROM Address 0xF8 to EEPROM Address 0xFB. The only data byte is the low byte of the EEPROM address, as shown in Figure 37.

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2SLAVEADDRESS

EEPROMADDRESS

HIGH BYTE(0xF8 TO 0xFB)

S W A

EEPROMADDRESSLOW BYTE

(0x00 TO 0xFF)

A PA

2 41 3 5 876

Figure 37. Setting an EEPROM Address

Because a page consists of 32 bytes, only the three MSBs of the address low byte are important for page erasure. The lower five bits of the EEPROM address low byte specify the addresses within a page and are ignored during an erase operation.

To write a single byte of data to the EEPROM. In this case, the command byte is the high byte of EEPROM Address 0xF8 to EEPROM Address 0xFB. The first data byte is the low byte of the EEPROM address, and the second data byte is the actual data, as shown in Figure 38.

0463

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3SLAVEADDRESS

EEPROMADDRESS

HIGH BYTE(0xF8 TO 0xFB)

S W A

EEPROMADDRESSLOW BYTE

(0x00 TO 0xFF)

A PA

2 41 3 5 107

A

9

DATA

86

Figure 38. Single Byte Write to the EEPROM

Block Write

In a block write operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the ADM1064, a send byte opera-tion sets a RAM address, and a write byte/word operation sets an EEPROM address, as follows:

1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by

the write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code that tells the slave

device to expect a block write. The ADM1064 command code for a block write is 0xFC (1111 1100).

5. The slave asserts ACK on SDA. 6. The master sends a data byte that tells the slave device how

many data bytes are being sent. The SMBus specification allows a maximum of 32 data bytes in a block write.

7. The slave asserts an ACK on SDA. 8. The master sends N data bytes. 9. The slave asserts an ACK on SDA after each data byte. 10. The master asserts a stop condition on SDA to end the

transaction.

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4SLAVEADDRESSS W A

2

COMMAND 0xFC(BLOCK WRITE)

41 3

A

5

BYTECOUNT

6

A

7

A

9 10

A PADATA1

8

DATAN

DATA2

Figure 39. Block Write to the EEPROM or RAM

Unlike some EEPROM devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except when

There must be at least N locations from the start address to the highest EEPROM address (0xFBFF) to avoid writing to invalid addresses.

An address crosses a page boundary. In this case, both pages must be erased before programming.

Note that the ADM1064 features a clock extend function for writes to EEPROM. Programming an EEPROM byte takes approximately 250 μs, which limits the SMBus clock for repeated or block write operations. The ADM1064 pulls SCL low and extends the clock pulse when it cannot accept any more data.

ADM1064 Data Sheet

Rev. E | Page 30 of 31

READ OPERATIONS The ADM1064 uses the following SMBus read protocols.

Receive Byte

In a receive byte operation, the master device receives a single byte from a slave device, as follows:

1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the

read bit (high). 3. The addressed slave device asserts an ACK on SDA. 4. The master receives a data byte. 5. The master asserts a NACK on SDA. 6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADM1064, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation, as shown in Figure 40.

0463

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5

2 31 4 65

SLAVEADDRESSS R DATA PA A

Figure 40. Single Byte Read from the EEPROM or RAM

Block Read

In a block read operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the ADM1064, this is done by a send byte operation to set a RAM address, or a write byte/word operation to set an EEPROM address. The block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows:

1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the

write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code that tells the slave

device to expect a block read. The ADM1064 command code for a block read is 0xFD (1111 1101).

5. The slave asserts an ACK on SDA. 6. The master asserts a repeat start condition on SDA. 7. The master sends the 7-bit slave address followed by the

read bit (high). 8. The slave asserts an ACK on SDA. 9. The ADM1064 sends a byte-count data byte that tells the

master how many data bytes to expect. The ADM1064 always returns 32 data bytes (0x20), which is the maximum allowed by the SMBus Version 1.1 specification.

10. The master asserts an ACK on SDA. 11. The master receives 32 data bytes. 12. The master asserts an ACK on SDA after each data byte. 13. The master asserts a stop condition on SDA to end the

transaction.

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6

SLAVEADDRESSS W A

2

COMMAND 0xFD(BLOCK READ)

41 3

A

5

S

6

SLAVEADDRESS

7

BYTECOUNT

9 10 1211

AR A

8

DATA1

DATA32 A

13

P

A

Figure 41. Block Read from the EEPROM or RAM

Error Correction

The ADM1064 provides the option of issuing a packet error correction (PEC) byte after a write to the RAM, a write to the EEPROM, a block write to the RAM/EEPROM, or a block read from the RAM/ EEPROM. This option enables the user to verify that the data received by or sent from the ADM1064 is correct. The PEC byte is an optional byte sent after the last data byte has been written to or read from the ADM1064. The protocol is the same as a block read for Step 1 to Step 12 and then proceeds as follows:

13. The ADM1063 issues a PEC byte to the master. The master checks the PEC byte and issues another block read if the PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end of the read.

15. The master asserts a stop condition on SDA to end the transaction.

Note that the PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial

C(x) = x8 + x2 + x1 + 1

See the SMBus Version 1.1 specification for details.

An example of a block read with the optional PEC byte is shown in Figure 42.

0463

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7

SLAVEADDRESSS W A

2

COMMAND 0xFD(BLOCK READ)

41 3

A

5

S

6

SLAVEADDRESS

7

BYTECOUNT

9 10 1211

AR A

8

DATA1

DATA32 A

13

PEC

14

A

15

P

A

Figure 42. Block Read from the EEPROM or RAM with PEC

Data Sheet ADM1064

Rev. E | Page 31 of 31

OUTLINE DIMENSIONS

0.50BSC

BOTTOM VIEWTOP VIEW

PIN 1INDICATOR

EXPOSEDPAD

PIN 1INDICATOR

SEATINGPLANE

0.05 MAX0.02 NOM

0.20 REF

COPLANARITY0.08

0.300.250.18

6.106.00 SQ5.90

0.800.750.70

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

0.450.400.35

0.25 MIN

4.254.10 SQ3.95

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

40

1

1120

21

30

31

10

05-

06

-20

11-A

Figure 43. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad (CP-40-9)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-026ABC

0.50BSC

LEAD PITCH

0.270.220.17

9.00BSC SQ

7.00BSC SQ

1.20MAX

TOP VIEW(PINS DOWN)

1

1213

2524

363748

0.750.600.45

PIN 1

VIEW A

1.051.000.95

0.200.09

0.08 MAXCOPLANARITY

SEATINGPLANE

0° MIN

7°3.5°0°0.15

0.05

VIEW AROTATED 90° CCW

Figure 44. 48-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-48) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADM1064ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-9 ADM1064ASUZ −40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48 EVAL-ADM1064TQEBZ Evaluation Kit [TQFP Version] 1 Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04633-0-1/15(E)