swiss light source bpm system & upgrade plans/activities boris keil paul scherrer institut

Boris Keil, PSI DITANET BPM Workshop Jan. 18, 2012

Swiss Light Source BPM System &Upgrade Plans/Activities Boris Keil

Paul Scherrer Institut


Jan. 18, 2012DITANET BPM Workshop

2


Introduction

Present SLS BPM System

Upgrade Plans & Activities

Summary

Contents

3


Introduction: SLS

• 2000: 1st Beam.

• 2001: User Operation.

• 400mA top-up, 2.4GeV, 500MHz.

• Ring: L=288m, frev ~ 1MHz.

• 2011: Start with developments for new BPM system.

4


Introduction: SLS (Cont’d)

SLS Features Affecting BPM Requirements

• Global Fast orbit feedback (FOFB): → Any drift & noise of BPM electronics & pickups immediately modulated onto beam (if within FB bandwidth & if no X-ray BPM feedback).

• Top-up operation: I=400mA ± ~1% → beam-current dependence of BPM less critical.

• Filling pattern feedback (keeps charge in bunches 0...N const.) → filling pattern dependence of BPMs less critical.

• X-Ray BPM feedbacks (correction ~ Hz, move FOFB ref. orbit) → Position drift of RF BPMs less critical.

Accelerator design & features important for orbit stability, not only pure BPM system performance.

5


Introduction



Summary

Contents

6



History & Status

• Same “DBPM” electronics for booster & ring (buttons), linac & transfer lines (resonant striplines). Licensed to I-Tech (=PSI spin-off), predecessor of Libera electron. 1st beam: 2000.

• Digitally programmable bandwidth & data rate (MHz ... Hz), using DDC ASICs (Intersil HSP50214B). Standard setting (ring):

- tune BPM: 1MSPS / 0.5MHz BW- other BPMs: 4KSPS / 0.8kHz BW (FOFB)

• Annual failure rate: Dropped over the years, still at “bottom of bathtub” (year 2011: Highest SLS uptime ever ...). But: Want new system before this changes.

• Ring: 73BPMs. Booster: 54 BPMs (only few needed). No spare problem (yet). In-house maintenance.

7



8



RFFE

• Mix 4 500MHz button signal to 36MHz IF.• Free-running LO.• Pilot for initial calibration & test.

Digitizer/DDC (“QDR”)

• 12-Bit ADC, 28/32MSPS.• Four 1-channel DDC ASICs (Intersil HSP50214B).• VME interface (booster) + LVDS DSP interface (ring).

DSP Board

• 12 VME crates, 1 DSP board + 6 BPMs each.• DSPs receives DDC output (button amplitudes), calculate position etc., perform FOFB algorithm.

9



10


Present SLS BPM System: DDC

DDC Block Diagram• ASIC with 1 Channel (Intersil_HSP50214B)• Future SLS BPM Upgrade: Want same flexibility (full filter reprogramming during operation, no hard-coding of filter coefficients in FPGA firmware …)

11



DDC Block Diagram (Cont’d)

12



DDC filter response for

orbit feedback mode (4 KSPS

data rate)

13



DDC filter response for turn-by-turn

mode (1 MSPS data rate)

Future BPM upgrade:

Would like to have flat passband

14


Parameter Value for FOFB mode (4 KSPS)Original Spec Achieved

Dynamic range 1-500 mA 0.1-500 mABeam current dependence• Full range• Relative 1 to 5 range• Differential @ 400 mA (typ.)

< 100 μm< 5 μm-

< 100 μm (I > 42mA)<35 μm <0.1 μm/mA

Bunch pattern dependence (typ.) - 1.5 μm (FPFB off)Temperature drift (electronics) - 2 μm/°CResolution @ 0.8 kHz BW (-3 dB) < 1 μm 0.8 μm

- DBPM Resolution = 0.8 μm (0.8 kHz BW):

< σ(y)/10 @ mini-beta ID BPMs (5 nm, 1% coupling: σ = 10 μm = original spec.)

= σ(y)/5 @ mini-beta ID BPMs (5 nm, 0.13% coupling, σ = 4μm)

But: FOFB needs only ~ 100 Hz BW, and average beta functions @ BPMs are larger than @ mini-beta ID BPMs → DBPMs not above, but close to the usual σ /10 resolution requirement for 0.13% coupling.

Present SLS BPM System: Specs

12/2011: SLS achieved 1pm rad vert. emittance. σ~1.5μm in low-beta IDs

15


Present SLS BPM System: FOFB

- Angular stability: < 1 μrad (typ. < 10 μm at experiment) - Position stability: σ/10 at Insertion Devices (ID) - Suppression of orbit perturbations up to 100 Hz by factor of >5 - Fast compensation of orbit distortions due to ID gap changes

Fast Orbit Feedback (FOFB) Features:

Orbit Stability Requirements:

- 73 BPMs / 73 horizontal and 73 vertical correctors- Decentralized data processing (12 sectors)- Sampling and correction rate: 4 kHz- Point-to-point fiber optic ring for next-neighbour (not global) data exchange- Initialization by beam dynamics application- FOFB in user operation: since Nov. 2003

16


booster(3 Hz)

girdereigenmodes(20-35 Hz)

vacuum-pumps?(50 Hz)

0 dB point: ~95 Hz

0 dB point: ~95 Hz

0 dB point

dam

pin

gex

cit

atio

nfa

cto

r

horizontal vertical

- Suppression up to 95 Hz

- Bandwidth limited by electronics loop delay (technology: 1999)

Global Orbit Stability(1 – 150 Hz):

Horizontal: 0.41 μm · βx (FOFB on)(0.83 μm · βx (FOFB off))

Vertical: 0.29 μm · βy (FOFB on)(0.41 μm · βy (FOFB off))

Distortion suppression function

Spectral power density (1–150 Hz)

Present SLS BPM System: FOFB

17


Introduction



Summary

Contents

18


Motivation for New BPM/FOFB System

• Long-term maintenance, spare part availability.

• Performance (BPM resolution, drift, computing power for better FOFB algorithms, …).

• Want upgrade before reaching rising edge of bath-tub reliability curve.

Strategy:

• PSI develops cavity BPM system for European XFEL & SwissFEL.

• New SLS BPM system can use same platform.


19


Modular BPM/Diagnostics Platform Architecture

New SLS BPM Electronics (Simplified)

ADC0.1-5Gsps

FPGAVirtex-5

FXT500MHz

ControlSystem

RF Front-end MezzanineCarrierboard

Common housing, fan, power supply

E-XFEL / SwissFEL Cavity BPM Electronics (Simplified)

ControlSystem

3-5GHz

RF Front-end MezzanineCarrierboard

Common housing, fan, power supply

LO

ADC0.1-0.5Gsps

FPGAVirtex-5

FXT

IQ


20


SLS & FEL BPMs: Platform Strategy

• Modular design: RF front-end, ADC mezzanine, FPGA carrier board. Standardized interfaces.

• SLS BPMs can use same FPGA carrier board as E-XFEL & SwissFEL.

• ADC mezzanine: Requirements for SLS BPMs & FEL undulator BPMs also very similar (16-bit, >100MSPS, …). Synergies save development time.

• Need new SLS-specific RF front-end.

• SLS Goal: Improve noise (>3x, ideally <100nm @ 2kHz), drift (active temperature stabilization, ...), latency, ...


21


P1

P2

RFFE1

G PAC

4 x AD C

4 x AD C

X1

Clock

Y2

Y1

X2

X1

Clock

Y2

Y1

X2

RF-Clk

VME RFFE Board VME Carrier Board

P2

P1A B

CD

Ext. Pilot

RFFE2

Rev.-C lk

New SLS BPM Electronics: Prototype Block Schematics


22


Advantages of SLS BPM In-House Design

• Estimate: Less expensive (incl. man power) compared to commercial solution.

• Synergies SLS ↔ E-XFEL / SwissFEL: Less man power for development & long-term maintenance.

• No “black box”. All documentation (source codes, board schematics, …) available. Reduces time & costs to integrate systems, fix problems, add new features. Ensures high SLS availability / uptime.

• Avoids dependence on companies.


23


Design Status of New SLS BPM System:

• FPGA Carrier Board: Prototype successfully tested. SLS-specific FPGA firmware (digital filters, …) under development: DDC + position calculation working.

• ADC mezzanine: First beam tests use E-XFEL BPM mezzanine. Then: Make design optimized for SLS (different no. of ADCs, jitter optimization, …).

• RF front-end: Concept & schematics draft finished. PCB layout, production & first tests until mid 2012.

• EPICS: Access of FPGA board (via VME IOC) working (medm ADC data GUI, DDC config. GUI, …).


24


Generic PSI FPGA ADC Carrier Board (“GPAC”)

• Prototype tested, works fine.

• SLS: One carrier board for two BPMs (2 mezzanines with 4 ADCs each).

• Present prototype uses Virtex-5 FPGAs. (we are currently evaluating which type to use for the final version: Artix/Kintex-7?).

X-ray quality control (RAMs, connector)


25


E-XFEL Undulator & Button BPM ADC Mezzanines

Cavity BPMs: 6-channel, 16-bit, 160MSamples/s.

Button BPMs: 8-channel, 12-bit, 500MSamples/s.

Both types: Low-noise differential coax inputs.


26



Using Cavity BPM ADC for 1st SLS DDC Tests ...

ADC16HL

ADC2

ADC1

ADC0

ADC3

ADC4

ADC5

FB_U

500

Pol

.Con

nect

or

8

36

34

34

34

34

34

MGT's

5V 3.3V

CFG

PB_CTL

TRIG

ADC16BIT

Shield

CLOCKDistribution

FPGA

16

12

6

Z0=100

LVDS

LV

PE

CL

Digital ID

7

1 DEBUG

2

HCKCLKIN

AIN5

AIN4

AIN3

AIN2

AIN1

AIN0

Z0=100

LVDS8

3.3V

2

CLKIN1-1600MHz

12

Z0=100

1

3 x LED

2.5V

1.2V

POWER(Options)

1

1

CAL

5

PA

DC

17

LV

DS

2Switch

66

DA

Q S

yste

m24

BIT

6

JTAG 3

4

CLOCK160MHz

Config

1

3.3V

3.3V

2.5V3.3

V

5.0V3

.3V

3.3

V

4.6

V

3.3V

1

500pol. High Speed Connector (Carrier Board FPGA Interface)

Differential Inputs

On-Board Gain and Offset Calibration

Low Jitter Clock Distribution (80fs)

Six 16-bit 160Msps ADCs

27


New SLS BPM RF Front-End

• Active local multi-point temperature stabilization of drift-sensitive electronics components on the PCB, for lowest beam position drift. Present SLS BPMs: No temperature stabilization, but temperature sensor.

PCB layout of newprototype has started,

production & 1stSLS beam tests until mid

2012.


28


1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

1P2TRF Switch

BP 500MHz

BP 500MHz

BP 500MHz

BP 500MHz

-180°

0°

-180°

0°

-180°

0°

-180°

0°

A B

CD

ADC12/16Bit

Data

ClkMat

chin

gN

etw

ork

ADC12/16Bit

Data

ClkMat

chin

gN

etw

ork

ADC12/16Bit

Data

ClkMat

chin

gN

etw

ork

ADC12/16Bit

Data

ClkMat

chin

gN

etw

ork

Pas

sive

Clo

ckD

istr

ibut

ion

Net

wo

rk

Temperature Controlled

RF Clock 500MHz

PE43701

PE4251

PowerSplitte r In terna l P ilot

AD9958

-5dBm (400mA, MB)

BP 500MHz

BP 500MHz

BP 500MHz

BP 500MHz

DBPM3_RFFE DBPM3_ADC

-50dBm (0.1mA, SB)

G PAC

D D SC ore

C lo c k / Tim in gC on t rol

D A C

D A CD D SC ore

I-Inp ut

Q -In pu t

QuadraturModulator

90°

0°LO

1P2TRF SwitchExterna l P ilot

TRF370417

LMX2541-2060E

TP 10kHz

TP 10kHz

1..500MHz (Direct)10..125MHz (MUL)

<900MHz

-180°

0°

Revolution C lock 500/(450/480)MHz

Revolution C lock

P L L

LMX2541-2060E

0° 0°

<900MHz

NB7N017M

PE4251

BPF-B503+

RF Power < 0.5W

PE4251 BPF-C450+

RF Power < 0.5W

400-510MHz495-510MHz

100 - 500 MHz

P1/

P2

P1/

P2

Power / Con tro l Bus

10-650MHz

500p

ol. P

iggy

Ba

ck C

onn

ecto

r

SCP-4-1W1+

MatchingNetwork

MatchingNetwork

LRPS-2-1+5-500MHz

LRPS-2-1+

5-500MHz

ER

A-5

1SM

+

JS4PS-1+

1P2TRF Switch

1P2TRF Switch

P L L

New SLS BPM RF Front-End: Block Schematics


29



Lab Test Setup For DDC TestsPSI modular BPM electronics: Using

SwissFEL test injector 500MHz resonant

stripline RFFE & E-XFEL cavity BPM ADC for tests (DDC, ...), until dedicated new SLS ADC & RFFE is

ready.

30



New DDC: VHDL, Optimized for Speed & Space

31



GUI: Full DDC Reconfiguration During OperationButton: Update DDC setting on

GPAC (EPICS interface)User-adjustable parameters

(sample rate, decimation, BW, filter ripple, ...)

Overall DDC response

32



DDC Test Results (Stripline RFFE + Cavity ADC + GPAC)

X: 130nm RMS (2kHz BW, 10mm geometry

factor, 50ms)

Y: 91nm RMS (2kHz BW, 10mm geometry

factor, 50ms)

• Data presently stored in internal FPGA BRAM (50ms).• To do: Store data in larger ext. RAM, for long-term (hours, days, ...) tests & low-frequency noise / drift analysis.• Results promising: RFFE + ADC were not made for SLS but FEL. Expect better performance with dedicated new SLS RFFE & ADC.

500nm

500nm

50ms 50ms

33


Fast Orbit Feedback: DSP Boards

• Present System: FOFB algorithm performed on 12 VME DSP boards.

• New FOFB System: Algorithm can be implemented on single (few) DSP(s).

• Data transfer between BPMs & DSP board via multi-gigabit fiber optic links of the new BPM board. Also to be used for beam-based SwissFEL feedbacks.

Evaluation board for new FOFB DSP: 160 GFLOPS. 55x faster than all 24 DSPs of present FOFB system together. Easy connection to new

BPM system / GPAC via PCI Express (4 wires …).


34


Fast Orbit Feedback: Corrector Magnets

Present FOFB• DSP boards receive BPM data• Calculate corrections• Set currents of corrector power supplies (PS) via VMEbus & Hytech VME boards

New FOFB• Sets currents of corrector PS via long-range multi- gigabit fiber optic links: Faster correction/latency, decoupling of DSPs & PS (quantities, location), …• Required electronics: Prototype available (final version may use newer FPGA …).

Corrector power supplies: So far no good reason for upgrade.


35


Introduction



Summary & Outlook

Contents

36


• Long-term failure statistics: SLS BPM/FOFB upgrade not urgent. Still high reliability. Performance: No pressure from users, still happy with beam stability.

• Development of new BPM/FOFB system already started: Takes time, should be ready before reliability reaches rising edge of “bath tub curve” & spares run out of stock.

• Platform strategy: Maximize synergies with E-XFEL & SwissFEL, minimize overall costs, maximize performance & availability. Ensure efficient long-term maintenance by full in-house know-how of all system details.

Summary

37


PSI Team & Credits

Present SLS BPM Electronics (Design in 2000): Patrick Pollet (QDR)Thomas Schilcher (DSP)Volker SchlottRok UrsicEt al. (see e.g. DIPAC 2001, CT03)

New SLS BPM Electronics:Raphael Baldinger (GPAC HW)Robin Ditter (stripline RFFE)Waldemar Koprek (DDC / GPAC FW)Goran Marinkovic (GPAC FW / HW)Markus Roggli (ADC & RFFE schem./layout)Markus Stadler (RFFE)Daniel Treyer (RFFE)

And:Thanks also to support from other PSI/GFA groups.



Thank you for yourattention!

swiss light source bpm system & upgrade plans/activities boris keil paul scherrer institut

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