syen 3330 digital systemsjung h. kim 1 syen 3330 digital systems chapter 6 – part 1

SYEN 3330 Digital Systems Jung H. Kim 1

SYEN 3330 Digital Systems

Chapter 6 – Part 1

SYEN 3330 Digital Systems Chapter 6-1

Sequential Circuits

A Sequential circuitcontains:

Storage Elements: Latches Flip-Flops Binary registers

Combinatorial Logic: Implements a multiple-output

switching function Inputs, labeled Inputs, are signals from

the outside. Outputs, labeled Outputs are signals to

the outside. Other inputs, labeled State or Present

State, are signals from memoryelements.

The remaining outputs, labeled NextState are inputs to memory elements.

Combina-tionalLogic

Storage Elements

Inputs Outputs

StateNextState


Sequential Circuits

Combinatorial Logic: Next state function:

Next State = f(Inputs, State) Output function (Mealy):

Outputs = g(Inputs, State) Alternate output function (Moore):

Outputs = h(State) Type of output function heavily

influences the design

Combina-tionalLogic

Storage Elements

Inputs Outputs

StateNextState


Overview of Chapter 6

• Types of Sequential Circuits

• Storage Elements Latches Flip-Flops

• Sequential Circuit Analysis State Tables State Diagrams

• Sequential Circuit Design Specification Assignment of State Codes Implementation HDL Representation


Types of Sequential Circuits

• Depends on time at which inputs are observed by storage elements and state of storage elements change

• Synchronous Behavior defined from knowledge of its signals at discrete

instances of time Storage elements affected by inputs and can change state only in

relation to a timing signal (clock pulses from a clock)

• Asynchronous Behavior defined from knowledge of inputs at any instant of time

and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are

asynchronous! Nevertheless, the synchronous abstraction makes complex

designs tractable!


Discrete Event Simulation

In order to understand the time behavior of a SequentialCircuit we use DISCRETE EVENT SIMULATION.

Rules:

Gates are modeled by an ideal (instantaneous) device and afixed gate delay.

Any change in input conditions is evaluated to see if itcauses a change in output conditions.

Changes in output conditions are "Posted" after the fixedgate delay.

When the time for a posted output change occurs, the outputis changed along with any inputs connected to it.


Simulated NAND Gate

FA

BDELAY 5 ns.

F(Instaneous)

Example: A 2-Input NAND gate with a 5 ns. delay:

t = A B F(I) F Comment

-Inf. 1 1 0 0 A=B=1 for a long time

0 1 0 1 1 0 0 F(Instantaneous) changes to 1

5 ns. 0 1 1 1 0 F changes after a 5 ns. delay

8 ns. 1 0 1 1 0 1 F(Instantaneous) changes to 0

13 ns. 1 1 0 1 0 F changes after 5 more ns. to 1

Assume that A and B have been 1 for a long time.Then at time t=0, A changes to a 0 and back to 1 at t=8 ns.


Storing StateConsider the following circuit:

This is a simple 2-inputmultiplexer with thefollowing relation:

Y = A whenever S = 1

Y = B whenever S = 0

What would happen if we connect output signalY to input signal B?


Storing State (Continued)

Now the output Y: Is equal to A when S = 1 and Depends on the previous state of

Y whenever S = 0

The simple combinatorial circuit has now become asequential circuit because its output is a function of thetime sequence of input signals!

• The circuit becomes:


Storing State (Continued)Here is a tabular example of what we might expect as inputsignals change with time. Entries further down the tableoccur in later times:

A S Y Comment0 1 0 Y = A when S = 11 1 11 0 1 Now Y "remembers" A when S = 00 0 1 No change in Y1 0 1 "0 0 1 "0 1 0 Y = A when S = 10 0 0 Y "remembers" A1 0 0 Even when A changes0 0 0


Storing State (Continued)Consider aslightly differentcircuit:

We have introduced aninverter in the feedbackpath. The followingbehavior will result: A S Y Comment

0 1 0 Y = A when S = 1 1 1 1 1 0 1 Now Y "remembers" A 1 0 0 Not Y a bit later 1 0 1 Not, Not Y a bit later 1 0 0 INSTABILITY


Basic NAND S -R Latch By "Cross-Coupling" two

NAND gates, we arrive atthe following circuit:

Q

Q'

S (set)

R (reset) Which has the

following timesequence behavior:

R S Q Q' Comment1 1 ? ? We don't know1 0 1 0 "Set" Q to 11 1 1 0 Now Q "remembers" 10 1 0 1 "Reset" Q to 01 1 0 1 Now Q "remembers" 00 0 1 1 Both go high1 1 ? ? INSTABILITY


Simulating S -R Latch

t R S Q(I) Q Q'(I) Q' Comment-Inf. 1 1 1 1 0 0Assume Q = 1, delays are 5 ns.0 ns. 1 01 1 1 1 0 0Force input "R" low5 ns. 01 1 1 1 1 0Q' follows Q'(I) after 5 ns.5 ns. 01 1 01 1 1 Since Q' changed, Q(I) does

too.10 ns. 01 01 01 1 Q follows Q(I) after 5 ns.12 ns.1 01 0 01 1 R changes back to 1+Inf. 1 1 0 01 1 Stable -- no more changes

Q

Q'

S (set)

R (reset)

Note that Q or Q' changing means that inputs(feedback) change as well.

Note that after two gate delays, the input to thelower NAND gate from Q will be zero, so R canchange with no further effect.


Basic S - R LatchBy "Cross-Coupling" twoNOR gates, we arrive atthe following circuit:

Which has the followingtime sequence behavior:

R S Q Q' Comment0 0 ? ? We don't know0 1 1 0 "Set" Q to 10 0 1 0 Now Q "remembers" 11 0 0 1 "Reset" Q to 00 0 0 1 Now Q "remembers" 01 1 0 0 Both go low0 0 ? ? INSTABILITY

S (set)

R (reset)Q

Q'


Clocked S - R Latch

By adding two NANDgates to the basic S - RNAND Flip Flop wearrive at the followingcircuit:

S

R

Q

Q'

CP

This has a time sequence behavior similar to the Basic S -RLatch EXCEPT THAT:

S and R are now active high signals (i.e. -- a "1" signal on Ssets Q to 1) and

The S and R inputs are only observed when the line CP ishigh.

CP has the meaning "Clock" or "Clock Pulse".


Clocked S - R Latch (Continued)

Q(t) S R Q(t+1) Comment

0 0 0 0 No change

0 0 1 0 Clear Q

0 1 0 1 Set Q

0 1 1 ??? Indeterminate

1 0 0 1 No change

1 0 1 0 Clear Q

1 1 0 1 Set Q

1 1 1 ??? Indeterminate

S

R

Q

Q'

CP

The Clocked S-R Latch can be described by a table:

The table describes whathappens after the clock[at time (t+1)] based on:

current inputs (S,R) and current state Q(t).


Characteristic Equation for S - R Latch

We can describe the behavior of outputQ at time (t+1) (immediately after oneclock pulse) using a K-Map:

Q

S

R

0 1 23

4 5 67

X

X1 1

1

We can see that:

Q(t+1) = S + R'Q

given that (both are not high at once):

SR = 0

The Clocked S – R Latch has the symbol:

C

R

S

Q

Q'


D Latch

By adding an inverterto the S-R Latch, we getthe D Latch:

DQ

Q'

CP

Q D Q(t+1) Comment

0 0 0 No change

0 1 1 Set Q

1 0 0 Clear Q

1 1 1 Set Q

Note that there are no"Indeterminate" states!

The graphic symbol for aD Latch is:

C

D Q

Q'


J-K LatchUsing a cross-coupled NORlatch and some input ANDgating with “feedback”, weget the J-K Latch:

Q

Q

J

C

K

Q J K Q(t+1) Comment0 0 0 0 No change0 0 1 0 Clear Q0 1 0 1 Set Q0 1 1 1 Toggle Q1 0 0 1 No change1 0 1 0 Clear Q1 1 0 1 Set Q1 1 1 0 Toggle Q

Note that there are no"Indeterminate" states!

NOTE: The clock pulse "C"must be carefully timed,in fact, almostimpossibly so, to makethis work!


T Latch

Tying J and K together, weget the T Latch with thesame clock problem!

Q

Q'

T

C

Q T Q(t+1) Comment

0 0 0 No change

0 1 1 Toggle Q

1 0 1 No change

1 1 0 Toggle Q

Here the state changeswhenever the input is a "1"and holds when the input is"0".

The JK Latch equations oftenlead to some designsimplification. The T Flip-Flop is somewhat morelimited. You can alwaysconstruct T from JK!

syen 3330 digital systemsjung h. kim 1 syen 3330 digital systems chapter 6 – part 1

Documents

digital systems chapter

state slide

digital systemsjung

overview of chapter

storing state continued

d latch slide

basic s r latch slide

clocked s r latch slide