symmetric autozeroing floating-gate current mirror...

Symmetric Autozeroing Floating-Gate CurrentMirror, Differential Pair and TransconductanceAmplifier for Ultra Low-Voltage Applications

Yngvar Berg and Mehdi Azadmehr

Abstract—In this paper we explore the symmetric autozeroingultra low-voltage current mirror, differential pair and transcon-ductance amplifier and present some applications. The ultra-low transconductance amplifier has a current boost function andresembles switch-cap and auto-zero circuits. The current boosttechnique have been used to implement ultra-low voltage digitallogic. The simulated data presented is relevant for a 90nm TSMCCMOS process.

Index Terms—CMOS, Low-Voltage, Amplifier, Autozero, Dif-ferential, Floating-Gate.

I. INTRODUCTION

In this paper we look at the noise properties of ultra-lowvoltage CMOS transconductance amplifiers. It has always beena challenge to implement analog circuits in a modern digitalCMOS process, especially if the analog circuitry is includedin a system with clocked digital logic. Traditional amplifiershave been limited by a lower limit for supply voltage given by2Vt + 2Vsat which in practice limits the supply voltage closeto 1V. Another challenge in mixed signal design is the impactof noise in the supply voltage given by the switching of digitalgates. Autozeroing has been proposed as a method to reducethe effect of noise in analog circuits.

While the supply voltage applicable in deep sub-submicronwill continue to decrease and eventually fall below 1V thethreshold voltage will remain relative stable. The gate oxidethickness becomes only a few nanometers and the supplyvoltage has to be reduced in order to ensure device reliability.In order to maintain maximum dynamic range, a low voltageanalog circuit must be able to deal with signal voltagesthat extend from rail-to-rail. This requires traditional circuitsolutions to be replaced by new circuit design strategies.

Floating-Gate (FG) gates have been proposed for Ultra-Low-Voltage (ULV) [1]. However, in modern CMOS technolo-gies there are significant gate leakage which undermine non-volatile FG circuits. FG gates implemented in a modern CMOSprocess require frequent initialization to avoid significantleakage. There are several approaches to FG CMOS logic [2],[3], [4], [5]. The semi floating-gate technique exploited in thispaper have been used for digital circuits design [6], [7] andanalog design [8].

Manuscript received January 29, 2012.Yngvar Berg is with the Institute of MicroSystems Technology, Vestfold

University College, Horten, Norway.Mehdi Azadmehr is with the Institute of MicroSystems Technology, Vest-

fold University College, Horten, Norway

In section 2 the basic autozeroing ULV circuit is presented,followed by symmetric ULV transconductance amplifiers insection 3 followed by the conclusion in section 4.

II. ULTRA LOW-VOLTAGE CIRCUITS

Cinn

Out

φ

φ

In FG

Cinp

Outφ

φ

In FG

nMOS pMOS

recharge transistor

recharge transistor

Voffset+

Voffset-

Fig. 1. MOS and pMOS clocked semi-floating-gate (CSFG) transis-tors.

The clocked-semi-floating-gate (CSFG) transistors areshown in Figure 1. The recharge transistors are controlled byclock signals which will force the nMOS evaluate transistorgate terminal (FG) to VDD in the recharge mode, i.e. φ = 1,and the pMOS transistor gate terminal to gnd when recharg-ing. Any input transition will affect the evaluate transistorsgate voltage either by a positive or a negative charge. By pow-ering up the gate to source voltages in an initialization phasewe are able to reduce the power supply without decreasing theON current provided by the enhanced transistors. The aim is tomaintain a high current level combined with a very low supplyvoltage. The enhancement can be viewed as an active thresholdvoltage shift. The recharge transistors are controlled by clocksignals which will force the nMOS evaluate transistor gateterminal (FG) to VDD in the recharge mode, i.e. φ = 1, andthe pMOS transistor gate terminal to gnd when recharging.Any input transition will affect the evaluate transistors gatevoltage either by a positive or a negative charge.

For very low supply voltages the CSFG biasing will not havea significant impact on the current level, and hence neitherrelative ON nor OFF currents are large. For increasing supplyvoltages, up to VDD = Vt, the relative current increases.For VDD ≤ 0.65V t, assuming that kin ≤ 0.7, wherekinn/p = Cinn/p/Cfg and Cfg is the total capacitance seenby the floating gate, the gate to source voltage will neverreach the threshold voltage. In this case the transistor willoperate in subthreshold regime. The transistors may operate

INTERNATIONAL JOURNAL OF CIRCUITS, SYSTEMS AND SIGNAL PROCESSING

Issue 4, Volume 6, 2012 255

Vout

Cinn

Cinp

Rn

Rp

En

Ep

φ

φ

Vin

Inv 1

Inv 2

Voffset+

Voffset-

a) ULV inverter

FG

Cin

φ

In+

Cin

In-

Vn

Clock drivers

Voffset+ Voffset+

Vp

φ

Ip+ Ip-

V+ V-I+ I-

Voffset- Voffset-

Cinp

Cinn

φ

Cinp

φ

Voffset+

Voffset-

Ep

En

Rp

Rn

In2

Ip2

Cinn

φ

Cinp

φ

Voffset+

Voffset-

Ep

En

Rp

Rn

In1

Ip1

IoutIin

φ

φI to V

C1

C2

Vfg1

Vfg2

IoutIin

b) Symmetric ULV diff pair c) Symmetric ULV current mirror

Vin Vout

φ

V+

φ

V-

Vn

VpI+ I-

Fig. 2. a) ULV inverter, b) symmetric ULV differential pair and c) symmetric ULV current mirror.

−3 −2 −1 0 1 2 3 4−3

−2

−1

0

1

2

3

4

Input current [A]

x 10 -7

x 10 -7

curr

ent [

A]

Fig. 3. The input and output currents of a symmetric current mirror.

in strong inversion if the supply voltage is close to or abovethe threshold voltage of the transistors. Furthermore, dummyrecharge transistors may be included to reduce noise inducedby the clock signal driving the recharge transistor.

The output currents as function of the input currents ofthe symmetric current mirror[9] are shown in Fig. 3. The bi-directionality of the symmetric current is evident and showsa reasonable linear characteristics and accuracy for a sineinput voltage signal producing the input current. The currentheadroom is −300nA to 300nA and the supply voltage is250mV .

The output current of the symmetric ULV differentialpair[10] is shown in Fig. 4, where the supply voltage is300mV and the offset voltages are 350mV and −50mV ,V− is swept from 0mV to 300mV and V+ is swept from0V to 300mV , and Wbias = 0.5μm to Wbias = 50μm. Inthis case we have used a clock signal of 100MHz and aninput signal of 200MHz. As expected the tanh shape of theoutput current of the differential pair is less evident whenthe bias transistor including in the clock driver inverters isincreased. The degradation of the power supply Vn and Vp

−0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3−5

−4

−3

−2

−1

0

1

2

3

4

5x 10

−6

ΔV+ - ΔV- [V]

ΔI o

ut [A

]

Wbias = 0.5μ

Wbias = 1.0μ

Wbias = 3.0μ

Wbias = 50.0μ

Fig. 4. The output currents of the symmetric ULV diff pair. VDD =300mV .

is not significant when the width of the bias transistor arevery large compared to the minimum sized transistors usedin the differential pair. For bias transistor widths exceeding3μm the output current is more linear or even slightly sinhshaped when the input capacitors are increased. In that case thedifferential pair will act as two binary inverters which providea sinh shaped output current.

A. Autozeroing ULV Gates

A ULV gate including clock drivers is shown in Figure 2.The clock drivers located close to the source/drain terminals ofthe evaluate transistors may be used to provide current sources.The inverters labeled Inv1 may be used as a bias transistor ina nMOS pseudo differential pair. The effective voltage of theevaluating transistors will be determined by the the supplyvoltage and the capacitive division associated with the inputcapacitances.

Both digital and analog ULV circuits can be designed usingautozeroing ULV inverters. The clock frequency applied must



be high enough to avoid significant charge leakage duringthe evaluation phase. The upper limit for the clock frequencydepends on the application and input signal frequency. Whenthe gates, i.e. all gates simultaneously, are recharged, henceoutput precharged to VDD/2, the precise output prechargevoltage of each gate are adapted to noise relevant for thegate. The precharge voltage is defined by the offset voltagesVpre = (Voffset+ + Voffset−) /2 due to a reverse biasinggate and simple voltage division. If the evaluate transistorare matched, i.e. Voffset− = VDD − Voffset+, the prechargevoltage can be expressed as Vpre ≈ VDD/2. Note that theevaluate transistors are not required to be matched accurately,we may adjust the precharge level by using the offset voltages.Assuming that Voffset+ = VDD and Voffset− = Vss = 0Vwe can estimate the effect of power supply noise on theprecharge voltage and accuracy of the autozeroing gate. Bymodelling the power supply noise as V

′DD = VDD + ΔV1

and V′ss = 0V + ΔV2 we can express the precharge voltage

as Vpre =(V

′DD + V

′ss

)/2 = (VDD + ΔV1 − ΔV2) /2. In

addition the nMOS and pMOS evaluate transistors are biasedor recharged with the power supply noise ΔV1 and ΔV2

respectively. When the gate enters the evaluation phase thegate are biased as an inverter and the power supply noise isevident for the evaluate transistors and the effective gate sourcevoltage of the evaluate transistors, assuming that the prechargevoltage is stable, can be expressed as

VDD + ΔV1 − ΔV2 nMOS

− (−ΔV2 + VDD + ΔV1) pMOS

= − (VDD + ΔV1 − ΔV2) , (1)

and the evaluate transistors remain matched after the autoze-roing is performed. All ULV gates respond only to AC signalsand blocks the DC level of input signals. This means that theprecharge level of inputs and outputs are not important forthe circuit’s functionality and accuracy. This feature makesit easier to use ULV circuits together with other subsystemswith different supply voltages and you can use external inputsignals with any DC level.

The switching of power supply when entering the evaluatemode may affect the accuracy of the ULV gate if there is an in-herent mismatch associated with the avaluate transistors. Thismismatch is not affected by power supply noise or other formsof circuit noise. Transistor mismatches, however may affectthe operation of the ULV gates. Ideally the precharge voltageshould VDD/2, or (VDD + ΔV1 − ΔV2) /2 in the presence ofpower supply noise. Evaluate transistor mismatch will affectthe out precharge directly through the voltage diviasion inrecharge mode. By modelling the mismatch as a transistorthreshold voltage shift of the nMOS evaluate transistor, i.e.Vpre = Vtn = Vtnnominal + ΔV3, the precharge voltage willbe Vpre = (VDD + ΔV1 − ΔV2 + ΔV3) /2. When the circuitenters the evaluate mode the output voltage of the gate willbe pulled towards one of the rails depending on the sign ofΔV3. If ΔV3 < 0 the nMOS is weak and the ouput will bepulled towards Vss and the AC effect of parasitic capacitance

seen from the output and to the semi floating-gates Csg (andeventually Cdg) will increase the effective threshold voltageof the nMOS evaluate transistor and reduce the effectivethreshold voltage of the pMOS evaluate transistors assocoatedwith the gate. Hence, the autozeriong will reduce the affect oftransistor mismatces locally. The prceding gate may, howeveralso be affected by the transisor mismatches of a gate. If theprecharge level of a specific gate is lower than VDD/2 dueto a strong nMOS evaluate transistor the precharge level ofa following circuit will be higher than VDD/2 and so on. Achain of gates will perform a global common autozero, ie.ewith all inherent transistor mismatches, with local autozeroand slighly different precharge voltages.

III. SYMMETRIC ULV TRANSCONDUCTANCE AMPLIFIER

C2

C1

φ

V+

C1

φ

Vn

Vp

+

-

V+

C1

Vo

φ

Cf1

φ

Vo

V-

V-

C1

FG

φ

In+ In-

Vn

Clock drivers

Voffset+ Voffset+

Vp

φ

Ip+ Ip-

V+ V-

I+

Voffset- Voffset-

φ

φ

φ

φ

φ

φ

Voffset+

Voffset+

Voffset-

Voffset-

Iout

a) Transistor level

b) Inverter symbol level

c) Amplifier symbol level

1

2

3 4

5

6

Vo

current mirror

current mirror

Va

Va

I+

Iout

- I+ I-

Iout

Cf1

Cf1

C2

C2

C1C1

C1 C1

Fig. 5. ULV transconductance amplifier.

The ULV transconductance amplifier is shown in Figure 5.Transistor level shown in Figure 5 a) consists of a bidirectionalpseudo differential pair and a bidirectional cirrent mirror. Wemay use simplified ULV inverter symbols for the amplifieras shown in Figure 5 b) where the clock drivers provind



the tail current for the pseudo differential pairs are labeled1 and 2 and the inverters labeled 3 and 4 are the differentialinput stage of the bidirectional differential pair. The inverterslabeled 5 and 6 provide for the current mirror function. Theamplifier level symbol is shown in Figure 5 c). Inverter 5 andthe local feedback capacitor Cf1 converts the output currentI+ of inverter 3 to a voltage Va = VDD − V+ which yieldsan output current of the current mirror, i.e. inverter 6, equalto −I+.

A significant feature of the symmetrical circuits resultsin increased transconductance. Basically, after recharge thecurrents in+ and ip+ and in and ip, will be the same. Anychange in the differential input ΔVin = ΔV+ − ΔV− willproduce a change in all currents so that

ΔIn+ = −ΔIn−= −ΔIp+

= ΔIp−I+ = ΔIp+ − ΔIn+

I− = ΔIp− − ΔIn−I+ = −I−,

and the transconductance of the symmetric pseudo-differential pair is thus the sum of the transconductance ofeach of the differential pair.

The autozeroing of the ULV gates is performed on theinverter level shown in Figure 5 c) where inverters 5 and 6 aredirectly connected to virtual power supply provided by clockdrivers.

Inverters 3 and 4 however perform autozeroing when con-nected to virtual power Vp = V ′

DD and Vn = V ′ss. The floating

gates are recharged to VDD, and V ′ss in the recharge phase

and when entering the evaluate phase the effective gate tosource voltages of the bias transistors are equal to VDD −Vss′

and −V ′DD for the nMOS and pMOS pseudo differential pair

respectively. Furthermore the evaluate transistors of inverters3 and 4 which form the symmetric differential pair will berecharged to V ′

DD−V ′n and V ′

p−V ′ss. The condition In+ = In−

and Ip+ = Ip− still holds, In+ = Ip+ and In− = Ip− must besatisfied. Assume a positive ΔV1, i.e. V ′

DD = VDD +ΔV1, thenMOS evaluate transistor will be recharged to provide morecurrent than the pMOS counterparts. In the evaluate modethe increased power supply will increase the current level ofthe pMOS evaluate transistor and the increased current of thenMOS evaluate tyransistors will be matched. Furthermore, thecurrent level will match the current level of the symmetriccurrent mirrors as well. In fact, all symmetric ULV gates willbe adjusted to the specific power supply available when thecircuits enters the recharge state. The autozeroing or rechargefrequency may be choosen i a wide range to avoid supply noiseand noise imposed by leakage. Note, that the autozeroing isperformed at all nodes driven including the internal node V a

in the amplifier shown in Figure 5.The ULV gates are noise tolerant due to two major aspects

1) Symmetry. All ULV gates, both analog and digital,are symmetric. The symmetry allows any circuit to beconnected to any other circuit without considering thedc level.

2) Autozeroing. All ULV gates, both analog and digital,perform autoaeroing at a high rate to reduce impact ofnoise.

− 0.4 −0.3 − 0.2 − 0.1 0 0.1 0.2 0.3 0.4−3

−2

−1

0

1

2

3x 10 -6

ΔV+ - ΔV- [V]

ΔIou

t [A

]ΔV- = -ΔV+

ΔV- = 0

Fig. 6. The output currents of the symmetric ULV transconductanceamplifier. VDD = 300mV . The output current is not determined bythe dc level of the inputs.

Simulated response of the symmetric transconductance am-plifier is shown in Figure 6 where the clock signal frequencyis 100MHz. We applied an input signal to the positive inputV+, i.e 200MHz sine and a peak to peak amplitude equal to200mV and a dc input to V−.

The response of the ULV amplifer to a differential sineinput and a varying supply voltage is shown in Figure 7. Thesupply voltage used in the simulation is a sine varying from300mV to 500mV . The supply voltage is used to rechargethe evaluate transistors directly in the recharge mode andto power the amplifier in the evaluate mode. The aurozerolevel changes with the supply voltage and the response is notaffected significantly by the the supply voltage or autozerolevel. The autozero level is always equal to VDD/2. Thedifferential sine input, V+ - V−, has an amplitude equal to20mV and a dc voltage equal to 0V . This is not natural in anautozero to half the VDD system, but is used in this case toshow that the dc level is not significant when the inputs areapplied to capacitors.

A. ULV Voltage Integrator and Differentiator

By using the ULV amplifier in Figure 5 as a voltage followerwe obtain the transfer function ΔVout = ΔV+. The circuitfollows any change in the input signal when operated in theevaluation mode. By adding another amplifier with oppositeclock signals and connect the inputs and outputs we obtain acontinuous time voltage follower. The current running in therecharge mode is not significant to the overall performance ofthe circuit. In Figure 8 a ULV differentiator is shown.



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10−7

−0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Time [s]

[V]

V+ V-

φ

Vnout

out

VDD

Autozero

Evaluate

V-V

out

Autozt

EE

D

uateate

Fig. 7. The response of the ULV amplifer to a differential sine input and a varying supply voltage.

C2

φ

V+

C1

φ

Vn

Vp

+

-

V+

C1

φ

C1

φ

Va C2

φ

C1

φ

Vn

Vp

C1

Vo

+

-

C1

Vo

C1

φ

φ

C1

Fig. 8. ULV differentiator.

φ

φVin

Cinn

Cinp

φ

φ

Rn

Rp

En

Ep

Cinn

Cinp

Vout

Fig. 9. The analog inverter.

B. Alternative symmetric transconductance amplifier

The single input analog inverter is shown in Fig. 9. Theideal response of the analog inverter may be expressed asΔVout = −ΔVin. The gain is dependent on the transcon-

φ

φ

A

Cinn

Cinp

φ

φ

Rn

Rp

En

Ep

Cinn

Cinp

VoutB In

Ip

Fig. 10. The double input analog inverter.

ductance to the output conductance ratio gm/go of the circuitin evaluation mode. The gain is thus dependent on boththe inherent transconductance and output conductance of theevaluate transistors and the capacitor ratio Cinn/p/Cfn/p.

The double input analog inverter is shown in Fig. 10. Thecircuit combines two inputs and provides an output defined by

ΔVout = G (ΔA + ΔB) , (2)

where G is the gain of the circuit. The gain is dependenton the transconductance and output conductance ratio of theevaluate transistors. Idealy the gain should be close to G =− 1

2 in order to use the voltage headrom. If the inputs andoutputs are precharged to VDD/2 during the precharge phase,we secure that the output voltage is defined by equation (1).If we apply continuous input signals we may reduce the gainof the inverter, i.e. |G| ≤ 1

4 to be able to process input signalswith a peak to peak amplitude equal to VDD .



φ

φ

Cinn

Cinp

φ

φ

Rn

Rp

En

Ep

Cfn1

Cfp1

φ

φV-

Cinn2

Cinp2

φ

φ

Rn

Rp

En

Ep

Cinn

Cinp

XV+ In

Ip

φ

φ

Cinn

Cinp

φ

φ

Rn

Rp

En

Ep

VoutY

Cfn2

Cfp2

φ

φ V+

φ

φ

φ

φV-

VoutXY

a) Differential ULV transconductance amplifer

b) Simplifed symbolic representation

Voffset+

Voffset+

Voffset+

Voffset-

Voffset-

Voffset-

Cinn

Cinp

Cfn1

Cfp1

V-

Cinn2

Cinp2

Cinn

Cinp

XV+

Cinn

Cinp

VoutY

Cfn2

Cfp2

c) Evaluation mode

Fig. 11. The ULV transconductance amplifier. a) transistor schemat-ics, b) simplified representation and c) evaluation mode.

The ULV gates presented perform an auto zeroing ofeach gate in each recharge phase. The output of each gateis determined by the mismatches inherent in each gate. Tedc level of the gate output may vary due to the inherentmismatches of the evaluate transistors feeding the output. Theresponse of the gates are determined by voltage changes ofgates providing the input signals and not the dc level of theinputs. There are no need for any dc-dc conversion due to therecharge phase forcing each gate output close to VDD/2.

The analog inverter and a double input binary inverter canbe used to design a simple ULV transconductance amplifier[?]. The pass-band ULV transconductance amplifier is shownin Fig. 11. The recharge transistors are connected to offsetvoltages which can be used to tune the frequency responseof the amplifier. If we increase the offsets, i.e. Voffset+ >VDD and Voffset− < 0V , the amplifier can process higherfrequency input signals. The most practical offset voltages areVDD and gnd(0V ). Other offset voltages can be be applied ifexternal voltages or internally generated voltages are provided.

The response of the analog inverter and double input analoginverter to a sine signal with an amplitude equal to 75mVapplied at input V− and a DC signal(125mV) applied at inputV+ is shown in Fig. 12. Although the analog inverter providingthe ΔY = −ΔV− has a gain less than |1| the signal can becombined with the input V+ if the input capacitor connecting

−0.08 −0.06 −0.04 −0.02 0 0.02 0.04 0.06 0.08−0.06

−0.04

−0.02

0

0.02

0.04

0.06

0.08

Y

X

ΔV- - ΔV+ [ΔV]

[ΔV]

G di = 1G si = -1

Fig. 12. The response of the analog inverter and double input analoginverter to a input sine signal with a precharge level equal to VDD/2(125mV), i.e. VDD = 250mV . Gsi and Gdi are the ideal gain of thesingle input and double input analog inverters respectively.

−1.5

−1

−0.5

0

.5

1

1.5x 10-6

−0.08 −0.06 −0.04 −0.02 0 0.02 0.04 0.06 0.08

ΔV+ - ΔV- [ΔV]

Iout

[A]

Fig. 13. Output current of the ULV transconductance amplifier.

Y to the double input analog inverter is increased compared tothe capacitors connected to V+. Furthermore the overall gainof the double input inverter is not critical. The gain seen fromeach input, i.e. V− and V+, should be equal in order to obtaina linear response of the amplifier. The feedback capacitors ofthe double input analog inverter is reduced to increase theoverall gain of the amplifier, hence the gain is |G| ≈ 2/3.

The output current of the ULV transconductance amplifieris shown in Fig. 13. The supply voltage is 250mV and theoffset voltages are 350mV and -100mV.

As mentioned the frequency response is dependent on theoffset voltages applied. The transconductance amplifier wassimulated with a sine input signal applied at the V− terminaland a dc voltage applied at V+ terminal. The supply voltageprovided through the clock signals is equal to 250mV. Thegain, ΔVout/ (ΔV+ − ΔV−) are shown. The data presentedare obtained based on several transient simulations.

The frequency response of the ULV transconductance am-



105

106

107

108

109−60

−50

−40

−30

−20

−10

0

10

20

30

Frequency [Hz]

Gai

n [d

B

Fig. 14. The frequency response of the ULV transconductanceamplifier with offset voltages equal to 250mV and 0V.

−150

−100

−50

0

50

100

150

200

250

300

350

105

106

107

108

109

Frequency [Hz]

Phas

e [D

eg]

Fig. 15. The phase of the ULV transconductance amplifier with offsetvoltages equal to 250mV and 0V.

plifier with offset voltages equal to 250mV and 0V is shownin Fig. 14 and the phase is shown in Fig. 15. The passband is1.8MHz to 60MHz and the gain is close to 30dB.

The frequency response of the ULV transconductance am-plifier with offset voltages equal to 350mV and -100mV isshown in Fig. 16. The gain has been reduced compared to thefrequency response shown in Fig. 14 due to a higher currentlevel and thus reduced relative transconductance. The gain isapproximately 10dB and the cut off frequency is 300MHz, i.ethe passband is 18MHz to 300MHz.

IV. CONCLUSION

The amplifier allows rail to rail signals an no need for dc-dcconversion is required. The ULV amplifier is not directly con-nected to the power supply and the response of the amplifieris not significantly affected by varying supply voltage. Thetransconductance amplifier may operate at a supply voltageequal to the threshold voltage of the nMOS transistor in a90nm CMOS process.

−100

−80

−60

−40

−20

0

20

105

106

107

108

109

Frequency [Hz]

Gai

n [d

B]

Fig. 16. The frequency response of the ULV transconductanceamplifier with offset voltages equal to 350mV and -100mV.

REFERENCES

[1] Y. Berg, D. T. Wisland and T. S. Lande: “Ultra Low-Voltage/Low-Power Digital Floating-Gate Circuits”, IEEE Transactions on Circuitsand Systems, vol. 46, No. 7, pp. 930–936,july 1999.

[2] K. Kotani, T. Shibata, M. Imai and T. Ohmi. “Clocked-Neuron-MOSLogic Circuits Employing Auto-Threshold-Adjustment”, In IEEE Inter-national Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.

[3] R. Lashevsky, K. Takaara and M. Souma “Neuron MOSFET as a Way toDesign a Threshold Gates with the Threshold and Input Weights Alterablein Real Time”, IEEE TT13.11-1.4, 1998, pp. 263–266.

[4] T. Shibata and T. Ohmi. “ A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations”, In IEEE Transactionson Electron Devices, vol 39, 1992.

[5] M. Azadmehr and Y. Berg. “Current-starved pseudo-floating gate ampli-fier”, WSEAS Transactions on Circuits and Systems, Volume 7 Issue 4,April 2008

[6] Y. Berg and O. Mirmotahari: ”Novel Static Differential Ultra Low-Voltageand High Speed Domino CMOS Logic”, Proceedings of the 10th WSEASInternational Conference on circuits, systems, control & signal processing(CSECS’11). Montreux, December 29-31, 2011.ISBN: 978-1-61804-062-6. s. 138-142.

[7] Y. Berg: ”Differential Static Ultra Low-Voltage CMOS Flip-Flop for HighSpeed Applications”, Proceedings of the 10th WSEAS International Con-ference on on circuits, systems, control & signal processing (CSECS’11).Montreux, December 29-31, 2011.ISBN: 978-1-61804-062-6. s. 134-137.

[8] Y. Berg and M. Azadmehr: ”Symmetric Autozeroing Floating-GateTransconductance Amplifier for Ultra Low-Voltage Applications”, Pro-ceedings of the 10th WSEAS International Conference on on circuits,systems, control & signal processing (CSECS’11). Montreux, December29-31, 2011.ISBN: 978-1-61804-062-6.

[9] Y. Berg and O. Mirmotahari: “Clocked Semi-Floating-Gate Ultra Low-Voltage Symmetric and Bidirectional Current Mirror”, in Proc. IEEESymposium on Design and Diagnostic of Electronic Systems (DDECS2009), Liberec, Czech Republic, April 2009.

[10] Y. Berg and O. Mirmotahari: “Clocked Semi-Floating-Gate PseudoDifferential Pair for Low-Voltage Analog Design”, In Proc. EuropeanConference on Circuit Theory and Design (ECCTD’2009), Antalya,Turkey, August 2009.

Yngvar Berg received the M.S. and Ph.D. degrees in Microelectronics fromthe Dept. of Informatics, University of Oslo in 1987 and 1992 respectively.He is currently working as a professor with the same department. Hisresearch activity is mainly focused on low-voltage/low-power digital andanalog floating-gate VLSI design with more than 170 published papers.



Mehdi Azadmehr received his mater and Ph.D. degree in Nanoelectronicsfrom the University of Oslo, Norway, in 2009. His Ph.D. project was fundedby Vesfold University College, Horten, Norway. The Ph.D. work aimed atdesigning bi-directional circuit for use as interface for resonating sensors. Hethen worked as assistant professor in 2 years at Vesfold University College andis now employed as associate professor at the same place. Main research aresare Organic electronics and analog electronic design with focus on interfacecircuits.



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