synchronization over ethernet - indico · synchronization over ethernet ... the related r&d...

Synchronization over Ethernet

Standard for a Precision Clock Synchronization P t l di t IEEE 1588Protocol according to IEEE 1588

Synchronous Ethernet according to ITU-T G 8261Synchronous Ethernet according to ITU-T G.8261

Prof. Hans Weibel, Zurich University of Applied Sciences

© 2003-2008 ZHAW

, y [email protected]

Who is ZHAW – Zurich University of Applied Sciences?

The School of Engineering is a department of the Zurich University of Applied Sciences (ZHAW)y pp ( )

ZHAW‘s Institute of Embedded Systems has a strong commitment to industrial communications in general and to Ethernet in particular, e.g.

Real-time Ethernet (Ethernet Powerling, ProfiNet, etc.)Synchronization (IEEE 1588)y ( )High-availability Ethernet add-ons (MRP, PRP, etc.)

The related R&D activities and services includeHardware assistance and off-load (IP)Protocol stacksSupport

© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 2

SupportEngineering and consultancy

Preliminary remark

only Ethernet solutions are taken into account in this presentation (according to workshop planning)p ( g p p g)

this requires some compromises to be accepted

the big advantage to be exploited is that the same infrastructure can be used for both datainfrastructure can be used for both data transmission and synchronization


The Standard IEEE 1588


The Standard IEEE 1588PTP Message Exchange

Master Clock Slave Clock

UDP

PTP

UDPDelay and

Delay and Ji

PTP

optionalIP

MACPhy

IP

MAC

Phy

JitterProtocol

Stack

JitterProtocolStackMII MII

optional

Phy Phy

Network

Delay and JitterPTP Precision Time Protocol (Application Layer)UDP User Datagram Protocol (Transport Layer)IP Internet Protocol (Network Layer)


Network( y )

MAC Media Access ControlPhy Physical Layer

The Standard IEEE 1588Determination of Phase Change Rate (Drift) – one step

Master Clock Slave Clock40

4238

t0k

42

44

46

40

42

44

t1k

48

50

52

46

48

50Δ0

54

56

58

50

52

54t0k+1 Δ1

Δ0 = t0k+1 - t0

k

Δ1 = t1k+1 - t1

k58

60

62

64

56

58

60

t1k+1

Drift = Δ 1 - Δ 0Δ 1


6462

1

The Standard IEEE 1588Determination of Phase Change Rate (Drift) – two step


4238

t0k

42

44

46

40

42

44

t1k

48

50

52

46

48

50Δ0

54

56

58

50

52

54t0k+1

Δ0 = t0k+1 - t0

k

Δ1 = t1k+1 - t1

kΔ1

58

60

62

64

56

58

60

t1k+1

Drift = Δ 1 - Δ 0Δ 1


6462

1

The Standard IEEE 1588Determination of Delay and Offset

O = Offset = ClocksSlave – ClocksMaster


4238

t0

Slave Master

d l t t t t

O

42

44

46

40

42

44t0 measured values t0, t1, t2, t3

A = t1-t0 = D+Ot1 = t0+D+O

A D = Delay48

50

52

46

48

50

t2BB = t3-t2 = D-O

Delay D = A + B

54

56

58

50

52

54

t3

Delay D

Offset O =

2A - B

2

58

60

62

64

56

58

60


t3 = t2-O+D64

62

The Standard IEEE 1588Boundary Clock copes with the Network‘s Delay Fluctuations

Switch with Boundary ClockMaster Clock Slave Clock

PTP PTPPTP

Slave

PTP

Master

UDP

IP

MAC

UDP

IP

MACMAC MAC

UDP

IP

UDP

IP

MAC MAC

Ph

MAC MAC

Phy PhyPhy Phy


Switching Function

The Standard IEEE 1588Topology and „Best Master Clock“

MOrdinary Clock, Grandmaster: clock selected as best Master“ (selection based

S

selected as „best Master (selection basedon comparison of clock descriptors)

MS

M MBoundary Clock, e.g. Ethernet switch

S: Port in Sla e State

MSM M

SSSSS: Port in Slave StateM: Port in Master State

S Ordinary Clock


Ordinary Clock

The Standard IEEE 1588 Version 2Transparent Clock

Master Clock Slave Clock

t Sync(t corr)Transparent Clock

t0 Sync(t0 , corr)

t1Sync(t0 , corr +Δs)Δs

Follow_up(t0)

t

_ p( 0)

Delay_Req(corr + Δr)t

t2Delay_Req(corr)

Δr

Delay_Resp(t3 , ∑corr) Time Stamping3

Δ Residence Time


t t

The Standard IEEE 1588 Version 2 Transparent Clock – End-to-End Delay Measurement

SS

STC

MS

TC

STC

TC

SS

Sync Stream e2e Delay Measurement


e2e Delay Measurement

The Standard IEEE 1588 Version 2 Transparent Clock – Peer-to-Peer Delay Measurement

SS

STC

MS

TC

STC

TC

SS

Sync Stream p2p Delay Measurement


p2p Delay Measurement

The Standard IEEE 1588Limits

Timestamp quantization effectsAccuracy of Start-of-Frame Detection Unknown portion of data path asymmetries in cables and transceiversJitter in the data path (PHY chips, network elements)E i t l ditiEnvironmental conditionsOscillator instabilitiesImplementation specific effects (e.g. phase between different asynchronous clock domains of all involved functional building blocks)Note: Uncertainty due to limited observation capabilities (e.g. the PPS output is subject of quantization effects as well)

Stochastic effects can be filtered out with statistical methodsSystematic errors remain


Systematic errors remain

The Standard IEEE 1588Industry Relevance

PTP is or will be applied in application areas such asTest and Measurement (LXI: LAN eXtensions for Instrumentation)Automation and control systems (various flavors of real-time Ethernets)Audio/Video Bridge (AVB according to IEEE 802.1as)Telecommunications

Silicon vendors and IP providers offerProtocol softwareHardware assistance IPsdw e ss s ce sPHYs with hardware assistance logicIEEE-1588 enabled microcontrollersSwitching cores with IEEE-1588 supportSwitching cores with IEEE 1588 support


Synchronous Ethernet


Synchronous EthernetPhysical Layer Timing in Legacy Ethernet

Ethernet works perfectly well with relatively inaccurate clocks

Each Ethernet link may use its own clockynominal clock rate is the same, but deviations of ± 50 ppm are allowed (dimensioning such that physical layer buffers do not underflow or overflow)

Details differ according to transmission technologyDetails differ according to transmission technologywhere the two directions of a link use different media (i.e. separate wire pairs or separate fibers), both directions may have independent clocksGBE over twisted pair uses all wire pairs simultaneously in both directions p p y

signal processing (echo compensation technique) requires same clock on both directions of a link

one PHY acts as the master, the other as slave


Synchronous EthernetTiming of a Fast Ethernet Link (100 Base-TX)

25 MHz ± 50 ppm

TX_CLK RX_CLKPHYMAC PHY MAC

RX CLK TX CLK

Cable

RX_CLK

25 MHz ± 50 ppm

TX_CLK

Symbol25 MHz ± 50 ppm

clkclk


transmission lineis driven by clk

clk recovered fromtransmission line

Synchronous EthernetPhysical Layer Timing in Legacy Ethernet

EE

XXE EXX

EX

X

X

X

EE


Synchronous EthernetTiming of a Gigabit Ethernet Link (1000 Base-T)

1000 Base-T transmission is split on 4 wire pairs operation simultaneously in both directions

transmitter and receiver are coupled via a hybridecho compensation is appliedboth directions require the same clock

A 1000 Base-T PHY can operate as a master or slave.

Master/slave role selection is part of the auto-negotiation procedure.

A i i i i h d i hi h d i ill b h d hi hA prioritization scheme determines which device will be the master and which will be slave.

The supplement to Std 802.3ab, 1999 Edition defines a resolution function to handle any conflicts:

multiport devices have higher priority to become master than single port devices.if both devices are multiport devices, the one with higher seed bits becomes the


master.

Synchronous Ethernet1000 Base-T uses 4 pairs simultaneously in both directions


Synchronous Ethernet1000 Base-T Pysical Layer Signalling with Echo Compensation


Synchronous EthernetTiming of a Gigabit Ethernet Link (1000Base-T)

25 MHz ± 50 ppm

GTX_CLK RX_CLKPHYMAC PHY MACMaster Slavex5

CLOCK_IN

RX CLK GTX CLK

Cable

RX_CLK

25 MHz ± 50 ppm

GTX_CLK

25 MHz ± 50 ppm

The Master PHY uses the internal 125 MHz clock generated from CLOCK_IN to transmit data on the 4 wire pairs.

Th Sl PHY th l k d f th it PHY th t it l k


The Slave PHY uses the clock recovered from the opposite PHY as the transmit clock.

Synchronous EthernetConcept - 1

Concept has been proposed, elaborated, and standardized by the Telco community in ITU-T by transferring the traditional SDH clock di ib i E h kdistribution concept to Ethernet networks

The Primary Reference Clock (PRC) frequency is distributed on the physical layer

a receiver can lock to the transmitter‘s frequencya switch selects the best available clockthis results in a hierarchical clock distribution tree

OAM messages (Synchronization Status Messages) are used to signal clock quality and sync failure conditions of the upstream switch

to allow selection of the best available timing source (stratum of upstreamto allow selection of the best available timing source (stratum of upstream source)to avoid timing loops


Synchronous EthernetConcept - 2

Active layer 2 data forwarding topology (as established by spanning tree protocol) and clock distribution tree are independent (i.e. a blocked port

d li h l k i i hb i i h)can deliver the clock to its neighboring switch)

Design rules (topology restrictions, priorities for source selection) guarantee clock quality

Clocking of Ethernet devices is changed in a way that is fully conforming with IEEE 802.3 standards

Standard PHY chips can be used as long as a few conditions are met e gStandard PHY chips can be used as long as a few conditions are met, e.g. PHY provides the recovered receive clock to the external worldGBE PHY allows master/slave role to be set by software (no automatic selection)selection)


Synchronous EthernetClock Sources for a Synchronous Ethernet Switch

Ext-In Ext-Out

Clock Selection / Regeneration

Oscillator

Clock Selection / Regeneration

Port 1 Port 2 Port … Port n


Synchronous EthernetPhysical Layer Timing in Synchronous Ethernet

EE

XPRC XE EXX

EX

X

X

X

EE

PRC tracable clock (other links


and directions are free running)

Synchronous EthernetCompared with IEEE 1588

Synchronous EthernetClock distribution based on

IEEE 1588Application layer protocol with Clock distribution based on

Ethernet‘s physical layer

Provides frequency only

Performance is independent of data

Application layer protocol with hardware assistance

Provides frequency and time of day

May be susceptible to specific dataPerformance is independent of data traffic

May be susceptible to specific data traffic patterns

Complementary technologies, can be used in combination:

Syncronous Ethernet delivers accurate and stable frequency to all nodes while IEEE 1588 can deliver time of day, where required.


Synchronous EthernetIndustry Relevance

Telco equipment manufacturers rely on both technologies

Synchronous Ethernet operation will certainly be an important feature in y p y pfuture carrier grade products

Synchronous Ethernet’s role in corporate and industrial communication application is not yet forseeableapplication is not yet forseeable

Silicon vendors and IP providers offerSynchronous Ethernet compatible PHYsIC f l k i i l i d iICs for clock monitoring, selection, and processing


Many thanks for your attention!

[email protected]

Zurich University of Applied Sciencesy ppInstitute of Embedded Systems

http://ines.zhaw.ch/ieee1588


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