Synchronous Circuit Design(Class 10.1 – 10/30/2012)

CSE 2441 – Introduction to Digital LogicFall 2012

Instructor – Bill Carroll, Professor of CSE

Today’s Topics

• Design of synchronous sequential circuits• Lab 8 prelab design exercise

Introduction to Synchronous Circuit Design (Synthesis)

• Given the circuit requirements (specifications), i.e., word description, state diagram, state table, etc.

• Find a hardware realization of the circuit.

z m

z 1

y r

C lo ck

y 1

M em o ry

C o m b in a tio n a llo g ic

... ...

. .....

x n

x 1

Y r Y 1

Introductory Design Example(from example 8.6, figure 8.21)

Given the following state diagram and state table. Derive a circuit realization.Assume D flip-flops will be used for memory.

State Diagram State Table

Generate the Transition Table

State Table StateAssignment

Transition Table(Binary state table)

(How many flip-flops are needed?)

Produce the Logic Equations

Transition Table(Binary state table) Output K-map Flip-flop Excitation (input)

K-maps

z = xy1’y2 + x’y1y2’ D1 = y1y2’ + xy2

D2 = x’y1 + xy1’

Realize the Logic Equations with Gates and Flip-flops

z = xy1’y2 + x’y1y2’

D1 = y1y2’ + xy2

D2 = x’y1 + xy1’

Lab 8 PreviewAnalyze, design and implement finite state machines (FSM)– Prelab

1. Use Quartus/Qsim to analyze a given synchronous circuit (FSM A)

2. Design a realization of a second circuit (FSM B) given it’s state diagram.

3. Use Quartus/Qsim to verify the design from 2 is correct.– In lab

1. Construct and test FSM A on the IDL 8002. Construct and test FSM B on the DE1

Test Your Understanding (Lab 8, Prelab 2)Design a realization of the following state diagram.

Use D flip flops as memory.

Test Your Understanding – Self-CheckGiven the state diagram.

xz1z20 1

A B 00

C B 01

D B 11

A B 10

Construct a state table.

A

B

C

D

y1y2

xz1z20 1

00 00 01 00

01 11 01 01

11 10 01 11

10 00 01 10

Y1Y2

Construct a Transition/Output Table Construct Excitation Table

For D flip-flops, transition tables and excitation tables are the same with D1=Y1 and D2 = Y2.

Test Your Understanding – Self-Check

Construct Excitation Maps Generate logic equations for D1, D2, z1, and z2

y1y2

x

0 1

00 0 0

01 1 0

11 1 0

10 0 0

y1y2

x

0 1

00 0 1

01 1 1

11 0 1

10 0 1

D1

D2

D1 = x’y2

D2 = x + y1’y2

z1 = y1

z2 = y2

Test Your Understanding – Self-Check

Realize the logic equations with gates and flip flops

Using JK Flip Flops as Memory for Figure 8.2 (Example 8.7)

x

0

0 1

0 0

0 1

11

1 0

0

0

d

d d

(c ) E xc ita tion m ap s

x

d

0 1

0 0

0 1

11

1 0

d

d d

1 0

0 0

x

0

0 1

0 0

0 1

11

1 0

1

d d

d d

1 0

K 1 J 2

1

d

x

d

0 1

0 0

0 1

11

1 0

d

1

d

0 1

d

K 2

0

J 1

(b ) E xc ita tion ta b le

J 1 K 1 J 2 K 2Y 1 Y 2/z

0 1x

00

01

1110

0 d

0 d

d 1d 0

0 d

1 d

d 0d 0

(a ) T ra n sit ion tab le

y 1 y 2 0 1x

00

01

1110

00 /0

00 /0

01 /011 /1

01 /0

11 /1

10 /010 /0

0 1x

0 0

0 1

111 0

0 d

d 1

d 01 d

1 d

d 0

d 10d

y 1 y 2 y 1 y 2

y 1 y 2 y 1 y 2 y 1 y 2y 1 y 2

Figure 8.23

J1 = xy2 K1 = x’y2 J2 = xy1’ + x’y1 K2 = xy1 + x’y1’

Clocked JK Flip-Flop Implementation (Example 8.7)x

z

C lock

y 1

y 2

Q

QCJ 1

Q

QCJ 2

K 1

K 2y 2

y 1

Figure 8.24

J1 = xy2 K1 = x’y2 J2 = xy1’ + x’y1 K2 = xy1 + x’y1’

Test Your UnderstandingDesign a realization of the following state diagram.

Use JK flip flops as memory.

Test Your Understanding – Self-CheckGiven the state diagram.

xz1z20 1

A B 00

C B 01

D B 11

A B 10

Construct a state table.

A

B

C

D

y1y2

xz1z20 1

00 00 01 00

01 11 01 01

11 10 01 11

10 00 01 10

Y1Y2

Construct a Transition/Output Table Construct Excitation Tables

y1y2

x

0 1

00 0d 0d

01 1d 0d

11 d0 d1

10 d1 d1

y1y2

x

0 1

00 0d 1d

01 d0 d0

11 d1 d0

10 0d 1d

J1K1 J2K2

Test Your Understanding – Self-Check

Construct Excitation Maps Generate logic equations for J1, K1, J2, K2, z1, and z2

y1y2

x

0 1

00 0 0

01 1 0

11 d d

10 d d

y1y2

x

0 1

00 0 1

01 d d

11 d d

10 0 1

J1

J2

J1 = x’y2

K1 = x + y2’

J2 = x

K2 = x’y1

z1 = y1

z2 = y2

y1y2

x

0 1

00 d d

01 d d

11 0 1

10 1 1

y1y2

x

0 1

00 d d

01 0 0

11 1 0

10 d d

K1

K2

Test Your Understanding – Self-Check

Realize the logic equations with gates and flip flops

Synchronous Circuit Design (Synthesis)

• Step 1 – Given a description (specification) of the circuit requirements, derive a state table that meets the requirements. Often it’s easier to first derive a state diagram followed by the equivalent state table.

• Step 2 – Find a state table with a minimum number of states that is equivalent to the original state diagram.

• Step 3 – Choose a state assignment and generate the state and output transition tables.

• Step 4 – Determine (select) the memory device or flip-flop type to be used and find the flip-flop excitation maps.

• Step 5 – From the excitation maps, produce (derive) logic equations for the flip-flop inputs. Also, form output maps and produce (derive) the output logic equations.

• Step 6 – Draw the logic circuit using the logic equations and appropriate logic devices (gates and flip-flops).