synchronous sequential networks
DESCRIPTION
Synchronous Sequential Networks. Sequential Network Model. Clocked Synchronous Sequential Network. Mealy Model. Outputs are only a function of the external inputs and the present state Z = g(X,Q). Mealy model of a clocked synchronous sequential network. Figure 7.3. Moore Model. - PowerPoint PPT PresentationTRANSCRIPT
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Synchronous Sequential Networks
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Sequential Network Model
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Clocked Synchronous Sequential Network
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Mealy Model
Mealy model of a clocked synchronous sequential network.Figure 7.3
Outputs are only a function of the external inputs and the present state
Z = g(X,Q)
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Moore Model
Moore model of a clocked synchronous sequential network.Figure 7.4
Outputs are only a function of the present state
Z = g(Q)
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Analysis of Clocked Synchronous Sequential Networks
• Excitation and Output Expressions
• Transition Equations• Transition Tables• Excitation Tables• State Tables• State Diagrams • Network Terminal Behavior
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Logic diagram for Example 7.1
Figure 7.5
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Logic diagram for Example 7.2
Figure 7.6
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Excitation and Output Expressions
• From example 7.1(7.4) (7.5)
(7.6)
• From example 7.2(7.7) (7.8)
(7.9) (7.10)
(7.11)(7.12)
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D1 = xQ2 +Q1Q2
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D2 = xQ1 +Q1Q2
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z = xQ1 + xQ1Q2
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J1 = y
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K1 = y + xQ2
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J2 = xQ1 + xyQ1
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K2 = x y + yQ1
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z1 =Q1Q2
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z2 =Q1 +Q2
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• From example 7.1(7.13)
(7.14)
• From example 7.2 (7.15)
(7.16)
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Q1+ = xQ2 +Q1Q2
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Q2+ = xQ1 +Q1Q2
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Q1+ = yQ1 + x yQ1 + yQ1Q2
Transition Equations
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Q2+ = xQ1Q2 + xyQ1Q2 + xyQ2 + xQ1Q2 + yQ1Q2
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Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
10111000
01110000
0011
1000
Example 7.1
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Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z1z2)
Input (xy)00 01 10 11
00011011
00011011
10110100
01000010
11110000
01001101
Example 7.2
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Excitation Table
Present state(Q1Q2)
Excitation(D1D2)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
10111000
01110000
0011
1000
Example 7.1
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Excitation Table
Present state(Q1Q2)
Excitation(J1K1,J2K2)
Output
(z1z2)
Input (xy)00 01 10 11
00011011
00,0000,0000,0000,00
11,0011,0011,1111,11
01,1100,1101,0100,01
11,1011,1011,0111,01
01001101
Example 7.2
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State Table
Present state Next state Output (z)Input (x) Input (x)0 1 0 1
00A01B10C11D
CDCA
BDAA
0011
1000
Example 7.1
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State Table
Present state Next state, Output (z)Input (x)
0 1ABCD
C,0D,0C,1A,1
B,1D,0A,0A,0
Example 7.1
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State Table
Present state
Next state Output
(z1z2)
Input (xy)00 01 10 11
00A01B10C11D
ABCD
CDBA
BAAC
DDAA
01001101
Example 7.2
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State diagram for Example 7.1
Figure 7.7
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State diagram for Example 7.2
Figure 7.8
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Timing diagram for Example 7.1
Figure 7.9
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The analysis procedure
Figure 7.10
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Modeling Clocked Synchronous Sequential Network Behavior
• State diagram• State Table• State Table Reduction: Implication table
• Transition table: State Assignment
• Excitation Table• Logic Diagram
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The serial binary adder
Figure 7.11
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State diagram for a Mealy serial binary adder
Figure 7.12
(a) Partial state diagram
(b) Completed state diagram
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State diagram for a Moore serial binary adder
Figure 7.13
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A sequence recognizer
Figure 7.14
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State diagram for a sequence recognizer
Figure 7.15
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A 0110/1001 sequence recognizer
Figure 7.16
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State diagram for the final example
Figure 7.17
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Experiment for determining equivalent pairs of states
Figure 7.18
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The structure of an implication table
Figure 7.19
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Implication table for determining the equivalent states of Table 7.13
Figure 7.20
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Implication table for determining equivalent states of the 0110/1001 sequence recognizer
Figure 7.21
(a) Initial table (b) Final table
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Next-state and output Karnaugh maps for the transition table of Table 7.17b
Figure 7.22
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A state-assignment map for the state table of Table 7.17a
Figure 7.23
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Guidelines for Obtaining State Assignments
Rule I: Two or more present states that have the same next state for a given input combination should be made adjacent
Rule II: For any present state and two adjacent input combinations, the two next states should be made adjacent
Rule III: Two or more present states that produce the same output symbol (0 or 1) for a given input combination should be made adjacent (only apply to one of the output symbols)
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Next-state and output Karnaugh maps for the transition table of Table 7.17c
Figure 7.24
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Two approaches to handling unused states. (a) State table. (b) Transition table with don’t-cares for unused states. (c) Next-state maps, output map, and expressions for table of Fig. 7.25b
Figure 7.25
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(d) Transition table when unused states cause the network to go to state A. (e) Next-state maps, output map, and expressions for table of Fig. 7.25d
Figure 7.25 cont.
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Logic diagram for the excitation table of Table 7.19
Figure 7.26
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Excitation and output maps for the excitation table of Table 7.20
Figure 7.27
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Logic diagram for the excitation table of Table 7.20
Figure 7.28
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Excitation and output maps for the Moore serial binary adder
Figure 7.29
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Logic diagram for the Moore serial binary adder
Figure 7.30
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General structure of a clocked sequential network realization using a PLD and clocked D flip-flops
Figure 7.31
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A clocked synchronous sequential network realization using a PLA and clocked D flip-flops
Figure 7.32