Release 12.1 - xst M.53d (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.34 secs --> Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.35 secs --> Reading design: cor.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "cor.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "cor"Output Format : NGCTarget Device : xc3s250e-4-cp132---- Source OptionsTop Module Name : corAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YESResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : autoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 24Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : autoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Library Search Order : cor.lsoKeep Hierarchy : NONetlist Hierarchy : as_optimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : Case Specifier : maintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "code/sbr.v" in library workCompiling verilog file "code/mux2.v" in library workModule compiledCompiling verilog file "code/mux1.v" in library workModule compiledCompiling verilog file "code/d_sh.v" in library workModule compiledCompiling verilog file "code/cor.v" in library workModule compiledModule compiledNo errors in compilationAnalysis of file succeeded. =========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .=========================================================================* HDL Analysis *=========================================================================Analyzing top module .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit . Related source file is "code/d_sh.v". Found 8-bit register for signal . Found 8-bit shifter logical right for signal . Summary:inferred 8 D-type flip-flop(s).inferred 1 Combinational logic shifter(s).Unit synthesized.Synthesizing Unit . Related source file is "code/sbr.v". Found 1-bit register for signal . Summary:inferred 1 D-type flip-flop(s).Unit synthesized.Synthesizing Unit . Related source file is "code/mux1.v". Found 8-bit register for signal . Found 8-bit addsub for signal . Summary:inferred 8 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit synthesized.Synthesizing Unit . Related source file is "code/mux2.v". Found 8-bit register for signal . Found 8-bit addsub for signal . Summary:inferred 8 D-type flip-flop(s).inferred 1 Adder/Subtractor(s).Unit synthesized.Synthesizing Unit . Related source file is "code/cor.v".WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.Unit synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 2 8-bit addsub : 2# Registers : 4 8-bit register : 4# Logic shifters : 2 8-bit shifter logical right : 2==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 2 8-bit addsub : 2# Registers : 32 Flip-Flops : 32# Logic shifters : 2 8-bit shifter logical right : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit ...Optimizing unit ...Optimizing unit ...Optimizing unit ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block cor, actual ratio is 2.Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 32 Flip-Flops : 32==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : cor.ngrTop Level Output File Name : corOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 39Cell Usage :# BELS : 142# INV : 1# LUT2 : 17# LUT3 : 37# LUT3_D : 4# LUT3_L : 1# LUT4 : 32# MUXCY : 14# MUXF5 : 20# XORCY : 16# FlipFlops/Latches : 32# FDR : 32# Clock Buffers : 1# BUFGP : 1# IO Buffers : 38# IBUF : 22# OBUF : 16=========================================================================Device utilization summary:---------------------------Selected Device : 3s250ecp132-4 Number of Slices: 47 out of 2448 1% Number of Slice Flip Flops: 32 out of 4896 0% Number of 4 input LUTs: 92 out of 4896 1% Number of IOs: 39 Number of bonded IOBs: 39 out of 92 42% Number of GCLKs: 1 out of 24 4% ---------------------------Partition Resource Summary:--------------------------- No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 32 |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: 4.892ns (Maximum Frequency: 204.415MHz) Minimum input arrival time before clock: 6.348ns Maximum output required time after clock: 5.749ns Maximum combinational path delay: 6.960nsTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.892ns (frequency: 204.415MHz) Total number of paths / destination ports: 272 / 32-------------------------------------------------------------------------Delay: 4.892ns (Levels of Logic = 4) Source: d7/r_3 (FF) Destination: d9/out_0 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: d7/r_3 to d9/out_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 3 0.591 0.610 d7/r_3 (d7/r_3) LUT3:I1->O 1 0.704 0.000 d9/Sh836_F (N26) MUXF5:I0->O 2 0.321 0.526 d9/Sh836 (d9/Sh836) LUT3:I1->O 1 0.704 0.424 d9/Sh8350 (d9/N3) LUT4:I3->O 1 0.704 0.000 d9/Sh868 (d9/Sh8) FDR:D 0.308 d9/out_0 ---------------------------------------- Total 4.892ns (3.332ns logic, 1.560ns route) (68.1% logic, 31.9% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 362 / 64-------------------------------------------------------------------------Offset: 6.348ns (Levels of Logic = 5) Source: sel (PAD) Destination: d9/out_0 (FF) Destination Clock: clk rising Data Path: sel to d9/out_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 39 1.218 1.439 sel_2_IBUF (sel_2_IBUF) LUT3:I0->O 1 0.704 0.000 d9/Sh836_F (N26) MUXF5:I0->O 2 0.321 0.526 d9/Sh836 (d9/Sh836) LUT3:I1->O 1 0.704 0.424 d9/Sh8350 (d9/N3) LUT4:I3->O 1 0.704 0.000 d9/Sh868 (d9/Sh8) FDR:D 0.308 d9/out_0 ---------------------------------------- Total 6.348ns (3.959ns logic, 2.389ns route) (62.4% logic, 37.6% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 16 / 16-------------------------------------------------------------------------Offset: 5.749ns (Levels of Logic = 2) Source: d6/r_5 (FF) Destination: o1 (PAD) Source Clock: clk rising Data Path: d6/r_5 to o1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 4 0.591 0.762 d6/r_5 (d6/r_5) LUT2:I0->O 1 0.704 0.420 o11 (o1_5_OBUF) OBUF:I->O 3.272 o1_5_OBUF (o1) ---------------------------------------- Total 5.749ns (4.567ns logic, 1.182ns route) (79.4% logic, 20.6% route)=========================================================================Timing constraint: Default path analysis Total number of paths / destination ports: 16 / 16-------------------------------------------------------------------------Delay: 6.960ns (Levels of Logic = 3) Source: rst (PAD) Destination: o1 (PAD) Data Path: rst to o1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 48 1.218 1.346 rst_IBUF (rst_IBUF) LUT2:I1->O 1 0.704 0.420 o21 (o2_7_OBUF) OBUF:I->O 3.272 o2_7_OBUF (o2) ---------------------------------------- Total 6.960ns (5.194ns logic, 1.766ns route) (74.6% logic, 25.4% route)=========================================================================Total REAL time to Xst completion: 6.00 secsTotal CPU time to Xst completion: 5.82 secs --> Total memory usage is 242376 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 4 ( 0 filtered)Number of infos : 1 ( 0 filtered)