sysc 2001*: copyright ©t. pearce, d. hutchinson, l. marshall nov. 2002 virgo lectures- revised nov....

SYSC 2001*: copyright ©T. Pearce, D. Hutchinson, L. Marshall Nov. 2002Virgo lectures- revised Nov. 14, 2006

1

Virgo

Ch. 11 of Stallings has been incorporated into these slides.


2

Computer System

p86 Processor

Memory

I/O

Bus

Connected Devices

keyboard

display

registers

locationsinstructions

& data

ports

Virgo Computer System Model


3

Virgo Computer System Model

Registers: 16-bits wide Cells: 8-bit contents, 16-bit address

Ports: read/write 8-bit values, 16-bit address

Model behaviour of components (and of programs!) in terms of these state variables


4

Stored Program Concept

1. instructions are encoded into binary values

2. encodings of instructions are loaded into memory

3. processor retrieves and executes instructions from memory (one at a time)

instructions encodings have variable length• 1 to 6 bytes• not every binary value 1 to 6 bytes long

corresponds to an instruction


5

encoded instructions are indistinguishable from encoded information ! (same binary values!)

Programs Inside The Black Box

instructions

1 to 6 bytebinary values


6

Little Endian Memory Storage

little endian (Intel) the least significant byte at the low address

lsbytemsbyte lsbyte

memorycontents address

msbyte

X

X + 1

16-bit value


7

p-86 Register Set

Four 16-Bit General Purpose Registers• can access 16-bits, high (H) byte, low (L) byte

AH AL

BH BL

CH CL

DH DL

AX

BX

CX

DX

8 bits8 bits


8

P-86 Register Set (cont’d)

16-Bit Addressing Registers (no 8-bit access!)

IP Instruction Pointer (i.e. PC)

SP Stack Pointer

BP Base Pointer

SI Source Index

DI Destination Index


9

P-86 Register Set (contd)

FLAGS Register (status flags – one bit/flag)

• 16-bit reg, but only some bits have meaning

• treat as individual bits, not 16-bit value

• ignore unused bits

ZF Zero Flag

CF Carry Flag

SF Sign Flag

OF Overflow Flag

IF Interrupt Flag

data manipulation& conditional control flow


10

P-86 Register Set (contd)

Other Registers in Programmer’s Model• support the execution of instructions• cannot be accessed directly by programmers• often larger than 16-bits• temporary reg’s (scratchpad values)

IR Instruction Register


11

Data Transfer Example

MOV (Move) Instruction

syntax: MOV dest , src

semantics: dest := src copy src value to dest state variable register and memory operands only (I/O ??)


12

Register Addressing Mode allows a register to be an operand

• as source: copy register value• as destination: write value to register

e.g. MOV AX, DX ; value in DX is ; copied to AX

AX := DX register addressing mode for both dest and src dest and src must be same size

• MOV AH, CL ; This is OK• MOV AL, CX ; This is not OK (why?)


13

Syntax Note on Constants

Decimal default Hexadecimal:

• always starts with digit 0 – 9• after start may include 0 – 9, and A – F

– case insensitive for A – F • ends with “H” (or “h”)

e.g. 1h, 23H, 0A2cH, 2a3DhAH ?????


14

Immediate Addressing Mode allows constant to be specified as source

• source value assembled into the instruction• value obtained from IR as instruction executed

e.g. MOV AL, 5 ; AL is 8 bit dest• instruction encoding includes 8-bit value 05h

what about: MOV AX, 5• 16-bit dest: encoding includes 16-bit value 0005h

what about MOV 4, BH ; lets be ridiculous• dest as immediate value ?


15

Direct Addressing Mode

specify the address of a memory operand• specify address as a constant value• address gets encoded as part of instruction• must be known when program is assembled !

use square brackets “[” and “]” to clarify immediate vs. direct!

[A] means A is the address of the operand

MOV AX, 3FC0H ; AX := 3FC0H

MOV AX, [ 3FC0H ] ; AX:= contents from memory

locations starting at 3FC0H

endian ???


16

Simple Indirect Addressing Mode

simple form: use current contents of a register as the address of an operand

only these registers can be used:• for memory operands:BX, BP, SI, DI

• for I/O operands: DX

e.g. MOV CX, [ BX ]

• contents of BX are used as the address of the memory containing value (16-bit, little endian) to load into CX

• only makes any sense if earlier instruction(s) put a useful address into BX!

more complex forms later!


17

Indirect Addressing Mode (contd) potential ambiguity?

MOV CX, [ BX ] v.s. MOV CX, BX

register, immediate and direct are static modes• operand bound to instruction at assemble-time

indirect is a dynamic mode• operand bound to instruction at run-time• depends on values at time instruction executed• more powerful! more complicated!


18

Manipulating I/O Ports

MOV allows only register and memory operands so . . . what accesses I/O ports?

• IN read a value from a port• OUT write a value to a port

IN / OUT: always use AL (or AX) and [DX]


19

I/O Port Example For now: OUT [DX], AL

• the 8-bit value in AL is written to the I/O port addressed by the contents of DX

indirect mode to specify I/O port! Display character at the “current” cursor position:

• write 7-bit ASCII encoded char to port 04E9H• must set up DX to point to I/O port• must set up AL to contain char• write: display char and “advance” cursor


20

I/O Example (contd)

MOV DX, 04E9H ; set display port address

MOV AL, 30H ; char = ‘0’ (ASCII!!)

OUT [DX], AL ; put char on display

(whew!) Enough for a simple program?

MOV and OUT


21

Program Fragment

mov dx, 04E9H

mov al, 'H'

out [dx], al

mov al, 'i'

out [dx], al

hlt

output ‘H’

output ‘i’


22

Assembler Program

; simple program that displays 'Hi' start: mov dx, 04E9H ; get display port address mov al, 'H' ; display 'H' out [dx], al ; mov al, 'i' ; display 'i' out [dx], al hlt ; STOP! end start

comments start with “ ; ”

label definition

where program starts

directive


23

Assembler Program

above is “source” code – human-oriented must be converted to binary values for loading

into memory ASSEMBLER is a program that encodes /

translates this sort of repr. of a program into the internal repr. required to run it.

CROSS ASSEMBLERS translate into internal repr. for different machines


24

Operand Compatibility operands must have compatible sizes if register mode is used, then no ambiguity

operand size = register size But no register operands potential ambiguity! Consider:

MOV AX, 1

MOV [ BX ], 1

MOV [1234H], 0 8-bit or 16-bit moves? default?

16-bit operand no ambiguity!


25

Operand Compatibility (contd)

need syntax to remove ambiguity qualify off-processor access using:

WORD PTR word pointer – 16-bit operand

BYTE PTR byte pointer – 8-bit operand

e.g. no ambiguity with:

MOV BYTE PTR [ BX ], 1 ;8 bit dest

MOV WORD PTR [1234H], 0 ;16 bit dest


26

Data Manipulation Instructions use state variable values to compute new values modify state variables to hold results (incl FLAGS)

ADD dest, src

dest := dest + src (bitwise add) dest is both a source and destination operand also modifies FLAGS as part of instruction execution: ZF := 1 if-and-only-if (iff) result = 0 SF := 1 iff msbit of result = 1 (sign = negative) CF := 1 iff carry out of msbit OF := 1 iff result overflowed signed capacity


27

Data Manipulation Example

Suppose that AH contains 73H, when

IP ADD AH, 40H

results: AH := 0B3H

ZF := 0 result 0

SF := 1 result is negative (signed)

CF := 0 (no carry out of msbit)

OF := 1 +ve + +ve = ve


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More Data Manipulation Instructions

SUB dest, src (Subtract)

dest := dest – src• like ADD, but bitwise subtract• modifies flags as in ADD, except:

CF := 1 iff borrow into msbit

CMP dest, src (Compare)• like SUB, except dest is not modified• modifies FLAGS ONLY !


29


DIV src (Unsigned Integer Divide)

where src may be specified using: register, direct or indirect mode, NOT immediate mode! size of divisor (8-bit or 16-bit) is determined by size of

src if direct or indirect used for src, must clarify size using

BYTE PTR or WORD PTR

e.g. DIV WORD PTR [BX ]


30

DIV src

for 8-bit src: divide src into 16-bit value in AX• two 8-bit results• AL := AX src (unsigned divide)• AH := AX mod src ( unsigned modulus)

flags are undefined after DIV (values may have changed, no meaning)


16-bit dividend8-bit divisor (src)


31


DIV src for 16-bit src:

• divide src into 32-bit value obtained by concatenating DX and AX (written DX:AX)

• AX := DX:AX src (unsigned divide)

• DX := DX:AX mod src (unsigned modulus)

• flags are undefined after DIV what if result is too big to fit in destination?

e.g. AX 1 ?? AL = ?? overflow trap – more later!

32-bit dividend16-bit divisor (src)


32

Control Flow Instructions

See Instruction Reference (posted) for more complete list of instructions – includes effects on FLAGS !!

execution may change value in IP changes address for fetch of next instruction


33

Why is C++ called a structured language? e.g.: C++ control flow

if ( condition ){ block T: do this if condition true; }else { block F: do this if condition

false;} next_statement;

if condition is true continue sequentially into block T, at end of block T, must skip to next_statement

if condition false skip past block T to block F, then continue sequentially through block F and on to next_statement

High Level Language Example

May use data manipulation

to decide condition

Need control flow instructions to ‘skip’


34

JMP Instruction

JMP target (Unconditional JUMP) IP := IP + target

control is always transferred to the specified target target operand is assembled as an immediate, 16-bit, signed

value relative offset (in bytes) from the end of the JMP instruction

to the start of the next instruction to be fetched• 16-bit signed value • +ve allows JMP forward (to higher address)• –ve allows jump backwards (to lower address)

e.g. loop back


35

Execution of JMP

Address Contents

0034H 0E9H

0035H 10H

0036H 00Hstart of fetch: IP = 0034H IR = ????????

after fetch: IP = 0037H IR = E9 0010

after execute: IP = 0047H IR = E9 0010

JMP 0010H

16-bit relative offset


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specify condition in terms of FLAG valuese.g. JZ JumpZero

if ZF = = 1: then jump to JumpZero else continue

e.g.: looping exampleMOV CX,5 ;loop 5 times

DoLoop:

. . .

SUB CX, 1

JNZ DoLoop

many possible conditions - see Instruction Reference

Conditional Jumps

label: identifies an address


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Conditional Jumps (contd) often condition and “not” condition are valid instr e.g. JZ dest (Jump Zero)

JNZ dest (Jump Not Zero)JC dest (Jump Carry)

• more too! (see Instruction Reference!) Conditional Jump often follows CMP

CMP AL, 10

JL LessThanTen. . . ; some code here

LessThanTen:


38

Conditional Jumps (contd)

CMP dest, src (Compare) performs dest value – src value and sets FLAGS

• does not modify dest! often useful to think of combination as:

CMP dest, srcJxx jmpdest

jump is taken if “dest xx src” condition holds Some conditions for xx: JE Jump Equal (opposite is JNE) JL Jump Less Than (JNL) JLE Jump Less Than or Equal (JNLE) JG Jump Greater Than


39


processor provides FLAGS to reflect results of (binary) manipulation under both signed and unsigned interpretations

jump instructions for different interpretations! Unsigned Signed

JA Above JG Greater

JAE Above or Equal JGE Greater or Equal

JB Below JL Less

JBE Below or Equal JLE Less or Equal (instructions for Not conditions too!)


40


Suppose AX contains 7FFFH:

Scenario 1 Scenario 2CMP AX, 8000H CMP AX, 8000H

JA Bigger JG Bigger

In each scenario, is the jump taken? Why? Programmer MUST know how binary values are

to be interpreted! (e.g. value in AX above)


41


Conditional jump limitation: uses 8-bit signed relative offset!

IP := IP + offset can’t jump very far! – 128 +127 bytes example: JL Less

Less:

MOV . . .

maximum possible distance = 127 bytes

some code here

8 bits, ‘sign extended to 16 bits’


42

Conditional Jumps (contd) One possible workaround if distance is greater than 127

bytes (but not the only one!):JNL Continue

JMP Less

Continue:

Less:

MOV . . .

distance >> 127 byteslots of

code here

16-bit relative offset


43

Problem: must convert ideas (human thoughts) into an executing program (binary image in memory)

Need: DEVELOPMENT PROCESS people-friendly way to write programs tools to support conversion to binary image

assembly language: used by people to describe programs • syntax: set of symbols + grammar rules for

constructing statements using symbols• semantics: what is meant by statements; ultimately:

the binary image

Assembly Language / Development Process


44

assembler: program – converts programs from assembly language to object format• object format: an intermediate format

– mostly binary, but may include other info

linker: program that combines object files to create an “executable” file

loader: loads executable files into memory, and may initialize some registers (e.g. IP )

Assembler, linker and loader are tools.

Assembly Language / Development Process


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Development Process

.EXELinker

loader is part of operating system (or possibly debugger)

Virgo simulator loads .OBJ files directlyNo Linker in Virgo!No .EXE file Computer System

memory

Loader

processor IP

.OBJ

.ASM file

.OBJ

.LST file

Assembler

Human readable results (including assembly errors) Can see what code was generated by assembler

may link multiple OBJ files

Editor

people work here


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people create .ASM files using assembly language

syntax must account for all aspects of a program and development process:• constant values

• reserve memory to use for variables

• write instructions: operations & operands

– addressing modes

• directives to tools in development process

p86 Assembly Language


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binary value: consists of only 0’s and 1’s ends with ‘B’ or ‘b’, e.g. 10101110b

hexadecimal value: starts with 0 .. 9 may include 0 . . 9, A .. F (a . . f ) ends with ‘H’ or ‘h’, e.g. 0FFH (8-bit hex value)

decimal value: default format – no “qualifier” extension consists of digits in 0 . . 9, e.g. 12345

string: sequence of characters encoded as 7-bit ASCII bytes: enclosed in single quotes, e.g. ‘Hi Mom’ (6 bytes) character: string with length = 1

p86 Assembly Language: Constants


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user-defined names – represent addresses lets programmer refer to addresses using logical names

– no need for concern with exact hexadecimal values leave assembler to:

• decide exact addresses to use• deal with hexadecimal addresses

labels are used to identify addresses for:• control flow – identify address of target• memory variables – identify address where data is

stored labels serve in 2 roles:

• label definition and label reference

p86 Assembly Language: Labels


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used by assembler to decide exact address must be first non-blank text on a line user-defined name followed by “:” name must start with alpha A .. Z a .. z then contain: alpha, numeric, ‘_’

• e.g. Continue: L8R: Out_2_Lunch:

cannot redefine reserved words • e.g. MOV: is illegal

p86 Assembly Language: Label Definition


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label represents address of first allocated byte after definition• e.g. DoThis: MOV AX, [ BX ]• DoThis represents address of first byte of the MOV instruction

label reference: use of label in an operand • refers to address assigned by assembler (no “:”)

control flow example (assume CX contains loop counter):DoWhile:

CMP CX, 0JE DoneDoWhile

…JMP DoWhile

DoneDoWhile: MOV AX, . . . (etc.)

p86 Assembly Language: Label Address/Reference

label definitionslabel references


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reserve memory for variables 2 sizes:DB ;reserves a byte of memoryDW ;reserves a word (2 bytes) of

memory may also provide (optional) initialization value as an operand

Examples:DB ; reserves one byte

X: DB ; reserves one byte – label X is

; defined to represent the address; of the byte

Y: DB 3 ; reserve one byte – label Y etc.

; and initialize the byte to 3

p86 Assembly Language: Memory Declarations


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Examples (continued):

DW ; reserve 2 consecutive bytes

Z: DW ; reserves 2 bytes – label Z is defined to ; represent the address of the first byte

W: DW 256 ; reserve 2 bytes – label W etc., and; initialize the bytes to 256 decimal (little endian !!!)

HUH: DW W ; reserve 2 bytes – label HUH etc., and ; initialize the bytes to contain the address ; of the variable W above

A:B: DB ‘C’ ; reserves 1 byte – labels A and B both

; represent the address of the byte, and ; initializes it to 43H

p86 Assembly Language: Memory Declarations


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complete instruction must be on one line instruction mnemonic & operands operands

• immediate: constant – can use label reference, example:

W: DW . . .

MOV BX, W • register: register name• direct: [ address ]

– state address as a label reference, example:W: DW

. . .MOV AX, [ W ]

p86 Assembly Language: Instructions


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Operands (continued)• register indirect: [ register ]

– exampleW: DW

. . .MOV BX, W MOV AX, [ BX ]

• relative-offset (control flow)– use label reference to identify target address– assembler calculates actual offset

JMP There . . . There:

etc.

p86 Assembly Language: Instructions


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statements that are intended to help tools are not assembled directly into instructions or memory

declarations

END Directive: directive to 2 tools: assembler and loader directs assembler to stop reading from .ASM file

• any subsequent statements are ignored operand: must be a label reference

• interpreted as specifying the address of the first instruction to be executed

• directs loader to load specified address into IP after loading .OBJ file

Syntax: END label-reference

p86 Assembly Language: Tool Directives


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each pass: processes all statements in .ASM file sequentially from start to finish

1st Pass: for each statement:1. check syntax 2. allocate any memory needed for image

– memory declaration (DB, DW)– instruction: opcode + operands

3. if encounter a label definition: assign value to label and keep record of (label, value) association in Symbol Table

if syntax errors in 1st pass, then write errors to .LST file and stop, else ....

2nd Pass: build binary for each statement:• may require calculating offsets – may result in errors – e.g. trying to jump too far for a

conditional jump (target out of range)• write results to .LST file• if no errors – write results to .OBJ file

p86 Assembly Language: 2 Pass Assembly Process


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Memory Allocation: assumes allocation starts at address 0000H uses location counter ($) to track address of next byte to allocate as bytes are allocated, adjust $ value for each memory declaration: (DB, DW)

• allocate # bytes declared • for example: suppose $ = 0006H and next line of program is: DW

– will allocate 2 bytes for DW statement:» use address 0006H for low byte» use address 0007H for high byte

– after allocation: $ = 0008H (next byte to allocate)• if next line of program is: DB ‘Hi Mom’

– will allocate 6 bytes for DB statement» use address 0008H for ‘H’, …, 000DH for ‘m’

– after allocation: $ = 000EH

p86 Assembly Language: 1st Pass in Detail


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for each instruction:• allocate bytes needed to encode opcode and operands• example: suppose $ = 0006H when next line of program is:

MOV CL, BL

– requires 2 bytes to encode instruction: opcode, CL dest, BL source– after allocation: $ = 0008H

if next line of program is:MOV BX, 1

– requires 4 bytes to encode• 2 bytes: opcode, BX dest, imm as src• 2 bytes: imm src value

– after allocation: $ = 000CH when a label definition is encountered:

• value of label = $

– value of label is the address of the next byte allocated to the program• save (label, $-current-value) in Symbol Table for recall during 2nd pass

p86 Assembly Language: 1st Pass in Detail

Instruction encodingdetails later


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build image of bytes to be loaded at addresses memory declaration: initialization value?

• if no init value – use default? instructions: opcodes and operands

• addressing mode info• label references in operands: look up values to use for label

in Symbol Table• for relative-offsets: offset = label-value – $

results to .LST file• errors• include image created (even if errors!)

.OBJ file contains image in format that can be loaded by simulator (only if no errors!)• includes info about “start address” – to initialize IP during

loading

p86 Assembly Language: 2nd Pass in Detail


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$ binary image0000 start:0000 C7C2E904 mov dx, 04E9H 0004 C6C048 mov al, 'H'0007 EE out [dx], al0008 C6C069 mov al, 'i'000B EE out [dx], al000C F4 hlt

end startAfter 1st Pass: syntax OK bytes have been allocated to statements Symbol Table constructed:

Symbol Value start 0000H

After 2nd Pass: binary image constructed

p86 Assembly Language: HI.LST ExampleLabel definition: in 1st pass – put

value in Symbol table


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34 0000 Start:35 0000 C7C4FEFF mov sp, 0FFFEH37 0004 C7C2E904 mov dx, 04E9H 43 0008 C6C510 mov ch, 1644 000B C6C101 mov cl, 145 000E 8B1EA300 mov bx, [Value] 47 0012 Outloop:48 0012 D3E3 shl bx, cl 49 0014 7206 jc Got150 0016 Got0: 51 0016 C6C030 mov al, ‘0’52 0019 E90300 jmp Dump54 001C Got1:55 001C C6C031 mov al, ‘1’

57 001F Dump:58 001F EE out [dx], al

p86 Assembly Language: Example


62

60 0020 80ED01 sub ch, 161 0023 75ED jnz Outloop 8< --------- SNIP! ---------------------

316 009B 0A00 Ten: dw 10317 009D 6400 Hundred: dw 100318 009F E803 Thousand: dw 1000319 00A1 1027 TenThousand: dw 10000

321 00A3 AF90 Value: dw 090AFH

Symbol ValueStart 0000HOutloop 0012HGot0 0016HGot1 001CHDump 001FHTen 009BHHundred 009DHThousand 009FHTenThousand 00A1HValue 00A3H

p86 Assembly Language: Example

Note: Do not confuse $ with IP!

$ = artifact of assemblerIP = artifact of processor


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allows declaration of symbolic constants improves (human) readability reduces the use of “magic numbers” Syntax:symbolic-name EQU numeric-constant

1st Pass: records (symbolic-name, constant) in symbol table

2nd Pass: replaces every occurrence of the symbolic-name with the specified constant• is NOT allocated any bytes !!!

p86 Assembly Language: EQU Directive

Note: No “:”


64

DisplayPort EQU 04E9H ; magic number

MOV DX , DisplayPort

; improved readability

is assembled to same encoding as

MOV DX , 04E9H

p86 Assembly Language: EQU Example


65

allows specification of the address of the next byte to be allocated

Syntax:

ORG numeric-constant

Assembler assigns location counter the value of the specified numeric constant

p86 Assembly Language: ORG Directive


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…JMP DoAtF000H

; suppose this instruction was ; assembled to bytes starting at 0120H

ORG 0F000HDoAtF000H:

MOV BX , . . .

; MOV instruction will be assembled ; to bytes starting at address F000H

Must always increase location counter (never decrease) Typical use:

• Force assembly to specific address range• Resulting code will reside in particular type of memory

located at that address (e.g. ROM)

p86 Assembly Language: ORG Example


67

Addressing Mode “A way for instructions to indicate the location of

an operand” Location may be:

• register• memory• I/O

Operand value may not be immediate, i.e. directly available in the instruction encoding. Then there must be info to determine • Effective Address (EA) of the operand: the address of the

location in the system that holds the operand value.


68

Addressing Modesmode instruction holds

Immediate* value to use as operand Direct* memory address of operand (pointer!) Indirect** address of cell containing address of operand Register* name of register to use as operand Register Indirect* name of register containing address of operand Displacement (Indexed) combine Reg. Indirect + Direct Stack ** implicit stack as operand

*we have discussed these before** not available in Virgo


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Memory Indirect Addressing (1)

Instruction operand field contains A=address of pointer to operand

Memory cell pointed to by address field contains the address of (pointer to) the operand

EA = (A)• Read (x) to mean “contents of cell x”

• AEAoperand

e.g. ADD [[ A ]] (not Virgo syntax?)• Add contents of cell pointed to by contents of A to accumulator

No memory indirect addressing in Virgo


70

Memory Indirect Addressing (2)

May be nested / cascaded• e.g. EA = (((A)))

– Draw the diagram yourself (linked list?)

Multiple memory accesses to find operand Hence slower



71

Memory Indirect Addressing Diagram [[ A ]]

Address AOpcode

Instruction

Memory

Operand

Pointer to operand



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direct mode: EA = A

• E.g. MOV AX,[Mess]

• OK for static addresses indirect register mode: EA=(R)

• e.g. MOV AX,[BX]

• OK for dynamic addresses to access byte or word

• must have exact address in register need more powerful modes for data structures

What is a data structure?

*Note: the Effective Address (EA) expressions with the round brackets describe these addressing modes in the notation used by Stallings Ch. 11.1

Indirect Addressing


73

composite structures: collections of elements1. array: elements are all of the same type

• in high-level language access using [ ] selector, e.g. X[ i ]

2. record (struct): may include elements of different typese.g. struct student {

string Name;int ID; }

• in high-level language access using “.” selector, e.g. X.Name

3. arrays of structures e.g. 201Class[ i ].Name4. stack: more later!want dynamic access to elements

Addressing modes for Data Structures


74

Arrays: start address is static or dynamic elements are stored sequentially all elements are of same type

• fixed memory requirement for each element

• constant offset (# or bytes) to start of next element

2 relevant cases in programming:• Start address of array is static

• Start address of array is dynamic

Addressing modes for Arrays


75

1. Start address of array is static• writing program for a specific array

– e.g. arrayX in assignment 5

2. Start address of array is dynamic• writing program for “any” array

– e.g. a function that processes an array and accepts the array as an argument

– different invocations of the function may process different arrays

Virgo addressing modes exist to support both cases

Addressing modes for Arrays (cont.)


76

Virgo ‘(Indirect) Indexed Addressing Mode’ : use when accessing array using static address

like register indirect, except also specify a constant• e.g. [ BX + constant ] i.e. EA = (BX)+constant

during execution, processor uses a temporary register to calculate BX + constant

accesses memory addressed by BX + constant restriction: may only use BX, BP, SI or DI (as for

register indirect)!

Array start address is static


77

to use in accessing an array:• start address of array is the constant• use register to hold index

– index = offset (in bytes) to specific element

e.g. suppose have array of integers declared:arrX: DW ; 1st element of array

DW ; 2nd element of array. . . ; etc.

SizeOfX: DW ; number of elements in X each element is 2 bytes long!

Static start address (cont.)


78

; sum the contents of array X into AXMOV AX, 0 ; initialize sumMOV BX, 0 ; initialize array indexMOV CX, [SizeOfX] ; get # of elements

CheckForDone:CMP CX, 0 ; any elements left to sum?JE Done ADD AX, [ BX + arrX ] ; sum ith element ADD BX, 2 ; adjust index (offset)SUB CX, 1 ; one less elementJMP CheckForDone

Done: ; at this point:AX = sum of elementsBX = offset to byte that follows array X in memoryCX = 0

Static start address: Code Fragment

arrX is static; BX has dynamic offset


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overflow?• what if sum exceeds capacity of AX?• what conditions should be tested? why?• JO vs. JC ??

could the control flow be more efficient?; set up AX, BX, CX as before

CMP CX, 0 ; any elements left to sum?JE Done

SumElement:ADD AX, [ BX + arrX ] ; sum ith elementADD BX, 2 ; adjust index (offset)SUB CX, 1 ; one less elementJNZ SumElement

Done: Eliminated 2 instructions from the loop, and used one byte less memory

(JNZ vs JMP)

Static start address: Example (cont.)

Don’t do CMP, flags set by SUB


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could the control flow be even more efficient ?• adjust CX only at start of loop execution?• adjust CX only at end of loop execution?

; set up AX, BX, CX as beforeCheckForDone:

SUB CX, 1 ; any elements left to sum?JC Done

ADD AX, [ BX + arrX ] ; sum ith elementADD BX, 2 ; adjust index (offset)JMP CheckForDone

Done:

Or:; set up AX, BX, CX as before

JMP CheckForDoneSumElement:

ADD AX, [ BX + arrX ] ; sum ith elementADD BX, 2 ; adjust index (offset)

CheckForDone:SUB CX, 1 ; one less elementJAE SumElement

Done:

Static start address: Efficiency


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Virgo: ‘(Indirect) Based Addressing Mode’ EA=(BX)+(SI) to access array using dynamic address like indexed, except use a register instead of a constant

• e.g. [ BX + SI ] during execution, processor uses a temporary register to calculate sum of

register values accesses memory addressed by sum restrictions: one must be base register: BX or BP one must be index register: SI or DI the only legal forms:

• [ BX + SI ] [ BX + DI ] [ BP + SI ] [ BP + DI ] often, the start address of an array is supplied as an argument to a function

• put this value in one register use other register to hold offset (index) into array

Array start address is dynamic


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; assume BX = start address of array,; and CX = number of array elements; now sum the contents of array into AX MOV AX, 0 ; initialize sum

MOV SI, 0 ; initialize array index CheckForDone:

CMP CX, 0 ; any elements left to sum?JE Done

ADD AX, [ BX + SI ] ; sum ith elementADD SI, 2 ; adjust index (offset)SUB CX, 1 ; one less elementJMP CheckForDone

Done: ; at this point: AX = sum of elements

Dynamic start address: Code Fragment


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like based, except include a constant too• e.g. [ BX + SI + constant ] i.e. EA=(BX)+(SI)+constant

during execution, processor uses a temporary register to calculate sum of values

accesses memory addressed by sum restrictions: same as based mode if start address of array of arrays is known:

• use start address as constant• use one register as offset to start of sub-array• use other register as index

if start address is not known, wing it! if array of structures:

• use one register for start address • use one register as offset to start of structure• use constant to select element

that’s all for (indirect) addressing modes!

Virgo (Indirect) Based-Indexed Addressing Mode

Some possible applications –use your imagination!


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Summary of Addressing Modes Available in Virgo-ways in which an operand can be specified

1. Immediate op dest,C not applicable2

2. Direct op dest,[A] EA=A3. Register direct op dest,R EA=R4. Register Indirect op dest,[R] EA=(R)5. Indexed op dest,[R+A] EA=A+(R)6. Based op dest,[R1+R2] EA=(R1)+(R2)7. Based-Indexed op dest,[R1+R2+A] EA=(R1)+(R2)+ANotes:

1) op is some opcode mnemonic, e.g. MOV or ADD. C means “some constant”, A means “some address” and R,R1,R2 mean “some registers”. In Virgo there are restrictions on which registers can be used in these expressions.

2) For immediate operands no memory address is required, as the operand is in the IR already.

Virgo term for

addressing mode Form of Virgo instruction

Corresponding Effective

Address Expression for

source operand

op dest, source


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Immediate Addressing

Value COpcode

Instructionin IR

addressing mode=“immediate”


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Direct Addressing

Address AOpcode

Instruction

Memory

Operand

in IR

addressing mode=“direct”


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Register Direct

Register Address ROpcode

Instruction

Registers

Operand

addressing mode=“register direct”

in IR


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Register Indirect Addressing Diagram

Register Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

addressing mode=“register indirect”in IR


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Displacement/Indexed Addressing Diagram

Register ROpcode

Instruction

Memory

OperandOffset to Operand

Registers

Address A

+

addressing mode=“indexed”in IR


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Indexed-Based Addressing Diagram

BaseRegister R1Opcode

Instruction

Memory


Registers

Register R2

+

addressing mode=“based”

Base address

in IR


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Indexed-Based Addressing Diagram

BaseRegister R1Opcode

Instruction

Memory


Registers

Index Register R2

+

addressing mode=“indexed-based”

Base address

Address A

in IR


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a data structure often used to hold values temporarilyConcept: a “stack” is a pile of “things”

• e.g. a stack of papers one “thing” is on top

• the rest follow beneath sequentially can add or remove “things” from top of pile if add a new “thing”, it is now on top (change state) if remove a “thing” from the top, then “thing” that was below it

in the pile is now on top (read state) can look at a thing in the stack if you know the position of the

thing relative to the top• e.g. 2nd thing is the one below the top

Stacks


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stack holds “values” reserve a block of memory to hold values use a pointer to point to the value on top

General case of operation: pointer points to value on top of stack add:

1. adjust pointer to next free (sequential) memory location2. copy value to selected memory location (becomes new top)

remove: 1. copy value of current top 2. adjust pointer to point to value “beneath” current top (becomes

new top) read:

• index from top pointer to ith item

Stacks: Implementation in a Computer


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Stacks: Implementation in a Computer

top pointer item on topnext item

last item

unused locations

items in stack

block of memory

next location for adding a value


last item

unused locations

items in stack

block of memory



last item

unused locations

items in stack

block of memory


Low address

High address


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empty stack (no items in stack)• what should top pointer point to?• implementation: usually points just outside the reserved block – next add

will adjust pointer before copying value – will copy into location in the block

full stack (no space to add more items)• what should happen if an item added?• implementation could:

– check for stack overflow (?) (exception handling!)– happily overwrite memory outside of reserved block (?)

Issue: Should stack grow from high-to-low addresses (as drawn in picture), or vice versa ?• conceptually: no difference• implementation: typically grows high-to-low

Stacks: Implementation: Special Cases


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Processor has built-in stack support: called hardware or run-time stack dedicated pointer register: SP

• some instructions use run-time stack implicitly via SP stack holds 16-bit values grows “down” in memory (high-to-low addresses)

(Built-In) Stack Operations:PUSH operand adds a new item at top of stack must specify 16-bit source operand operand may be register or memory grows “down”effective execution:

SP := SP – 2 // adjust pointer mem[SP] := operand// copy value to top

Stacks: p86 Stack


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POP operand removes item from top of stack must specify 16-bit destination operand operand may be register or memoryeffective execution:

operand := mem[SP] // copy value to topSP := SP + 2 // adjust pointer

“Read” an item from stack: must index from top [SP + constant ] is illegal!!!common solution uses BP

MOV BP, SP ; copy top pointer We know access using [BP + constant] is legal could use any of BP, BX, SI, DI

Stacks: p86 Stack (Continued)


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Note: Must initialize SP before using stack operations:e.g. MOV SP, 0FFFEH

Example: suppose need to save registers: PUSH AX

PUSH BXPUSH CX

now … to access saved AX value:could POP values off until AX value reached, OR:

MOV BP, SP

+2MOV … , [ BP + 4 ] ; read saved AX +4

Stacks: p86 Stack (Continued)

AX value

BX value

CX value

SP

AX value

BX value

CX value

SP

BP

AX value

BX value

CX value

SP

BP


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Stack Addressing

Operand is (implicitly) on top of stack e.g. Z=X+Y

• PUSH X

• PUSH Y

• ADD Pop top two items from stackand add, Push result on stack

• POP ZNo stack

addressing in Virgo


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Subroutines Often need to perform the same program activity many times High-level language: function, procedure, method Assembly language: subroutine Want ability to:

• encapsulate program activity in program text

• invoke the activity from elsewhere in program Control flow

• pass control to the activity

• execute the activity

• return control to the invocation point


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Subroutine CALL and RET During invocation: must save invocation point information During return: must return to saved invocation point Machine-level implementation mechanisms:

• CALL target (invoke target subroutine)

PUSH IP save return address on run-time stack

JMP target pass control to activity• RET (return from subroutine)

POP IP return to pushed address

IP value AFTER fetching CALL instruction!


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CALL activity (after fetch IP = = Next) PUSH IP JMP activityafter execution IP = = activity

Stack

program

CALL activityNext:

activity:

RET

RET POP IPafter execution IP = = Next

Stack

SP Next

old topN.B. only works if return address is on top of stack when RET is executed

--responsibility of subroutine!!

SP Next

old top


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Nested Subroutine Callsprogram

CALL Next1:

activity1: CALLNext2:

RET

activity2:

RET

old topNext1

old top

Next2Next1

old top

Run-TimeStack


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Subroutine Parameters Parameters:

• increase the generality of an activity• allow invocations to behave differently• allows caller (the code that invokes) and callee (the

invoked activity) to communicate information Example: could have a dedicated subroutine that displays the

value 245 void Display245( ); nice, but .....

• could generalize by adding a parameter• allow a 16-bit value to be displayed to be communicated at

invocationvoid DisplaySigned( word Value );


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Subroutine Parameters (contd) could further generalize by adding another parameter to communicate the base for displaying Value

void Display16( word Value, byte Base);

(Base- 0 : binary, 1 : hex, 2 : decimal) text of function/subroutine is static – write in terms of parameters behaviour of each invocation is dynamic – depends on arguments –

the actual parameter values passed to specific invocations parameters can be communicated in various ways:

• global variables

• registers

• on the stack common POLICY for high-level languages


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Global Variable A shared (static) memory variable to communicate invocation argument:

• caller: puts argument value in variable, then calls• callee: reads argument from variable• Example:

MOV WORD PTR [Value], 245CALL activity. . .

activity: MOV AX, [Value]. . .RET

Value: DW

Caller

Callee

Global variable


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Global Variables

not widely used in practice problems in large programs – software engineering issues in SYSC 2003:

• turns out to be essential

• only way to communicate in some cases


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Subroutine Parameter Passing

Via Registers:

• could exchange arguments in registers

• caller: load registers with values

• callee: read values from registers

• used in assignments 4 and 5

• OK, but ... finite number of registers

• what to do if more parameters than registers? Via the Run-Time Stack

• caller: push invocation arguments onto stack

• callee: indexes into stack to access arguments

sysc 2001*: copyright ©t. pearce, d. hutchinson, l. marshall nov. 2002 virgo lectures- revised nov....

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