system c usage tutorial

8/12/2019 System C Usage Tutorial

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SystemC Tutorial

Author: Silvio Veloso

[email protected]


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Contents

Needed tools Starting example

Introduction

SystemC highlights

Differences

Modules, processes, ports, signals, clocksand data types


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Needed tools

SystemC library package v2.0.1Download in www.systemc.org

Linux platform

GCC compiler GTKWave Waveform tool

some text editor


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Starting Example:Full Adder

SC_MODULE( FullAdder ) {

sc_in< sc_uint > A;sc_in< sc_uint > B;

void FullAdder::doIt( void ) {

sc_int tmp_A, tmp_B;sc_int tmp_R;

FullAdder.h FullAdder.cpp

_ _

void doIt( void );

SC_CTOR( FullAdder ) {

SC_METHOD( doIt );sensitive


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Introduction

What is SystemC ? SystemC is a C++ class library and methodology

that can effectively be used to create a cycle-

software, hardware and their interfaces.


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SystemC highlights

Supports hardware and software co-design Developing an executable specification

avoids inconsistency and errors

vo s wrong n erpre a on o especification

SystemC has a rich set of data types foryou to model your systems

It allows multiple abstraction levels, fromhigh level design down to cycle-accurateRTL level


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Why is SystemC different ?

Current design methodology

Manual conversion creates errors The C model is not more used

Many tests are needed to validate


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Why is SystemC different ?

SystemC design methodology

Better methodology, translate is not necessaryWritten in only one language


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Modules

Modules are the basic building blocks topartition a design

Modules allow to partition complex

systems in smaller components Modules hide internal data representation,

use interfaces

Modules are classes in C++ Modules are similar to entity in VHDL


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Modules

SC_MODULE(module_name){// Ports declaration

// Si nals declaration

// Module constructor : SC_CTOR// Process constructors and sensibility list

// SC_METHOD

// Sub-Modules creation and port mappings

// Signals initialization}

They can contain ports, signals, local data,other modules, processes and constructors.


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Modules

Module constructor Similar to architecture in VHDL

SC_CTOR( FullAdder ) {



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Modules

Sub-modules instantiation:

Instantiate module

Module_type Inst_module (label);

Instantiate module as a pointer

Module_type *pInst_module;

// Instantiate at the module constructor SC_CTOR

pInst_module = new module_type (label);


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Modules

How to connect sub-modules ?

Named Connection or

Positional Connection


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Modules

Named Connection

ns _mo u e.a s ;Inst_module.b(c);Inst_module.q(q);

pInst_module -> a(s);

pInst_module -> b(c);pInst_module -> q(q);


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Modules

Positional Connection

Inst_module


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Modules

Internal Data Storage Local variables: can not be used to

Allowed data types

C++ types

SystemC types User defined types


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Modules

SC_MODULE( Mux21 ) {

sc_in< sc_uint > in1;

sc_in< sc_uint > in2;sc_in< bool > selection;sc_out< sc_uint > out;

SC_CTOR( Mux21 ) {



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Modules

Example:

sample

q

SC_MODULE(filter) {// Sub-modules : componentssample *s1;coeff *c1;

mult *m1;

sc_signal > q, s, c; // Signals

// Constructor : architecture

filterfilter

s1

din dout

c1

coeff

cout

m1

mult

a

q

b

s

c

_

// Sub-modules instantiation andmapping

s1 = new sample (s1);s1->din(q); // named mappings1->dout(s);

c1 = new coeff(c1);c1->out(c); // named mapping

m1 = new mult (m1);(*m1)(s, c, q); // Positional mapping

}}


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Processes

Processes are functions that are identified to theSystemC kernel. They are called if one signal ofthe sensitivity list changes its value.

Processes implement the funcionality of modules

Processes are very similar to a C++ function or

method

Processes can be Methods, Threads and CThreads


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Processes

MethodsWhen activated, executes and returns- SC_METHOD(process_name)

Threads

Can be suspended and reactivated- wait() -> suspends

- one sensitivity list event -> activates

- SC_THREAD(process_name)

CThreadsAre activated in the clock pulse- SC_CTHREAD(process_name, clock value);


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Processes

Type SC_METHOD SC_THREAD SC_CTHREAD

ActivatesExec.

Event in sensit. list Event in sensit. List Clock pulse

SuspendsExec.

NO YES YES

Infinite Loop NO YES YESsuspended/reactivated

by

N.D. wait() wait()wait_until()

Constructor &

Sensibilitydefinition

SC_METHOD(call_back);

sensitive(signals);sensitive_pos(signals);sensitive_neg(signals);

SC_THREAD(call_back);

sensitive(signals);sensitive_pos(signals);sensitive_neg(signals);

SC_CTHREAD(

call_back,clock.pos() );SC_CTHREAD(

call_back,clock.neg());


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Processes

Process Example

Into the .H filevoid Mux21::doIt( void ) {

Into the .CPP file

SC_CTOR( Mux21 ) {



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Ports and Signals

Ports of a module are the external interfaces thatpass information to and from a module

In S stemC one ort can be INOUTor INOUT

Signals are used to connect module portsallowing modules to communicate

Very similar to ports and signals in VHDL


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Ports and Signals

Types of ports and signals:

All natives C/C++ types All SystemC types

How to declare

IN : sc_in OUT : sc_out Bi-Directional : sc_inout


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Ports and Signals

How to read and write a port ?

Methods read( ); and write( );

Examples:

in_tmp = in.read( ); //reads the port in to in_tmp

out.write(out_temp); //writes out_temp in the out port


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Clocks Special object

How to create ?sc_clock clock_name (

clock_label,period, duty_ratio, offset,

initial_value ); Clock connection

f1.clk( clk_signal ); //where f1 is amodule

Clock example:

2 12 22 32 42

sc_clock clock1 ("clock1", 20, 0.5, 2, true);


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Data Types

SystemC supports: C/C++ native types SystemC types

SystemC types Types for systems modelling 2 values (0,1) 4 values (0,1,Z,X) Arbitrary size integer (Signed/Unsigned) Fixed point types


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SystemC types

Simple bit type Assignment similar to char

my_bit = 1;

Declaration bool my_bit;

OperatorsBitwise & (and) | (or) ^ (xor) ~ (not)

Assignment = &= |= ^=

Equality == !=


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SystemC types

SC_LOGIC type

More general than bool, 4 values : (0 (false), 1 (true), X (undefined) , Z(high-impedance) )

my_logic = 0; my_logic = Z;

Simulation time bigger than bool

Operators like bool

Declaration sc_logic my_logic;


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SystemC types

Operators of fixed precision typesBitwise ~ & | ^ >> =

Auto-Inc/Dec ++ --Bit selection [x] ex) mybit = myint[7]

Part select range() ex) myrange = myint.range(7,4)

Concatenation (,) ex) intc = (inta, intb);


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SystemC types

Arbitrary precision integers Integer bigger than 64 bits

sc_bigint

_

More precision, slow simulation

Operators like SC_LOGIC

Can be used together with:

Integer C++ sc_int, sc_uint


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SystemC types

Bit vector

sc_bv 2-value vector (0/1) Not used in arithmetics operations Faster simulation than sc_lv

sc_lv Vector to the sc_logictype

Assignment operator (=) my_vector = XZ01 Conversion between vector and integer (int or uint)

Assignment between sc_bvand sc_lv Additional Operators

Reduction and_reduction() or_reduction() xor_reduction()

Conversion to_string()


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SystemC types

Examples:

sc_bit y, sc_bv x; y = x[6];

sc_bv x, sc_bv y; y = x.range(0,7);

sc_bv databus, sc_logic result; result = databus.or_reduce();

sc_lv bus2; cout


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User defined types

Comparation operatorOperator Built-in == cant be used

function inline must be defined for user

typesinline bool operator == (const packet_type& rhs) const

{

return (rhs.info==info && rhs.seq==seq &&

rhs.retry==retry);}


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User defined types

Example#include "systemc.h"

struct packet_type {

long info;int seq;int retry;

inline bool operator == (const packet_type& rhs) const {

return (rhs.info == info && rhs.seq == seq && rhs.retry == retry);

}};

#endif

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