system demonstration platform user guide · 2019. 10. 12. · a system demonstration platform user...

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System Demonstration PlatformUser Guide

Revision 1.3, February 2011

Part Number82-100110-01

Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106

Copyright Information© 2011 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.

Printed in the USA.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark NoticeThe Analog Devices icon bar and logo, VisualDSP++, Blackfin, EZ-KIT Lite, and EZ-Extender are registered trademarks of Analog Devices, Inc.

EZ-Board is a trademark of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

Regulatory Compliance The EVAL-SDP-CB1Z is designed to be used solely in a laboratory envi-ronment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board should not be used in or near any medical equipment or RF devices.

The EVAL-SDP-CB1Z board has been certified to comply with the essen-tial requirements of the European EMC directive 89/36/EC amended by 93/68/EEC and therefore carries the “CE” mark.

The EVAL-SDP-CB1Z board evaluation system contains ESD (elec-trostatic discharge) sensitive devices. Electrostatic charges readily accu-mulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EVAL-SDP-CB1Z boards in the protective shipping package.

SDP User Guide i

CONTENTS

PREFACE

Product Overview .......................................................................... -iii

Purpose of This Manual ................................................................. -iv

Intended Audience .......................................................................... -v

Manual Contents ............................................................................ -v

What’s New in This Manual ............................................................ -v

Technical or Customer Support ...................................................... -vi

Product Information ...................................................................... -vi

Analog Devices Web Site .......................................................... -vi

Notation Conventions ................................................................... -vii

GETTING STARTED

Package Contents .......................................................................... 1-1

PC Configuration ......................................................................... 1-2

USB Installation ........................................................................... 1-2

Installing the Software ............................................................. 1-3

Connecting the SDP Board to the PC ...................................... 1-3

Verifying Driver Installation .................................................... 1-3

Powering Up/Down the SDP ......................................................... 1-5

Contents

ii SDP User Guide

Powering Up the SDP Board ................................................... 1-5

Powering Down the SDP Board ............................................... 1-5

HARDWARE DESCRIPTION

LEDs ........................................................................................... 2-1

POWER LED (LED2) ............................................................ 2-1

LED 1 .................................................................................... 2-2

Connector Details ........................................................................ 2-2

Connector Pin Assignments ..................................................... 2-3

Pin Sharing ........................................................................... 2-10

Power ......................................................................................... 2-11

Daughter Board Design Guidelines ............................................. 2-11

Connector Location .............................................................. 2-11

Keep Out Area ...................................................................... 2-14

Restriction on Right Angle Connectors .................................. 2-14

Mechanical Specifications ........................................................... 2-14

SCHEMATIC

SDP User Guide iii

PREFACE

Thank you for purchasing the EVAL-SDP-CB1Z System Demonstration Platform (SDP) from Analog Devices, Inc. The SDP is used as part of the evaluation system for many ADI components.

The SDP board is designed to be used in conjunction with various ADI component evaluation boards as part of a customer evaluation environ-ment. The SDP provides USB connectivity through a USB 2.0 high speed connection to the computer allowing users to evaluate components on this platform from a PC application. The SDP is based on ADSP-BF527 Blackfin processor, with the Blackfin processor peripheral communication lines available to the component daughter board through the two identical 120-pin small footprint connectors

Product OverviewThe board features:

• Analog Devices ADSP-BF527 Blackfin processor

• Core performance up to 600 MHz

• 208 -ball CSP-BGA package

• 24 MHz CLKIN oscillator

• 5 Mb of internal RAM memory

Purpose of This Manual

iv SDP User Guide

• 32Mb flash memory

• Numonyx M29W320EB or

• Numonyx M25P32

• SDRAM memory

• Micron MT48LC16M16A2P-6A - 16 Mb x 16 bits (256 Mb/32 MB)

• 2 x 120-pin small foot print connectors

• Hirose FX8 -120P-SV1(91),120 Pin Header

• Blackfin processor peripherals exposed

• SPI

• SPORT

• TWI/I2C

• GPIO

• PPI

• Asynchronous Parallel

For more information, go to http://www.analog.com/sdp.

Purpose of This ManualThe SDP User Guide provides instructions for installing the SDP hardware (EVAL-SDP-CB1Z board) and software onto your computer. The neces-sary installation files are provided with the evaluation daughter board package.

http://www.analog.com/sdp

SDP User Guide v

Preface

Intended AudienceThe primary audience for this manual is a system engineer who seeks to understand how to set up the SDP board and begin USB communications to the computer.

Manual ContentsThe manual consists of:

• Chapter 1, “Getting Started” on page 1-1Provides software and hardware installation procedure, PC system requirements and basic board information.

• Chapter 2, “Hardware Description” on page 2-1Provides information on the EVAL-SDP-CB1Z components.

• Chapter 3, “Schematic” on page 3-1Provides EVAL-SDP-CB1Z schematics.

What’s New in This ManualRevision 1.3 of the SDP User Guide revises the document’s name to “Sys-tem Demonstration Platform User Guide”.

Technical or Customer Support

vi SDP User Guide

Technical or Customer SupportYou can reach Analog Devices, Inc. Customer Support in the following ways:

• Visit the SDP Web site athttp://www.analog.com/sdp

• E-mail processor questions [email protected] (World wide support)

[email protected] (Europe support)

[email protected] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized distributor

• Send questions by mail to:Analog Devices, Inc.

One Technology Way

P.O. Box 9106

Norwood, MA 02062-9106

USA

Product InformationProduct information can be obtained from the Analog Devices Web site.

Analog Devices Web SiteThe Analog Devices Web site, www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.

http://www.analog.com/sdp

mailto:[email protected]



http://www.analog.com

SDP User Guide vii

Preface

Also note, MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest infor-mation about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.

Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your e-mail address.

Notation ConventionsText conventions used in this manual are identified and described as follows.

Example Description

Close command (File menu)

Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close com-mand appears on the File menu).

{this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required.

[this | that] Optional items in syntax descriptions appear within brackets and sepa-rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delim-ited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this.

.SECTION Commands, directives, keywords, and feature names are in text with letter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

http://www.analog.com/subscriptions



Notation Conventions

viii SDP User Guide

Note: For correct operation, ...A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ...Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol.

Example Description

SDP User Guide 1-1

1 GETTING STARTED

This chapter provides specific information to assist you with using the SDP board as part of your evaluation system.

The following topics are covered.

• “Package Contents”

• “PC Configuration”

• “USB Installation”

• “Powering Up/Down the SDP”

Package ContentsYour EVAL-SDP-CB1Z board package contains the following items.

• EVAL-SDP-CB1Z board

• 1m USB Standard-A to mini-B cable

Contact the vendor where you purchased your SDP board or contact Ana-log Devices, Inc. if any item is missing.

PC Configuration

1-2 SDP User Guide

PC ConfigurationFor correct operation of the SDP board, your computer must have the fol-lowing minimum configuration

• Windows XP Service Pack 2 or Windows Vista

• USB 2.0 port

When removing the SDP board from the package, handle the board care-fully to avoid the discharge of static electricity, which can damage some components.

USB InstallationPerform the following tasks to safely install the SDP board onto the computer.

There are two stages in the software application installation procedure. The first installs the application software. The second installs the .NET Framework 3.5 and the necessary drivers.

The SDP board evaluation system contains ESD (electrostatic dis-charge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy dis-charges. Proper ESD precautions are recommended to avoid perfor-mance degradation or loss of functionality. Store unused SDP boards in the protective shipping package.

SDP User Guide 1-3

Getting Started

Installing the Software1. Run the application install provided. The first stage will install the

Applications GUI and necessary support files onto the computer

2. Immediately following the application install, the .NET Frame-work 3.5 and the driver package for the SDP board is installed. If the .NET Framework 3.5 is already pre-installed on the computer in question, this stage will be skipped and step two will consist of a driver package installation only

Connecting the SDP Board to the PC• Attach the SDP board to a USB 2.0 port on the computer via the

Standard-A to Mini-B cable provided.

Verifying Driver InstallationBefore using the SDP board, verify the driver software has installed properly.

• Open the Windows Device Manager and verify the SDP board appears under ADI Development Tools as shown in Figure 1-1.

USB Installation

1-4 SDP User Guide

Figure 1-1. Device Manager

SDP User Guide 1-5

Getting Started

Powering Up/Down the SDPThe following sections describe how to safely power up and down the SDP.

Powering Up the SDP Board1. Connect the SDP board to the daughter evaluation board through

the 120 pin mating connectors.

2. Power the daughter board

3. Connect the USB port on the computer to the SDP board.

Powering Down the SDP Board1. Power down the daughter evaluation board

2. Disconnect the USB port on the computer from the SDP board

3. Disconnect the SDP board from the daughter evaluation board

Powering Up/Down the SDP

1-6 SDP User Guide

SDP User Guide 2-1

2 HARDWARE DESCRIPTION

This chapter describes the hardware design of the EVAL- SDP -CB1Z board.

The following topics are covered.

• “LEDs” — Describes the SDP on board LEDs.

• “Connector Details” — Details the pin assignments on the 120 pin Connectors

• “Power” — Lists power requirements of the SDP and identifies connector power inputs and output pins

• “Daughter Board Design Guidelines” — Provides guidelines regarding how to design daughter boards for use with the SDP

• “Mechanical Specifications” — Provides dimensional information

LEDsThere are two LEDs located on the SDP board. Refer to Figure 2-1.

POWER LED (LED2)The green power LED indicates that the SDP board is powered. This is not an indication of USB connectivity between the SDP and the PC.

Connector Details

2-2 SDP User Guide

LED 1The orange LED is an LED to be used as a diagnostic tool for evaluation application developers.

Connector DetailsThe SDP board contains two identical Hirose FX8-120P-SV1(91), 120 pin header, connectors. Through these connectors, the peripheral communication interfaces of ADSP-BF527 Blackfin processor are exposed. The exposed peripherals are:

• SPI

• SPORT

• I2C/TWI

Figure 2-1. SDP Board LEDs

SDP User Guide 2-3

Hardware Description

• GPIO

• Asynchronous Parallel

• PPI

• UART

• Timers

Also, included on the connector specification are input and output power pins, ground pins, and pins reserved for future use.

For further details on the peripheral interfaces, including timing diagrams, see the ADSP-BF52x Blackfin Processor Hardware Reference.

Connector Pin AssignmentsThe connector pin assignments have been defined independently of the any internal pin sharing, which occurs on the Blackfin processor. Table 2-1 lists the connector pins and identifies the functionality assigned to each connector pin on the SDP board.

Table 2-1. 120 Pin Connector Pin Assignments

Pin No. Pin Name Description

1 VIN Power to SDP board. Requires 200mA @ 4 – 7 Volts.

2 NC No Connect. Leave this pin unconnected. Do not ground.

3 GND Connect to ground plane of board.


5 USB_VBUS Connected directly to the USB +5v Supply.


7 PAR_D23 Parallel Data Bus Bit 23.1 (No connect.)



Connector Details

2-4 SDP User Guide



12 PAR_D14 Parallel Data Bus Bit 14.









21 PAR_RD Asynchronous Parallel Read Strobe.

22 PAR_CS Asynchronous Parallel Chip Select.


24 PAR_A3 Parallel Address Bus Bit 3.


26 PAR_FS3 Synchronous (PPI) Parallel Frame Sync 3.



29 SPORT_DR3 SPORT Data Receive 3.1 (No connect.)

30 SPORT_DR2 SPORT Data Receive 2.1 (No connect.)

31 SPORT_DR1 SPORT Data Receive 1. Secondary SPORT Data into processor.

32 SPORT_DT1 SPORT Data Transmit 1. Secondary SPORT Data from processor.

33 SPORT_DT2 SPORT Data Transmit 2.1 (No connect.)

34 SPORT_DT3 SPORT Data Transmit 3.1 (No connect.)

Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)


SDP User Guide 2-5


35 SPORT_INT SPORT Interrupt. Used to trigger a non-periodic SPORT event.


37 SPI_SEL_B SPI Chip Select B. Use this to control a second device on the SPI bus.

38 SPI_SEL_C SPI Chip Select C. Use this for a third device on the SPI bus.

39 SPI_SEL1/SPI_SS SPI Chip Select 1.2 (See Pin Sharing.) Used to connect to SPI Boot Flash if required. Also used as Chip Select when Blackfin processor is operating as SPI Slave.


41 SDA_1 I2C Data 1.2 (See Pin Sharing.)

42 SCL_1 I2C Data 1.2 (See Pin Sharing.)

43 GPIO0 General Purpose Input/Output.




47 GPIO6 General Purpose Input/Output.2 (See Pin Sharing.)

48 TMR_A Timer A flag pin. Use as first Timer if required.

49 TMR_C Timer C flag pin.1 (No connect.)







56 EEPROM_A0 EEPROM A0. Connect to A0 Address line of the EEPROM




Connector Details

2-6 SDP User Guide


59 UART_RX UART Receive Data.2 (See Pin Sharing.)

60 RESET_IN Active low pin to reset EVAL-SDP-CB1Z board.

61 BMODE1 Boot Mode 1. Pull up with 10k resistor to set SDP to boot from SPI Flash. Enabled on Connector A only.

62 UART_TX UART Receive Data.2 (See Pin Sharing.)










72 TMR_D Timer D flag pin.2 (See Pin Sharing.)

73 TMR_B Timer B flag pin. Use as second Timer if required.

74 GPIO7 General Purpose Input/Output.2 (See Pin Sharing.)





79 SCL_0 I2C Clock 0. Daughter Board EEPROM must be connected to this bus.

80 SDA_0 I2C Data 0. Daughter Board EEPROM must be connected to this bus.



SDP User Guide 2-7



82 SPI_CLK SPI Clock.

83 SPI_MISO SPI Master In, Slave Out Data.

84 SPI_MOSI SPI Master Out, Slave In Data.

85 SPI_SEL_A SPI Chip Select A. Use this to control the first device on the SPI bus.


87 SPORT_TSCLK SPORT Transmit Clock.

88 SPORT_DT0 SPORT Data Transmit 0. Primary SPORT Data from processor.

89 SPORT_TFS SPORT Transmit Frame Sync.

90 SPORT_RFS SPORT Receive Frame Sync.

91 SPORT_DR0 SPORT Data Receive 0. Primary SPORT Data into processor.

92 SPORT_RSCLK SPORT Receive Clock


94 PAR_CLK Clock for Synchronous Parallel Interface (PPI).





99 PAR_INT Parallel Interrupt. Used to trigger a non-periodic Parallel event.

100 PAR_WR Asynchronous Parallel Write Strobe.








Connector Details

2-8 SDP User Guide

Each interface provided by the SDP is available on unique pins of the SDP’s 120 pin connector. The connector pin numbering scheme is out-line in Figure 2-2.











116 VIO(+3.3V) +3.3V Output. 20mA max current available to power IO voltage on daughter board.





1 Functionality not implemented on the EVAL-SDP-CB1Z.2 Shared across both connectors.



SDP User Guide 2-9


Figure 2-2. 120 Pin Connector Outline

Connector Details

2-10 SDP User Guide

Pin SharingTwo types of pin sharing occur on the SDP board and must be taken into account when using two or more of the connector's peripherals interfaces between a daughter board and the SDP board. The first type is pin sharing that occurs internally in the Blackfin processor. The second type is pin sharing that occurs when a single Blackfin processor output pin is shared across both connector A and connector B.

Internal Blackfin processor pin sharing can restrict the simultaneous avail-ability of peripheral interfaces on a single connector or across both connectors. The Blackfin processor's internal design has multiple signals physically sharing each single output pin. As mentioned previously, the pins on the 120 pin connector were defined independently of this pin sharing. This has the effect of limiting the peripherals which can be used simultaneously on the SDP. A system designer must consult the ADSP-BF52x Blackfin Processor Hardware Reference for the ADSP-BF527 processor to ensure the selected peripherals are available simultaneously and their signals do not share Blackfin processor output pins. An example of this sharing is that the SPORT and PPI peripherals physically share the same Blackfin processor pins. Therefore, these two interfaces cannot be utilized in a single application.

Pin sharing also occurs from certain Blackfin processor output pins to both Connector A and Connector B. The following signals are connected from a single Blackfin processor output pin to both Connector A and Connector B:

• I2C Bus 1, pins 42 and 43

• SCL 0 on I2C Bus 0, pin 79

• GPIO 6 and GPIO 7, pins 47 and 67

• Timer D, pin 72

• UART, pins 59 and 62

SDP User Guide 2-11


PowerThe SDP board requires that any daughter board connected to the SDP board provides the SDP board with 5V @ 200mA. This supply should be made available on Pin 1 (VIN) of the 120 pin connector. This supply is required to power the Blackfin processor, the memory, and the other com-ponents on the SDP Board. The SDP board also provides 3.3V @ 20mA on Pin 116 (VIO_3.3) to connected daughter boards as the VIO voltage for the daughter board. Pin 5 (USB_VBUS) is connected to the +5V line of the USB connector, providing 5V+/- 10% as an output of the SDP board.

Daughter Board Design GuidelinesThe daughter board design guidelines specify the layout, connector posi-tion, keep out areas and dimensions of potential daughter boards. This guidance is to ensure that a daughter board can connect off either Con-nector A or Connector B of the SDP board. Following these guidelines ensures that both connectors on the SDP can have any one of the cata-logue of daughter boards physically attached to the connectors simultaneously.

Connector LocationThe daughter board connector and securing screw holes are to be located in the top left hand corner. This arrangement can be seen for Daughter Board A in Figure 2-3. Note Daughter Board B is the same as A rotated clockwise through 90°. The exact location of the connector from the board's edge is important in order to allow both boards connect at the same time. As can be seen in Figure 2-3, if either board exceeds these dimensions, it is not possible to connect the other. Every effort was made to extend the 5.9mm dimension as large as possible in order to allow space for vias between the connector and the edge of the board. These are abso-

Daughter Board Design Guidelines

2-12 SDP User Guide

lute max dimensions and should not be exceeded. See Figure 2-3 for further details.

Figure 2-3. Maximum Board Dimensions for Connector Placement

5.9mm

3.3mm

3.3mm 5.9mm

Daughter

Board A

Daughter Board B

SDP User Guide 2-13


The full specification drawing for the connector location on the daughter board can be seen in Figure 2-4.

The mating daughter board 120 pin connector is the Hirose FX8-120S-SV(21), 120-pin receptacle, FEC 132-4660, Digikey H1219-ND. Please consult the connector's data sheet for full details on the connector. Note pins 1 to 60 are placed on the left side of the connec-tor and pins 61 to 120 are placed on the right side of the connector.

Figure 2-4. Connector Placement on Compatible Daughter Board

Mechanical Specifications

2-14 SDP User Guide

Keep Out AreaIn order to allow the greatest flexibility for future controller boards, a keepout area is established for components higher that 3mm. The keepout area is 12.65mm wide and extends down the entire left side of the daugh-ter board.

Restriction on Right Angle ConnectorsDue to the close proximity of the edges of daughter boards A and B (seen in Figure 2-3 on page 2-12) right angle connectors are not allowed on the top and left edges of the daughter boards and (if required) should be placed on the right or bottom edges. The phrase "right angle connector" is used to describe any connector that requires the connection to protrude over the edge of the board (for example, right angle SMB or screw terminal)

Mechanical SpecificationsThe mechanical specifications of the SDP board are 2.75" x 2.25" (69.85mm x 27.15mm). The height of the 120 pin connectors from the bottom of the board is approximately 0.152" (3.86 mm). The tallest com-ponent on the top is approximately 0.125" (3.175 mm), and the tallest components on the bottoms are the connectors at approximately 0.152" (3.86 mm). Refer to Figure 2-5.

SDP User Guide 2-15


Figure 2-5. SDP Board Mechanical Specifications

Mechanical Specifications

2-16 SDP User Guide

SDP User Guide 3-1

3 SCHEMATIC

This chapter provides the schematic drawings for the EVAL- SDP -CB1Z board. The schematic pages include:

• System Demonstration Platform—Power

• System Demonstration Platform—Memory

• System Demonstration Platform—Clocks_USB

• System Demonstration Platform—Blackfin_I/O

• System Demonstration Platform—Connector A

• System Demonstration Platform—Connector B

3-2 SDP User Guide

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G12

VDDINT

G13

VDDINT

G14

VDDINT

H14

VDDINT

J14

VDDINT

K14

VDDINT

L14

VDDINT

M14

VDDINT

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VDDINT

P13

VDDINT

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VDDINT

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VDDRTC

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G20

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R20

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L19

VPPOTP

G7

VDDEXT

G8

VDDEXT

G9

VDDEXT

G10

VDDEXT

G11

VDDEXT

H7

VDDEXT

H8

VDDEXT

J7

VDDEXT

J8

VDDEXT

K7

VDDEXT

K8

VDDEXT

L7

VDDEXT

L8

VDDMEM

M7

VDDMEM

M8

VDDMEM

N7

VDDMEM

N8

VDDMEM

P7

VDDMEM

P8

VDDMEM

P9

VDDMEM

P10

VDDMEM

P11

VDDMEM

H20

VROUT

F19

VRSEL

U1-C

ADSP-BF522_3_4_5_6_7_208-BGA

A1

GND

A17

GND

A20

GND

B20

GND

H9

GND

H10

GND

H11

GND

H12

GND

H13

GND

J9

GND

J10

GND

J11

GND

J12

GND

J13

GND

K9

GND

K10

GND

K11

GND

K12

GND

K13

GND

L9

GND

L10

GND

L11

GND

L12

GND

L13

GND

M9

GND

M10

GND

M11

GND

M12

GND

M13

GND

N9

GND

N10

GND

N11

GND

N12

GND

N13

GND

Y1

GND

Y20

GND

U1-D

ADSP-BF522_3_4_5_6_7_208-BGA

1

EN

2

GND

3

IN

4

IN

8

SS

7

SENSE

6

OUT

5

OUT

U3

ADP1706

2.5V

C2

10nF

C5

4.7uF

C4

4.7uF

C6

4.7uF

C7

4.7uF

1

EN

2

GND

3

IN

4

IN

8

SS

7

SENSE

6

OUT

5

OUT

U4

ADP1706

1.2V

C3

10nF

C8

4.7uF

C9

4.7uF

C11

0.1uF

C12

0.1uF

C13

0.1uF

C18

1nF

C19

10nF

C20

0.1uF

C23

0.1uF

C25

0.1uF

C26

0.1uF

C15

0.1uF

C16

0.1uF

C28

10uF

C29

10uF

C30

10uF

C32

10uF

C33

10uF

+

C34

47uF

20%

+

C35

47uF

20%

+

C36

47uF

20%

C22

10nF

C46

0.1uF

C31

0.1uF

C21

1nF

C10

10nF

C14

10nF

C27

10nF

C17

10nF

LED2

GREEN

R11

1k

D5

BAT54

C24

10nF

7

IN

8

IN

6

SD

4

GND

1

OUT

2

OUT

3

OUT

5

NR

U2

ADP3335-LCSP

C1

1nF

+3.3V

VIN

+3.3V

+2.5V

+1.2V

+2.5V

+3.3V

+1.2V

V-UNREG

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32 MByte SDRAM

4MByte Flash

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MICK McCARTHY

14-01-10

** Fit part MT48LC32M16A2P-75:C for 64 MByte SDRAM

* Fit part MT48LC16M16A2P-75:D for 32 MByte SDRAM

V1

DATA15

W1

DATA14

W2

DATA13

Y2

DATA12

W3

DATA11

Y3

DATA10

W4

DATA9

Y4

DATA8

W5

DATA7

Y5

DATA6

W6

DATA5

Y6

DATA4

W7

DATA3

Y7

DATA2

W8

DATA1

Y8

DATA0

V20

ABE1

V19

ABE0

L20

AMS3

M19

AMS2

K19

AMS1

J19

AMS0

P19

ARDY

N20

AOE

M20

ARE

N19

AWE

Y11

ADDR19

W11

ADDR18

Y12

ADDR17

W12

ADDR16

Y13

ADDR15

W13

ADDR14

Y14

ADDR13

W14

ADDR12

Y15

ADDR11

W15

ADDR10

Y16

ADDR9

W16

ADDR8

Y17

ADDR7

W17

ADDR6

Y18

ADDR5

W18

ADDR4

Y19

ADDR3

W19

ADDR2

W20

ADDR1

T19

SRAS

U20

SCAS

T20

SWE

P20

SCKE

K20

CLKOUT

U19

SA10

R19

SMS

U1-A

ADSP-BF522_3_4_5_6_7_208-BGA

2

DQ0

4

DQ1

5

DQ2

7

DQ3

8

DQ4

10

DQ5

11

DQ6

13

DQ7

15

DQML

16

WE

17

CAS

18

RAS

19

CS

20

BA0

21

BA1

22

A10

23

A0

24

A1

25

A2

26

A3

53

DQ15

51

DQ14

50

DQ13

48

DQ12

47

DQ11

45

DQ10

44

DQ9

42

DQ8

40

N/C

39

DQMH

38

CLK

37

CKE

36

A12

35

A11

34

A9

33

A8

32

A7

31

A6

30

A5

29

A4

U5-A

MT48LC16M16A2P

49

VDD

Q

43

VDD

Q

9

VDD

Q

3

VDD

Q

27

VDD

14

VDD

1

VDD

52

VSSQ

46

VSSQ

12

VSSQ

6

VSSQ

54

VSS

41

VSS

28

VSS

U5-B

MT48LC16M16A2P

D4

A19

C3

A18

B2

A17

E6

A16

D6

A15

C6

A14

A6

A13

B6

A12

D5

A11

C5

A10

A5

A9

B5

A8

A2

A7

C2

A6

D2

A5

B1

A4

A1

A3

C1

A2

D1

A1

E1

A0

G6

DQ15

F5

DQ14

G5

DQ13

F4

DQ12

G3

DQ11

F3

DQ10

G2

DQ9

F2

DQ8

E5

DQ7

H5

DQ6

E4

DQ5

H4

DQ4

H3

DQ3

E3

DQ2

H2

DQ1

E2

DQ0

F6

BYTE

G4

VCC

C4

NC

H6

VSS

H1

VSS

D3

A20

A3

RB

B3

VPP/

WP

B4

RP

A4

W

G1

G

F1

E

U6

M29W320EBZE

C40

0.1uF

C37

0.1uF

1

2

4

U7

NC7S00

1

2

4

U8

NC7S08

1

2

4

U9

NC7S08

1

2

4

U10

NC7S08

C41

0.1uF

C43

0.1uF

C44

0.1uF

C48

0.1uF

C49

0.1uF

15

IN

16

S1A

1

S1B

2

D1

3

S2A

4

S2B

5

D2

6

GND

7

D3

8

S3B

9

S3A

10

D4

11

S4B

12

S4A

13

EN

14

VDD

U12

ADG774A_LFCSP

10

COM

5

COM

9

RH

8

RG

7

RF

6

RE

4

RD

3

RC

2

RB

1

RA

R40

RES-RNA310

100k

C50

0.1uF

C51

0.1uF

R34-A

33r

R34-B

33r

R34-C

33r

R34-D

33r

R34-E

33r

R34-F

33r

R34-G

33r

R34-H

33r

R35-A

33r

R35-B

33r

R35-C

33r

R35-D

33r

R35-E

33r

R35-F

33r

R35-G

33r

R35-H

33r

R36-H

33r

R36-G

33r

R36-F

33r

R36-E

33r

R36-D

33r

R36-C

33r

R36-B

33r

R36-A

33r

R37-H

33r

R37-G

33r

R37-F

33r

R37-E

33r

R37-D

33r

R37-C

33r

R37-B

33r

R37-A

33r

R38-H

33r

R38-G

33r

R38-F

33r

R38-A

33r

R38-B

33r

R39-A

33r

R39-C

33r

R39-G

33r

R38-C

33r

R39-B

33r

R38-D

33r

R38-E

33r

R39-E

33r

R39-D

33r

R39-F

33r

R39-H

33r

R41

33R

R42

33R

C70

10nF

C71

1uF

1

2

4

U20

NC7S08

+3.3V

A[1:19]

D[0:15]

A[1:19]

A1

D[0:15]

D0

+3.3V

RESET

AWE

ARE

AMS3

AMS2

AMS1

AMS0

AMS0

AMS2

AMS3

AMS1

FLASH_A19

FLASH_A20

FLASH_CS

FLASH_CS

FLASH_A20

FLASH_A19

D[0:15]

A[1:19]

A18

A19

SA10

SA10

SRAS

SCAS

SWE

SCKE

CLKOUT

ABE1

ABE0

SMS

SWE

SCAS

SRAS

SMS

CLKOUT

SCKE

ABE0

ABE1

+3.3V

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A12

A13

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

PG0/

FLAS

H_E

N

+3.3V

CS_A

CS_B

CS_LATCH

+3.3V

ARE

AWE

PAR_RD_WR

SHEET: 3 OF 6

SCALE:

REVISION RECORD

DRAWN:

DATED:

DATED:

CHECKED:

QUALITY CONTROL:

DATED:

DATED:

RELEASED:

COMPANY:

TITLE:

DRAWING NO:

A

B

C

D

DATE:

1

2

3

4

5

6

D

C

B

A

CODE:

SIZE:

REV:

LTR

ECO NO:

APPROVED:

Sets Boot Mode for 8-/16-bit Flash

ESD Diodes

or SPI Flash if BMODE1 pulled high

ANALOG DEVICES

(CLOCKS_USB)


Paddy Duignan

SDP1Z

13-01-09

B

MICK McCARTHY

14-01-10

A14

RTXI

A11

CLKIN

A15

RTX0

C19

CLKBUF

A10

XTAL

U1-I

ADSP-BF522_3_4_5_6_7_208-BGA

W9

BMODE3

Y9

BMODE2

W10

BMODE1

Y10

BMODE0

B18

RESET

B19

NMI

G19

SS/PG

J20

EXT_WAKE

U1-K

ADSP-BF522_3_4_5_6_7_208-BGA

C20

USB_ID

H19

USB_VREF

D20

USB_RSET

A19

USB_XTALIN

E19

USB_VBUS

E20

USB_DP

F20

USB_DM

A18

USB_XTALOUT

U1-B

ADSP-BF522_3_4_5_6_7_208-BGA

C38

0.1uF

4

MR

3

RESET

1

RESET

5

VCC

2

GND

U11

ADM6319

C42

0.1uF

R1

10k

R2

10k

R4

200k

R7

10k

R5

10k

R6

10k

R8

DNP

D3

Y1

24.000MHz

R12

330R

C45

8.2pF

C47

8.2pF

D2

D1

D7

BAT54

L1

C53

0.1uF

1

VBUS

2

D-

3

D+

4

IO

5

GND

6

SHLD

7

SHLD

J1

USB-MINI-B-THRU-HOLE

VIN

RESET

RESET

+3.3V

+3.3V

+3.3V

MR

BMODE1

USB_VBUS

SHEET: 4 OF 6

SCALE:

REVISION RECORD

DRAWN:

DATED:

DATED:

CHECKED:

QUALITY CONTROL:

DATED:

DATED:

RELEASED:

COMPANY:

TITLE:

DRAWING NO:

A

B

C

D

DATE:

1

2

3

4

5

6

D

C

B

A

CODE:

SIZE:

REV:

LTR

ECO NO:

APPROVED:

JTAG

Remove Pin 3 for keying

Will be driven low as soon

as core is ready to boot.

ANALOG DEVICES

(BLACKFIN I/O)


Paddy Duignan

SDP1Z

13-01-09

B

MICK McCARTHY

14-01-10

F1

PF0

E1

PF1

E2

PF2

D1

PF3

D2

PF4

C1

PF5

C2

PF6

B1

PF7

B2

PF8

A2

PF9

B3

PF10

A3

PF11

B5

PF12

A5

PF13

B6

PF14

A6

PF15

U1-E

ADSP-BF522_3_4_5_6_7_208-BGA

R2

PG0

P1

PG1

P2

PG2

N1

PG3

N2

PG4

M1

PG5

M2

PG6

L1

PG7

L2

PG8

K1

PG9

K2

PG10

J1

PG11

J2

PG12

H1

PG13

H2

PG14

G1

PG15

U1-F

ADSP-BF522_3_4_5_6_7_208-BGA

A7

PH0

B7

PH1

A8

PH2

B8

PH3

A9

PH4

B9

PH5

B10

PH6

B11

PH7

A12

PH8

B12

PH9

A13

PH10

B13

PH11

B14

PH12

B15

PH13

B16

PH14

B17

PH15

U1-G

ADSP-BF522_3_4_5_6_7_208-BGA

A4

SCL

B4

SDA

F2

PJ0

G2

PJ1

U1-H

ADSP-BF522_3_4_5_6_7_208-BGA

V2

TCK

R1

TDI

U2

TMS

U1

TRST

T1

TDO

T2

EMU

U1-J

ADSP-BF522_3_4_5_6_7_208-BGA

R3

10k

R9

0R

R10

0R

J3-1

J3-2

J3-3

J3-4

J3-5

J3-6

J3-7

J3-8

J3-9

J3-10

J3-11

J3-12

J3-13

J3-14

R13

4k7

R16

2k2

1

CLR

11

CLK

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

U19

74AHC273

R19

10k

R20

10k

R21

10k

2

4

U21

NC7S04

2

4

U22

NC7S04

19

IN1

1

D1

2

S1

14

S2

15

D2

17

IN2

12

S3

11

D3

9

IN3

4

S4

5

D4

7

IN4

13

VDD

3

GND

U13

ADG782

R17

2k2

J5-1

J5-2

J5-3

J5-4

R18

200k

R23

200k

R24

200k

LED1

YELLOW

R26

1k

15

2

R28-B

33r

16

1

R28-A

33r

2

15

R27-B

33r

4

13

R27-D

33r

6

11

R27-F

33r

8

9

R27-H

33r

8

9

R28-H

33r

7

10

R28-G

33r

5

12

R28-E

33r

3

14

R28-C

33r

16

1

R27-A

33r

14

3

R27-C

33r

12

5

R27-E

33r

10

7

R27-G

33r

R29-B

33r

R29-D

33r

R29-F

33r

R29-H

33r

R30-B

33r

R30-D

33r

R30-F

33r

R30-H

33r

R32-G

33r

R32-E

33r

R32-C

33r

R32-B

33r

R31-A

33r

R31-C

33r

R31-E

33r

R31-G

33r

R32-H

33r

R32-F

33r

R32-D

33r

R32-A

33r

R31-B

33r

R31-D

33r

R31-F

33r

R31-H

33r

C56

0.1uF

C57

0.1uF

C58

0.1uF

C59

0.1uF

R43

33R

R33

33R

R30-G

33r

R30-E

33r

R30-C

33r

R30-A

33r

R29-G

33r

R29-E

33r

R29-C

33r

R29-A

33r

6

11

R28-F

33r

4

13

R28-D

33r

1

2

4

U14

NC7S32

C39

0.1uF

PF1/PPI_D1/RFS0

PF3/PPI_D3/DT0PRI

PF5/PPI_D5/TSCLK0/TACLK1

PF7/PPI_D7/DR0SEC/TACI1

PF9/PPI_D9/RSCLK1/SPISEL6

PF11/PPI_D11/TFS1/CZM

PF13/PPI_D13/TSCLK1/SPISEL3/CUD

PF15/PPI_D15/DR1SEC/UART1RX/TACI3

PF0/PPI_D0/DR0PRI

PF2/PPI_D2/RSCLK0

PF4/PPI_D4/TFS0/TACLK0

PF6/PPI_D6/DT0SEC/TACI0

PF8/PPI_D8/DR1PRI

PF10/PPI_D10/RFS1/SPISEL7

PF12/PPI_D12/DT1PRI/SPISEL2/COG

PF14/PPI_D14/DT1SEC/UART1TX

PG1/SPISS/SPISEL1

PG3/MISO/DR0SECA

PG5/TMR1/PPI_FS2

PG7/TMR3/DR0PRIA/UART0TX

PG9/TMR5/RSCLK0A/TACI5

PG11/TMR7

PG13/UART1RXA/TACI2

PG15/TFS0A/MII_PHYINT/RMII_MDINT

PG0/FLASH_EN

PG2/SCK

PG4/MOSI/DT0SECA

PG6/DT0PRIA/TMR2/PPI_FS3

PG8/TMR4/RFS0A/UART0RX/TACI4

PG10/TMR6/TSCLK0A/TACI6

PG12/UART1TXA

PG14/TSCLK0A1/MOC

PH0/MII_CRS/RMII_CRSDV

PH2/MDIO

PH4/MII_TXCLK/RMII_REFCLK

PH6/ERXDO

PH8/SPISEL4/ERXD1/TACLK2

PH10/ERXD2

PH12/ERXD3

PH14/ERXDV

PH1/ERXER

PH3/ETXEN

PH5/ETXD0

PH7/ETXD1

PH9/SPISEL5/ETXD2/TACLK3

PH11/ETXD3

PH13/ERXCLK

PH15/COL

PJ2/SCL

JTAG_TDO

JTAG_EMU

JTAG_TCK

JTAG_TDI

JTAG_TMS

JTAG_TRST

+3.3V

JTAG_EMU

JTAG_TMS

JTAG_TCK

JTAG_TRST

JTAG_TDI

JTAG_TDO

+3.3V

I2C_SEL_A

SDA_B

SDA_A

RESET

CS_LATCH

D[0:15]

D0

D1

D2

D3

D4

D5

D6

D7

I2C_SEL_A

CONA_PPI_EN

CONA_PPI_DIR

CONB_PPI_EN

CONB_PPI_DIR

+3.3V

+3.3V

I2C_SEL_B

I2C_SEL_C

SDA_C

I2C_SEL_B

I2C_SEL_C

SDA_C

+3.3V

PJ2/SCL

+3.3V

+3.3V

PJ0/PP1_FS1/TMR0

PJ1/PPI_CLK/TMRCLK

AWE

+3.3V

SHEET: 5 OF 6

SCALE:

REVISION RECORD

DRAWN:

DATED:

DATED:

CHECKED:

QUALITY CONTROL:

DATED:

DATED:

RELEASED:

COMPANY:

TITLE:

DRAWING NO:

A

B

C

D

DATE:

1

2

3

4

5

6

D

C

B

A

CODE:

SIZE:

REV:

LTR

ECO NO:

APPROVED:

D[23:16] (Future Use)

PAR_WR

PAR_CS

PAR_INT

PAR_RD

PAR_FS3

PAR_FS2

PAR_FS1

PAR_CLK

PAR_A3

PAR_A2

PAR_A1

PAR_A0

SPORT_RSCLK

SPORT_RFS

SPORT_DR0

SPORT_DR1

SPORT_DR2

SPORT_DR3

SPORT_TSCLK

SPORT_TFS

SPORT_DT0

SPORT_DT1

SPORT_INT

SPORT_DT2

SPORT_DT3

Future Use

Future Use

Future Use

SPI_SEL_A

SPI_SEL_B

SPI_SEL_C

SPI_SEL1/SPI_SS

SPI_CLK

SPI_MISO

SPI_MOSI

SDA_0

SCL_0

SDA_1

SCL_1

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

TMR_A

TMR_B

TMR_C

TMR_D

UART_TX

UART_RX

RESET_IN

BMODE1_A

Future Use

Future Use

Future Use

DIR=1: A->B; DIR=0: B->A

ANALOG DEVICES

(CONNECTOR A)


Paddy Duignan

SDP1Z

13-01-09

B

MICK McCARTHY

14-01-10

J2-1

J2-2

J2-3

J2-4

J2-5

J2-6

J2-7

J2-8

J2-9

J2-10

J2-11

J2-12

J2-13

J2-14

J2-15

J2-16

J2-17

J2-18

J2-19

J2-20

J2-21

J2-22

J2-23

J2-24

J2-25

J2-26

J2-27

J2-28

J2-29

J2-30

J2-31

J2-32

J2-33

J2-34

J2-35

J2-36

J2-37

J2-38

J2-39

J2-40

J2-41

J2-42

J2-43

J2-44

J2-45

J2-46

J2-47

J2-48

J2-49

J2-50

J2-51

J2-52

J2-53

J2-54

J2-55

J2-56

J2-57

J2-58

J2-59

J2-60

J2-61

J2-62

J2-63

J2-64

J2-65

J2-66

J2-67

J2-68

J2-69

J2-70

J2-71

J2-72

J2-73

J2-74

J2-75

J2-76

J2-77

J2-78

J2-79

J2-80

J2-81

J2-84

J2-83

J2-82

J2-85

J2-86

J2-87

J2-89

J2-88

J2-91

J2-90

J2-92

J2-93

J2-94

J2-95

J2-96

J2-97

J2-99

J2-98

J2-100

J2-101

J2-102

J2-103

J2-104

J2-105

J2-106

J2-107

J2-108

J2-109

J2-110

J2-111

J2-112

J2-113

J2-114

J2-115

J2-116

J2-117

J2-118

J2-119

J2-120

R14

0R

A6

1A1

B5

1A2

B6

1A3

C5

1A4

C6

1A5

D5

1A6

D6

1A7

E5

1A8

A1

1B1

B2

1B2

B1

1B3

C2

1B4

C1

1B5

D2

1B6

D1

1B7

E2

1B8

A3

1DIR

A4

1OE

U15-A

74LVCH16245AZRDR

E6

2A1

F5

2A2

F6

2A3

G5

2A4

G6

2A5

H5

2A6

H6

2A7

J6

2A8

E1

2B1

F2

2B2

F1

2B3

G2

2B4

G1

2B5

H2

2B6

H1

2B7

J1

2B8

J3

2DIR

J4

2OE

U15-B

74LVCH16245AZRDR

A6

1A1

B5

1A2

B6

1A3

C5

1A4

C6

1A5

D5

1A6

D6

1A7

E5

1A8

A1

1B1

B2

1B2

B1

1B3

C2

1B4

C1

1B5

D2

1B6

D1

1B7

E2

1B8

A3

1DIR

A4

1OE

U16-A

74LVCH16245AZRDR

E6

2A1

F5

2A2

F6

2A3

G5

2A4

G6

2A5

H5

2A6

H6

2A7

J6

2A8

E1

2B1

F2

2B2

F1

2B3

G2

2B4

G1

2B5

H2

2B6

H1

2B7

J1

2B8

J3

2DIR

J4

2OE

U16-B

74LVCH16245AZRDR

R25

DNP

C54

0.1uF

C55

0.1uF

C60

0.1uF

C61

0.1uF

C66

10nF

C67

10nF

C72

1uF

C73

1uF

D4

BAT54

1

2

4

U23

NC7S32

MR

+3.3V

CONA_PAR_D[0:15]

CONA_PAR_D0

CONA_PAR_D1

CONA_PAR_D2

CONA_PAR_D3

CONA_PAR_D4

CONA_PAR_D5

CONA_PAR_D6

CONA_PAR_D7

CONA_PAR_D8

CONA_PAR_D9

CONA_PAR_D10

CONA_PAR_D11

CONA_PAR_D12

CONA_PAR_D13

CONA_PAR_D14

CONA_PAR_D15

A[1:19]

A1

A2

A3

A4

ARE

AWE


PG5/TMR1/PPI_FS2

PJ0/PP1_FS1/TMR0

PJ1/PPI_CLK/TMRCLK

PG2/SCK

PG3/MISO/DR0SECA

PG4/MOSI/DT0SECA

PG1/SPISS/SPISEL1

PH7/ETXD1

PH6/ERXDO

PJ0/PP1_FS1/TMR0



PF2/PPI_D2/RSCLK0

PF1/PPI_D1/RFS0


PF0/PPI_D0/DR0PRI




PF3/PPI_D3/DT0PRI

PG11/TMR7

PH8/SPISEL4/ERXD1/TACLK2



PH0/MII_CRS/RMII_CRSDV

PH1/ERXER

PH2/MDIO

PH3/ETXEN

PH4/MII_TXCLK/RMII_REFCLK

PH5/ETXD0


PG5/TMR1/PPI_FS2

PG9/TMR5/RSCLK0A/TACI5

BMODE1

SDA_A

PJ2/SCL

CS_A

CONA_PAR_D[0:15]

D[0:15]

PF0/PPI_D0/DR0PRI

PF1/PPI_D1/RFS0

PF2/PPI_D2/RSCLK0

PF3/PPI_D3/DT0PRI





PF8/PPI_D8/DR1PRI








CONA_PAR_D0

CONA_PAR_D1

CONA_PAR_D2

CONA_PAR_D3

CONA_PAR_D4

CONA_PAR_D5

CONA_PAR_D6

CONA_PAR_D7

CONA_PAR_D8

CONA_PAR_D9

CONA_PAR_D10

CONA_PAR_D11

CONA_PAR_D12

CONA_PAR_D13

CONA_PAR_D14

CONA_PAR_D15

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

ARE

CONA_PPI_EN

CONA_PPI_DIR

CONA_PAR_D0

CONA_PAR_D1

CONA_PAR_D2

CONA_PAR_D3

CONA_PAR_D4

CONA_PAR_D5

CONA_PAR_D6

CONA_PAR_D7

CONA_PAR_D8

CONA_PAR_D9

CONA_PAR_D10

CONA_PAR_D11

CONA_PAR_D12

CONA_PAR_D13

CONA_PAR_D14

CONA_PAR_D15

PG12/UART1TXA

PG10/TMR6/TSCLK0A/TACI6

PG0/FLASH_EN

USB_VBUS

+3.3V

+3.3V

+3.3V

+3.3V

V-UNREG

VIN

CS_A

PAR_RD_WR

SHEET: 6 OF 6

SCALE:

REVISION RECORD

DRAWN:

DATED:

DATED:

CHECKED:

QUALITY CONTROL:

DATED:

DATED:

RELEASED:

COMPANY:

TITLE:

DRAWING NO:

A

B

C

D

DATE:

1

2

3

4

5

6

D

C

B

A

CODE:

SIZE:

REV:

LTR

ECO NO:

APPROVED:

Future Use

Future Use

BMODE1_B

RESET_IN

UART_RX

UART_TX

TMR_D

TMR_C

TMR_B

TMR_A

GPIO_7

GPIO_6

GPIO_5

GPIO_4

GPIO_3

GPIO_2

GPIO_1

GPIO_0

SCL_1

SDA_1

SCL_0

SDA_0

SPI_MOSI

SPI_MISO

SPI_CLK

SPI_SEL1/SPI_SS

SPI_SEL_C

SPI_SEL_B

SPI_SEL_A

Future Use

Future Use

SPORT_DT3

SPORT_DT2

SPORT_INT

SPORT_DT1

SPORT_DT0

SPORT_TFS

SPORT_TSCLK

SPORT_DR3

SPORT_DR2

SPORT_DR1

SPORT_DR0

SPORT_RFS

SPORT_RSCLK

PAR_A0

PAR_A1

PAR_A2

PAR_A3

PAR_CLK

PAR_FS1

PAR_FS2

PAR_FS3

PAR_RD

PAR_INT

PAR_CS

PAR_WR

D[23:16] (Future Use)

Future Use

Future Use

DIR=1: A->B; DIR=0: B->A

ANALOG DEVICES

(CONNECTOR B)


Paddy Duignan

SDP1Z

13-01-09

B

MICK McCARTHY

14-01-10

J4-1

J4-2

J4-3

J4-4

J4-5

J4-6

J4-7

J4-8

J4-9

J4-10

J4-11

J4-12

J4-13

J4-14

J4-15

J4-16

J4-17

J4-18

J4-19

J4-20

J4-21

J4-22

J4-23

J4-24

J4-25

J4-26

J4-27

J4-28

J4-29

J4-30

J4-31

J4-32

J4-33

J4-34

J4-35

J4-36

J4-37

J4-38

J4-39

J4-40

J4-41

J4-42

J4-43

J4-44

J4-45

J4-46

J4-47

J4-48

J4-49

J4-50

J4-51

J4-52

J4-53

J4-54

J4-55

J4-56

J4-57

J4-58

J4-59

J4-60

J4-61

J4-62

J4-63

J4-64

J4-65

J4-66

J4-67

J4-68

J4-69

J4-70

J4-71

J4-72

J4-73

J4-74

J4-75

J4-76

J4-77

J4-78

J4-79

J4-80

J4-81

J4-84

J4-83

J4-82

J4-85

J4-86

J4-87

J4-89

J4-88

J4-91

J4-90

J4-92

J4-93

J4-94

J4-95

J4-96

J4-97

J4-99

J4-98

J4-100

J4-101

J4-102

J4-103

J4-104

J4-105

J4-106

J4-107

J4-108

J4-109

J4-110

J4-111

J4-112

J4-113

J4-114

J4-115

J4-116

J4-117

J4-118

J4-119

J4-120

R15

DNP

A6

1A1

B5

1A2

B6

1A3

C5

1A4

C6

1A5

D5

1A6

D6

1A7

E5

1A8

A1

1B1

B2

1B2

B1

1B3

C2

1B4

C1

1B5

D2

1B6

D1

1B7

E2

1B8

A3

1DIR

A4

1OE

U17-A

74LVCH16245AZRDR

E6

2A1

F5

2A2

F6

2A3

G5

2A4

G6

2A5

H5

2A6

H6

2A7

J6

2A8

E1

2B1

F2

2B2

F1

2B3

G2

2B4

G1

2B5

H2

2B6

H1

2B7

J1

2B8

J3

2DIR

J4

2OE

U17-B

74LVCH16245AZRDR

A6

1A1

B5

1A2

B6

1A3

C5

1A4

C6

1A5

D5

1A6

D6

1A7

E5

1A8

A1

1B1

B2

1B2

B1

1B3

C2

1B4

C1

1B5

D2

1B6

D1

1B7

E2

1B8

A3

1DIR

A4

1OE

U18-A

74LVCH16245AZRDR

E6

2A1

F5

2A2

F6

2A3

G5

2A4

G6

2A5

H5

2A6

H6

2A7

J6

2A8

E1

2B1

F2

2B2

F1

2B3

G2

2B4

G1

2B5

H2

2B6

H1

2B7

J1

2B8

J3

2DIR

J4

2OE

U18-B

74LVCH16245AZRDR

C62

0.1uF

C63

0.1uF

C64

0.1uF

C65

0.1uF

C68

10nF

C69

10nF

C74

1uF

C75

1uF

D6

BAT54

1

2

4

U24

NC7S32

A4

A3

A2

A1

CONB_PAR_D15

CONB_PAR_D14

CONB_PAR_D13

CONB_PAR_D12

CONB_PAR_D11

CONB_PAR_D10

CONB_PAR_D9

CONB_PAR_D8

CONB_PAR_D7

CONB_PAR_D6

CONB_PAR_D5

CONB_PAR_D4

CONB_PAR_D3

CONB_PAR_D2

CONB_PAR_D1

CONB_PAR_D0



PJ0/PP1_FS1/TMR0

PH6/ERXDO

PH7/ETXD1

PG1/SPISS/SPISEL1

PG4/MOSI/DT0SECA

PG3/MISO/DR0SECA

PG2/SCK

PJ1/PPI_CLK/TMRCLK

PJ0/PP1_FS1/TMR0

PG5/TMR1/PPI_FS2


AWE

ARE

+3.3V

MR

CONB_PAR_D[0:15]

A[1:19]




PF8/PPI_D8/DR1PRI





PG14/TSCLK0A1/MOC

PH9/SPISEL5/ETXD2/TACLK3



PH10/ERXD2

PH11/ETXD3

PH12/ERXD3

PH13/ERXCLK

PH14/ERXDV

PH15/COL



PG13/UART1RXA/TACI2

BMODE1

SDA_B

PJ2/SCL

CS_B

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CONB_PAR_D15

CONB_PAR_D14

CONB_PAR_D13

CONB_PAR_D12

CONB_PAR_D11

CONB_PAR_D10

CONB_PAR_D9

CONB_PAR_D8

CONB_PAR_D7

CONB_PAR_D6

CONB_PAR_D5

CONB_PAR_D4

CONB_PAR_D3

CONB_PAR_D2

CONB_PAR_D1

CONB_PAR_D0

CONB_PAR_D15

CONB_PAR_D14

CONB_PAR_D13

CONB_PAR_D12

CONB_PAR_D11

CONB_PAR_D10

CONB_PAR_D9

CONB_PAR_D8

CONB_PAR_D7

CONB_PAR_D6

CONB_PAR_D5

CONB_PAR_D4

CONB_PAR_D3

CONB_PAR_D2

CONB_PAR_D1

CONB_PAR_D0

CONB_PPI_DIR

CONB_PPI_EN

ARE








PF8/PPI_D8/DR1PRI





PF3/PPI_D3/DT0PRI

PF2/PPI_D2/RSCLK0

PF1/PPI_D1/RFS0

PF0/PPI_D0/DR0PRI

CONB_PAR_D[0:15]

D[0:15]

PG12/UART1TXA

PG15/TFS0A/MII_PHYINT/RMII_MDINT

USB_VBUS

+3.3V

+3.3V

+3.3V

+3.3V

V-UNREG

VIN

CS_B

PAR_RD_WR

system demonstration platform user guide · 2019. 10. 12. · a system demonstration platform user...

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