20170622_SOCMore Deeply !
¾ FPGA prototyping ¾
• Circuit design ¾ Analog, digital, memory, power regulator, MEMS, … ¾
• Computer-aided design or EDA ¾ Design automation, synthesis, simulation, verification ¾
System Design • System prototype on FPGA
Input TP
TPGamma sRGB
PART A
host_reg_sys I2C
Reference
SoC Design Challenges • In 2007, feature size » 65 nm, µP frequency » 5 GHz, die
size » 600 mm2, µP transistor count per chip » 500M, wiring level » 9 layers, supply voltage » 0.9 V, power consumption » 170 W. ¾ Chip complexity
n Effective design and verification methodology? More efficient optimization algorithms? Time-to-market?
¾ Power consumption n Power & thermal issues?
¾ Supply voltage n Signal integrity (noise, IR drop, etc)?
¾ Feature size, dimension n Sub-wavelength lithography (impacts of process variation)?
noise? wire coupling? reliability? manufacturability? 3D layout? ¾ Frequency
n Interconnect delay? electromagnetic field effects? timing closure? 11
Computer-Aided Design (CAD) • Design Flow
Design Entry VHDL Verilog
Test Bench VHDL Verilog
Synthesis Design Compiler (Synopsys) Ambit (Cadence)
Scan Synthesis DFT Compiler (Synopsys) Turbo Scan (Syntest) DFT - Fast Scan (Mentor)
Design Entry
Technology Simulation
Library
Code Coverage
Design Implementation -- RTL
Design Verification -- RTL
Scan Synthesis DFT Compiler (Synopsys) Turbo Scan (Syntest) DFT - Fast Scan (Mentor)
Design Entry
Formal Verification LEC (Cadence) Formality (Synopsys)
Design Entry
Golden RTL
Timing Verification
PrimeTime (Synopsys)
Gate Simulation
Power Optimization
SOC Encounter (Cadence) Astro (Synopsys)
Design Verification – Gate Level
Formal Verification LEC (Cadence) Formality (Synopsys)
Design Entry Gate Level Netlist (After APR)
Phantom Layout (After APR)
Timing Verification
PrimeTime (Synopsys)
Gate Power Analysis
Design Entry
Design Entry
SOC






SOC