systemc language fundamentals

SystemC Language Fundamentals

Version 12.2 Rev 19.09.02

Lab Manual November 12, 2019

ii Cadence Design Systems, Inc. 11/12/2019

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11/12/2019 Cadence Design Systems, Inc. iii

Table of Contents

SystemC Language Fundamentals

Module 1: About This Course

Lab 1-1 Locating Cadence Online Support Solutions ........................................................... 1-1

Module 2: SystemC Introduction

Lab 2-1 The SystemC Installation ............................................................................................ 2-1

Module 3: SystemC Basics

Lab 3-1 SystemC Module Construction ................................................................................... 3-1

Module 4: Data Types and Operators

Lab 4-1 User-Defined Data Structures ..................................................................................... 4-1

Module 5: Processes and Events

Lab 5-1 Method and Thread Processes ................................................................................... 5-1

Module 6: Interfaces, Channels, and Ports

Lab 6-1 Hierarchical Channels ................................................................................................. 6-1

Module 7: SystemC Event Scheduler

Lab 7-1 SystemC Event Scheduling ........................................................................................ 7-1

Module 8: Building and Using Primitive Channels

Lab 8-1 Primitive Channels ....................................................................................................... 8-1

Module 9: Building and Refining Hierarchical Channels

Lab 9-1 Channel Refinement .................................................................................................... 9-1

Module 10: Querying the Simulator

Lab 10-1 Hierarchy Walker Application ................................................................................... 10-1

Module 11: Debugging SystemC

Lab 11-1 Debugging SystemC .................................................................................................. 11-1

Module 1: About This Course

About This Course

11/12/2019 SystemC Language Fundamentals 1-3

Lab 1-1 Locating Cadence Online Support Solutions

Objective: Log in to Cadence online support and search for information about a specific issue.

To do this lab requires access to the internet and a Cadence online support account. As an

alternative, your instructor might be able to demonstrate this lab for you.

1. In a web browser enter

http://support.cadence.com

2. Log in to Cadence online support with your email and password.

The online support home page appears.

3. In the Search field enter:

VCD for Verilog modules instantiated in SystemC

and select the SEARCH button. A window containing the search results opens.

Note: In the search results, on the left see the ways that you can filter the results,

such as by platform, product, and feature.

4. In the search results, select the match titled:

How to generate VCD files for verilog modules that are instantiated in SystemC

This opens a new tab or window describing the problem and the solution.

Read a little bit about the problem and solution.

5. Close the solution tab or window.

http://support.cadence.com/

http://support.cadence.com/

Module 2: SystemC Introduction

Lab 2-1 The SystemC Installation


Lab 2-1 The SystemC Installation

Objective: Examine and test the SystemC installation.

Do this lab in the lab02-intro directory.

This directory is initially empty.

For this lab, you examine and test the SystemC installation, and optionally do the SystemC

Simulation Tutorial.

Verify Your Environment Variables

The Cadence execution wrapper xrun sets most variables as needed. The user must set two

environment variables.

1. Verify the values of two environment variables that the scripts cannot set:

a. Enter: echo $CDS_LIC_FILE

5280@licence-server

b. Enter: echo $PATH

Must include: installdir/tools/bin

Examine the Documentation Library

You use the Cadence Help documentation browser to view documentation.

1. Launch the Cadence Help facility; enter in a terminal window:

cdnshelp&

2. Select to search Local Documents for “SystemC” and Filter to “Manuals”.

3. Locate and very briefly examine the following documents.

▪ SystemC Simulation User Guide

▪ SystemC Simulation Reference

▪ SystemC Simulation Tutorial

▪ SystemC Advanced Debugging Tutorial

▪ SystemC Simulation Quick Reference

The SystemC Installation Lab 2-1

2-2 SystemC Language Fundamentals 11/12/2019

Examine the SystemC Examples

The installation provides several SystemC examples. Most provided examples demonstrate

proprietary extensions specific to Cadence SystemC simulation. You can download more vendor-

independent examples from the OSCI web site.

1. Locate the example directory, enter:

ls `cds_root xrun`/tools/systemc/examples/

2. Briefly examine the examples README file.

Execute a SystemC Example

1. Copy the systemc_only example directory to the lab02-intro lab directory.

2. Run your local copy of the systemc_only example; enter:

run_xrun

3. Compare the “golden” results to your results; enter:

diff xmsim.au xmsim.log

You should see no differences.

Optionally do the SystemC Simulation Tutorial

For this section, you do the SystemC Simulation Tutorial. The tutorial model is a drink machine

design (that distributes drinks), and a testbench that controls and tests the drink machine. You follow

the tutorial instructions to debug the design while experiencing the native debugging capabilities of

the Cadence SimVision simulation analysis environment.

1. Locate and open the tutorial instructions (that you just now briefly examined).

2. Follow the tutorial instructions.

Module 3: SystemC Basics

Lab 3-1 SystemC Module Construction



Objective: Construct a SystemC module.

Do this lab in the lab03-lang directory.

This lab directory provides the PNET system described below.

For this lab, you complete the pnet_chan.cpp file defining the PNET channel.

Preview the PNET System

1 unused addr

0 7-bit ASCII char

1 P addr enc[3:0]

0 E operand enc[6:4]

The Personal Network (PNET) is an ultra-local desktop network of up to four character-oriented devices connected in a ring topology.

cpu

chan

Each PNET node has a CPU and a data transceiver channel.

The CPU generates random address / data byte pairs at random times and writes them to the channel. It differentiates the bytes by setting the leftmost bit “1” for an address byte and “0” for a data byte.

The channel encodes the address /data byte pairs and writes them to the network. The encoded pair include a parity bit, an encryption bit, and a 3-bit encryption operand. Encoding preserves the leftmost bit. The channel reads address/data byte pairs from the network and either forwards them, or if the address matches its address, decodes them and writes them to the CPU.

Due to the random timing of the CPUs, all communication between processes occurs through FIFO channels, both at the PNET channel level and at the PNET system level.

SystemC Module Construction Lab 3-1


PNET Node Detail

node

channel P P

P P

cpu

P P

cpu tx fifo

cpu rx fifo

P P net fifo

net fifo

P P

prev node

next node

cpu write proc

cpu read proc

cpu read proc

cpu write proc

net write proc

net read proc

cpu fifo

net fifo



Examine the PNET Source Files

pnet_chan.h,cpp

The PNET channel is a SystemC module with four ports for cpu and network read

and write data, two internal FIFOs to collect cpu and network data, four processes to

read and write cpu and network data, an address attribute, and encode and decode

functions. The cpu read process reads address / data byte pairs through ports from an

external FIFO, encodes them, and depending upon the address, writes them to either

the local cpu data FIFO or the local network data FIFO. The cpu write process reads

address / data byte pairs from the internal cpu FIFO, decodes them, and writes them

through a port to the external cpu FIFO. The counterpart network read and write

processes act similarly, but of course do not encode or decode the bytes.

pnet_cpu.h,cpp

The PNET CPU is a SystemC module with two ports for cpu read and write data, two

processes to write and read cpu data, and an address attribute. The CPU write process

generates random address / data byte pairs, writes them through a port to an external

FIFO, and inserts them into a monitor for later checking. The CPU read process reads

address / data byte pairs through a port from an external FIFO, and erases them from

the monitor.

pnet_node.h,cpp

The PNET node is a SystemC module with two ports for network read and write data,

two local FIFOs for cpu read and write data, a cpu instance, and a channel instance.

The node connects cpu instance ports and channel instance ports through the local

FIFOs for cpu read and write data, and connects channel instance ports to node ports

for network read and write data.

pnet_system.h,cpp

The PNET system is a SystemC module with a parameterizable number of node

instances and FIFOs. The FIFOs communicate net data between the nodes. The

system dynamically allocates nodes and FIFOs, and connects node network data write

and read ports through the FIFOs.

pnet_monitor.h,cpp

The PNET monitor keeps a counter and a data multiset for each node. Its insert()

method inserts a data value and increments the counter. Its erase() method erases a

data value. Its summarize() method displays the number stored and the number erased

and any remaining data values.

sc_main.cpp

This file sets SEED, NODES, VERBOSITY, and TRANSACTIONS global

constants. Its sc_main() function instantiates the PNET system and monitor, sets the

random seed, and starts the simulation.

SystemC Module Construction Lab 3-1


Complete the PNET Channel Description

1. Complete the PNET channel description.

Modify the pnet_chan.cpp file to enter the network read and write methods.

Tip: These methods will be very similar to the cpu read and write methods.

2. Test your PNET channel description.

a. Compile and simulate, enter:

xrun –f xrun_args.txt –sysc

Correct as required until simulation succeeds with all transmitted data received.

Note: Set the VERBOSITY constant in sc_main.cpp to 2 to produce more

verbose diagnostic messages.

b. More thoroughly test the PNET system.

Set the TRANSACTIONS constant in sc_main.cpp to a larger number (1000) and

again compile and simulate. This will more likely detect any clashes or deadlocks

between the nodes.

Module 4: Data Types and Operators

Lab 4-1 User-Defined Data Structures


Lab 4-1 User-Defined Data Structures

Objective: Define and use a data structure.

Do this lab in the lab4-data directory.

This directory provides the completed (and partially modified) PNET system of the previous lab and

an additional test file for the data structure you will define.

For this lab, you define and test a data structure representing the network high / low data bytes, and

then modify the PNET channel to use this structure for all network communication between nodes.

Examine the New and Modified PNET Source Files

pnet_frame.h

The PNET frame is a structure of high / low data bytes that also defines the minimum

operators and methods required of any user data type used with SystemC. You will

later create the corresponding pnet_frame.cpp file.

pnet_frame_test.cpp

This is a separate test for just the PNET frame.

pnet_node.h, pnet_system.h,cpp

Modified to replace the network high / low data bytes with the PNET frame type.

Describe, Test, and Debug the PNET Frame Structure

1. Create the pnet_frame.cpp file defining the operators and methods declared in the

provided pnet_frame.h file.

2. Test just your PNET frame definition by itself (and debug as needed), enter:

xrun pnet_frame.cpp pnet_frame_test.cpp –sysc

Modify, Test, and Debug the PNET Channel

1. Modify files pnet_chan.h and pnet_chan.cpp to replace the network high / low data

bytes with the PNET frame type.

Tip: Compare the previous lab’s pnet_node.h and pnet_system.h/cpp with the

provided modified counterparts in this lab.

2. Test your PNET channel modifications (and debug as needed), enter:


User-Defined Data Structures Lab 4-1


Module 5: Processes and Events

Lab 5-1 Method and Thread Processes



Objective: Convert thread processes to method processes.

Do this lab in the lab5-proc directory.

This directory provides the completed (and partially modified) PNET system of the previous lab.

For this lab, you replace the PNET channel’s SC_THREAD processes with SC_METHOD processes

to the extent practical, thus demonstrating your understanding how these process types differ.

Examine the Modified PNET Source Files

pnet_node.cpp

The cpu FIFO size is increased from 1 to 4. Later discussion explains why.

Discussion Concerning PNET Channel Process Modifications

CPU Read Process

You can make the cpu_read_process() an SC_METHOD process statically sensitive

to the data_written() event finder of the “p_cpu_read” fifo input port (don’t initialize).

Only some pre-specialized ports have event finders. A port needs event “finders”

because at the point the process is made statically sensitive, the port might not yet be

bound to a channel. Local process variables exist only during the process activation,

and as an SC_METHOD process cannot block and thus cannot “step” its execution, it

no longer can verify the address/data sequence, but instead must trust that data[7]

accurately specifies whether an address or data byte. The process likewise cannot

store the address locally, as it cannot then “wait” for the data. It must instead store the

address in a class member variable. Question - why can we not resolve this by making

the address variable “static”? Answer - because a static variable belongs to all

instances of the class, and the PNET system has four nodes that would thus all “own”

the variable. The SC_METHOD cpu_read_process() can safely continue to use a

blocking read on the input fifo, as the process is triggered by a write to the input fifo,

which ensures that data is available when the process activates. The process should

now use non-blocking writes (nb_write()) to the local cpu fifo and net fifo, and wrap

those writes within sc_assert(expression) macros to provide a more useful error

indication if the write fails. You must increase the size of these local fifos from 1 to 2,

as two processes write to them, and the cpu_read_process() process now cannot wait

if another process has already filled a fifo.

Method and Thread Processes Lab 5-1


CPU Write Process

You can with a bit more challenge make the cpu_write_process() an SC_METHOD

process statically sensitive to the data_written_event() of the local cpu fifo (don’t

initialize). You need to resolve issues with both the process input fifo and the process

output fifo. The SC_METHOD cpu_write_process() can safely continue to use a

blocking read on the input fifo, as the process is triggered by a write to the input fifo,

which ensures that data is available when the process activates. The process should

now use non-blocking writes to the output fifo, and wrap those writes within

sc_assert() macros to provide a more useful error indication if the write fails.

▪ The first issue is with the local cpu fifo. The cpu_read_process() and

net_read_process() processes both write to the local cpu fifo. Both processes can

write the fifo in the same evaluate phase, but the cpu_write_process() can be

notified only once per evaluate phase, thus backing up transactions in the fifo.

You can resolve this issue by looping the cpu_write_process() process while the

cpu fifo num_available() method indicates that the fifo still has data available.

▪ The second issue is with the output fifo located in the parent node. As the

SC_METHOD cpu_write_process() process cannot consume time, it must write

both the address and the data bytes to the output fifo without potentially waiting

for a full fifo, thus the fifo size must be increased to 4 (already done) to

accommodate the address and data from two frames.

Net Read Process

You can make the net_read_process() an SC_METHOD process statically sensitive to

the data_written() event finder of the “p_net_read” fifo input port. The SC_METHOD

net_read_process() can safely continue to use a blocking read on the input fifo, as the

process is triggered by a write to the input fifo, which ensures that data is available

when the process activates. The process should now use non-blocking writes to the

local “cpu_fifo” and “net_fifo”, and wrap those writes within sc_assert() macros to

provide a more useful error indication if the write fails. At this point, no other issues

with fifos should exist. The input fifo is written by only one process (in the cpu unit)

and the cpu fifo and net fifo that two processes write can now each accommodate two

frames.

Net Write Process

The net_write_process() process has the two fifo-related issues similar to those you

resolved for the cpu_write_process() process. However, the output fifo for the

network interconnect is located at the system level. As you would learn little more by

making this modification, let’s pretend that the project manager has declined to allow

you to modify the system to increase the system network fifo size from 1 to 2. You

can leave this process as a thread process.




1. Modify files pnet_chan.h and pnet_chan.cpp to replace the SC_THREAD processes

with SC_METHOD processes to the extent practical.

Tip: Do this iteratively, one process at a time, and test each new process.



Module 6: Interfaces, Channels, and Ports

Lab 6-1 Hierarchical Channels



Objective: Convert a module to a channel.

Do this lab in the lab6-ifcp directory.


For this lab, you replace the PNET channel’s processes and ports with interface methods, thus

converting the PNET channel to a true SystemC channel.

PNET Node Detail

node

channel

cpu fifo

net fifo

cpu write func

net write func

cpu read func

net read func

cpu

P P

I I

I

cpu write proc

cpu read proc

node connect process

node connect process

I P P

Hierarchical Channels Lab 6-1



pnet_ifs.h

This file declares the cpu and network write and read interfaces.

pnet_cpu.h,cpp

The PNET CPU is modified to replace the input and output ports with generic

SystemC ports specialized for the cpu write and read interfaces. To access the

interface methods implemented in the channel, the generic port utilizes the pointer

operator. The cpu read process now assumes that only data meant for it is provided to

it, so no longer reads the address to verify it.

pnet_node.h,cpp

The PNET node is modified to remove the internal cpu FIFOs and instead connect the

CPU ports directly to the PNET channel. It also replaces its own network fifo input

and output ports with SystemC ports it connects to the channel and through which the

system accesses the network write and read methods implemented by the channel.

pnet_system.h,cpp

The PNET system is modified to replace the FIFO-based node interconnect with a

process between each node pair that endlessly reads a frame from the previous node

and writes it to the next node.




1. Modify files pnet_chan.h and pnet_chan.cpp to convert the module to a channel,

inherit the cpu and network write and read interfaces, remove the ports, and replace

the cpu and network read and write processes with the cpu and network write and

read interface methods.

Tip: The algorithms will not significantly change, but instead of, for example, an

internal process to read cpu data through a port from an external fifo, the

algorithm is a method called by an external process to write cpu data.

Remember that the cpu read method now returns to the cpu only the data byte

and not the address byte.



Module 7: The SystemC Event Scheduler

Lab 7-1 SystemC Event Scheduling


Lab 7-1 SystemC Event Scheduling

Objective: Examine simulation event scheduling.

Do this lab in the lab07-schd directory.

This directory provides the fifo_test.cpp file that instantiates and tests a SystemC FIFO.

For this lab, you examine the behavior of a FIFO channel.

Examine the Test Case

fifo_test.cpp

The test instantiates a SystemC FIFO of size 2 and spawns write and read processes

to write and read 3 elements. It spawns the processes twice, in different order,

separated by 1 ns, to detect any process ordering issues. The writes and reads use

blocking semantics.

Execute the Test Case

1. Execute the FIFO test, enter:

xrun fifo_test.cpp –sysc

Examine the Test Case Output

1. Examine the diagnostic output in the log file:

Writing to a not full FIFO requires how many cycles? ___

Notifying the reader that data has been written requires how many cycles? ___

Reading from a not empty FIFO requires how many cycles? ___

Notifying the writer that data has been read requires how many cycles? ___

Module 8: Building and Using Primitive Channels

Lab 8-1 Primitive Channels


Lab 8-1 Primitive Channels

Objective: Construct and use a primitive channel.

Do this lab in the lab08-pchan directory.

This directory provides the most recently completed (and partially modified) PNET system, a set of

interfaces for a primitive channel that you will complete, and a test of that channel.

For this lab, you create a primitive channel and use it in your PNET channel.

Examine the Interfaces

pnet_sync_ifs.h

This file declares the pnet_sync_write_if and pnet_sync_read_if interfaces. The

interfaces are deliberately similar to the SystemC FIFO interfaces.

Implement and Test the Interfaces

1. Implement the interfaces.

The pnet_sync class template located in the pnet_sync.h file is a SystemC primitive

channel that inherits and implements the interfaces. To simplify the channel, it stores

at most one element. Complete this class template by defining the update() method

that the kernel calls during the update phase of the delta cycle to update the primitive

channel.

▪ If a write is pending, the update() method must do something with the

m_write_pending flag, the m_num_available variable, and the

m_data_written_event event. It must also make the written value available for

reading.

▪ If a read is pending, the update() method must do something with the

m_read_pending flag, the m_num_free variable, and the m_data_read_event

event.

2. Test your primitive channel description.

a. Compile and simulate, enter:

xrun pnet_sync_test.cpp –sysc

Correct as required until the test indicates completion with no error.

Primitive Channels Lab 8-1



1. Modify files pnet_chan.h and pnet_chan.cpp to utilize your pnet_sync primitive

channel instead of the SystemC FIFO for the cpu and network data FIFOs.



Module 9: Building and Refining Hierarchical Channels

Lab 9-1 Channel Refinement



Objective: Refine a hierarchical channel.

Do this lab in the lab09-hchan directory.


For this lab, you replace the PNET channel’s interface methods with processes acting through ports

upon external signal-level channels, thus converting the PNET channel’s transaction-level interface

to a signal-level interface.

PNET Wrapper Detail

wrapper

refined

cpu fifo

net fifo

cpu read proc

cpu write proc

net read proc

net write proc

P P P P P P

P

P

P

P

P

P

net write trans

P

P

P

net read trans

P

P

P

cpu write trans

cpu read trans

P P P P P P

I I

I I

I I I I

data

ready

done

transmit >--->receive

Channel Refinement Lab 9-1



pnet_refined.h

The refined PNET channel is a SystemC module with processes that act through ports

upon external signal channels connected to transactors. To simplify the processes,

they call helper functions to perform the transaction bus protocols. You will complete

the refined channel definition.

pnet_trans.h,cpp

These files declare and define transactor channels that implement the cpu and

network write and read interfaces to convert between transaction-level interfaces and

signal-level-level interfaces.

pnet_wrap.h,cpp

These files declare and define a wrapper channel that implements the cpu and

network write and read interfaces. The wrapper instantiates the refined PNET channel

(with signal-level interfaces), a transactor for each of the cpu and network write and

read interfaces, and signal channels between the transactors and the refined channel.

The wrapper presents the interfaces that the node expects, so can easily replace the

previous unrefined PNET channel.

pnet_cpu.cpp

The PNET CPU is modified to greatly reduce the rate at which transactions are

generated. Now that transactions consume simulation time, the PNET network ring

topology has an inherent potential to become deadlocked. You can reduce the

deadlock potential to zero by maintaining an impractically miniscule mean FIFO

usage. You can reduce the deadlock potential to acceptable limits by maintaining a

reasonable FIFO usage. The mean FIFO usage can increase with FIFO size. The

pnet_sync channel is size one. A reasonable FIFO usage for a FIFO of size one is

perhaps 50%, that is, the cpu should insert new frames at about half the mean rate that

the system can clear them.

pnet_node.h,cpp

The PNET node is modified to instantiate the wrapper channel instead of the

unrefined channel.



Modify, Test, and Debug the Refined PNET Channel

1. Complete the pnet_refined.cpp file by defining the cpu and network read and write

processes and their helper functions.

Tip: The four processes can be very similar to those of the PNET channel of lab 4,

but replace read and write calls to ports with calls to the helper functions.

Remember that the cpu is now expecting only data bytes and no address bytes.

The helper function protocols can be very similar to those of the provided

transactors. Be sure to use correct port names, i.e. the refined channel reads

“tx” data and writes “rx” data.

2. Test your PNET refined channel modifications (and debug as needed), enter:


Module 10: Querying the Simulator

Lab 10-1 Hierarchy Walker Application


Lab 10-1 Hierarchy Walker Application

Objective: Describe the SystemC design object hierarchy.

Do this lab in the lab10-query directory.

This directory provides the completed and unmodified PNET system of the previous lab.

For this lab, you define the hierarchy walker application presented in the training materials.

Examine the New and Modified Files

pnet_walker.h

The PNET hierarchy walker is a SystemC module. It implements a listChildObjects()

method to describe the objects in a passed reference to a vector of SystemC objects. It

implements its inherited start_of_simulation() callback to pass a vector of top-level

SystemC objects to the listChildObjects() method.

sc_main.cpp

The sc_main() function is modified to instantiate the hierarchy walker.

Define and Test the Hierarchy Walker

1. In a new pnet_walker.cpp file, define the hierarchy walker methods. Indent each

object report two additional spaces for each additional level below the top-level

objects. Optionally display vectors between parent and child objects. The first few

lines of the display could look something like this:

system : sc_module

|_system.node_0 : sc_module

| |_system.node_0.cpu : sc_module

| | |_system.node_0.cpu.p_cpu_write : sc_port

| | |_system.node_0.cpu.p_cpu_read : sc_port

| | |_system.node_0.cpu.cpu_write_proc : sc_thread_process

| | |_system.node_0.cpu.cpu_read_proc : sc_thread_process

| |_system.node_0.wrap : sc_module

| |_system.node_0.wrap.cpu_write_trans : sc_module

| | |_system.node_0.wrap.cpu_write_trans.p_cpu_tx_data_value : sc_out

| | |_system.node_0.wrap.cpu_write_trans.p_cpu_tx_data_ready : sc_out

...

Note: To assist with the parent-child vector display, the solution uses a vector of

bool to track whether it has displayed the last element at each level.

2. Test your hierarchy walker, enter:

xrun -f xrun_args.txt -sysc

Module 11: Debugging SystemC

Lab 11-1 Debugging SystemC


Lab 11-1 Debugging SystemC

Objective: Diagnose and correct design operation.

Do this lab in the lab11-debug directory.

This directory is initially empty.

For this lab, you do the SystemC Advanced Debugging Tutorial. The tutorial model is a mixed-

language Consumer-Producer system somewhat similar to the PNET system. You follow the tutorial

instructions to debug the design, applying advanced features of the Cadence SimVision simulation

analysis environment.

Locate and Follow the Tutorial Instructions

1. Locate and open the tutorial instructions (that you briefly examined in lab 2)

2. Follow the tutorial instructions.