systemverilog constraints - dvcon 2020

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SystemVerilog Constraints Appreciating What You Forgot In School to Get Better Results Dave Rich Methodology Product Engineer Mentor, A Siemens Business

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Page 1: SystemVerilog Constraints - DVCon 2020

SystemVerilog ConstraintsAppreciating What You Forgot In School to Get Better Results

Dave RichMethodology Product Engineer

Mentor, A Siemens Business

Page 2: SystemVerilog Constraints - DVCon 2020

Motivation• More time is taken in debug

than any other project task

• Time wasted in debugging constrained random related problems is significant

16%

22%

23%

36%4%

Test Planning

Testbench Development

Creating and Running Test

Debug

Other

Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study, Used with permission

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Page 3: SystemVerilog Constraints - DVCon 2020

Agenda• Overview of Constrained Random Verification• Verilog Rules for Evaluating Expressions• The Effect of Probabilities and Statistics on Results

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Page 4: SystemVerilog Constraints - DVCon 2020

Constrained Random Verification• Defines stimulus at high level of

abstraction (random space)– Random variables and their range– System constraints

• More efficient than directed tests– Usually complemented by directed tests to

close coverage

• Requires a measurement strategy to assess the verification progress– Metric Driven Verification

DeviceUnder

Verification

0101010101110110110110110110100111011101110110111001011011011101101101

1010101010000001000111011101110110110110110110110001001001001001011

FunctionalCoverage

Checker

Header Payload Checksum

Constraints Are we done?

Manipulate random space

Does it work?

How efficient are my constrained random stimuli?

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Page 5: SystemVerilog Constraints - DVCon 2020

Constraints without Constraint Solvers

bit [1:0] X; // 0, 1, 2, 3bit [1:0] Y;

do beginX = $urandom;Y = $urandom;

end while (! (X<Y) );

• Wasted time randomizing– then throwing out results

• May never reach a solution– takes too long, or never

• Can randomize variables in sequential order only if dependencies are known

• Gets too complex as more constraints added– (X[0] != Y[0])

beginX = $urandom_range(0,2);Y = $urandom_range(X+1,3);

end

X < Y

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Page 6: SystemVerilog Constraints - DVCon 2020

Failure

Introduction to SystemVerilog Constrained RandomRandom Variables

Solution

Constraints Solver x

x

x

x

x

x

x

x

x

xx x

xx

x

x

x x x x xx

x

xx

xx

x

x

x x

xx

x

x xx

x

Random Constraints

6

M

QYZ

F

H

G

UA

RNG

Page 7: SystemVerilog Constraints - DVCon 2020

Randomizing Variables• Randomization is tied to object-oriented class system• Object is randomized by calling built-in randomize method

class Bus;rand bit [15:0] addr;rand bit [31:0] data;int pkt_number;constraint word_align {addr[1:0] == 2’b0;}

endclassBus busA = new;repeat (50)

if ( busA.randomize() == 1 ) $display("addr = %h data = %h",busA.addr,busA.data);

else$error("Randomization FAILED");

Both addr & data will be randomized

pkt_number will NOT be randomized

The randomize method sets the rand variables if successful

Always test return value of randomize

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Page 8: SystemVerilog Constraints - DVCon 2020

Introduction to SystemVerilog Constrained Random

• Expressions need to be held true by the Solver when solving a randomization problem

• May include random variables, non-random state variables, operators, distributions, literals, and constants

• Can be hard (default) or soft• Can be switched on/off using constraint_mode() • special operators

– inside (set membership), – -> (implication), – dist (distribution/weighting), – foreach (iteration),– if..else (conditional), – unique,…

• randomize()– Built-in class method– Randomizes class fields with rand/randc qualifiers according

to predefined constraints– Accepts inline constraints using the “with” clause– can be called to recursively randomize all random variables

of a class, or to randomize specific variable(s)• $urandom()

– Called in a procedural context to generate a pseudo-random number

• $urandom_range()– Returns an unsigned random integer value within a specified

range• std::randomize()

– Can be called outside the class scope to randomize non-class members.

– Can accept inline constraints using the “with” clause.• randcase, randsequence

– procedural randomness

• shuffle()– array shuffle

SystemVerilog Randomization Methods

SystemVerilog Randomization Constraints

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Page 9: SystemVerilog Constraints - DVCon 2020

Computing the Solution Space

• Solver uses formal techniques to prove a solution is possible

• Six possible solutions

• Random variables chosen as a set

• Each solution has equal probability • X has 50% chance of 0 value

class A;rand bit [1:0] X, Y;constraint C1 { X < Y;}

endclass

X Y

0 1

0 2

0 3

1 2

1 3

2 3

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Page 10: SystemVerilog Constraints - DVCon 2020

Understanding Verilog Expressions in SystemVerilog

• A fundamental principle of SV: Unify Expression Semantics

Verilog

SystemVerilog

n Started out unifying RTL-gate-TBn Split into multiple languages

n Came back together

Design AssertionsTestBench(s)

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Page 11: SystemVerilog Constraints - DVCon 2020

Verilog Expressions• Must handle specific integral bit widths

– Most programming languages only consider bytes or words• Signed and Unsigned arithmetic• Cannot generate extra hardware

– Need precise definitions for synthesis• Many steps in evaluating an expression

– Context– Precedence– Casting

• DV engineers not trained in software development– Want implicit casting (as opposed to VHDL)

A + B << C + DA +(B << C)+ D

(A + B)<<(C + D)

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Page 12: SystemVerilog Constraints - DVCon 2020

Expression Contexts• A self-determined expression is one where the bit length of the

expression result has no external influences – top level• A context-determined expression is one where the bit length of the

expression result is influenced by being part of another expression

A + B >> C < DOperators Length ofi op j result

Comments

+ - Max(L(i),L(j)) Operands are sized to result

<< >> L(i) j is self-determined

< <= > >= 1 Bit Operands are sized to Max

Precedence

Max(L(A),L(B),L(D))

((A + B)>> C)< D

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Page 13: SystemVerilog Constraints - DVCon 2020

LRM tables

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Page 14: SystemVerilog Constraints - DVCon 2020

Bit-Width Determination

• In-context operands sized to largest operand 4-bits

• A padded with 0• A + B evaluated in 4-bit context

– overflow truncated– result is 2 (4’h2) not 18(5’h12)

• Shift right result is 4 bits• Overall result is 1 bit

bit [2:0] A = 4; // 3 bitsbit [3:0] B = 14; // 4 bitsint C = 1; // not involvedbit [3:0] D = 8; // 4 bits( A + B >> C < D )

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Page 15: SystemVerilog Constraints - DVCon 2020

Constraint Expressions• Follows same Verilog rules—No Magic

• Unexpected consequences• Expect A+B sum to be less than 16, but A=4, B=14 is also a valid solution• Same fix as Verilog

rand bit [2:0] A;rand bit [3:0] B;constraint { A + B >> 1 < 4’d8; }

constraint { 5’(A + B) >> 1 < 4’d8; }

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Page 16: SystemVerilog Constraints - DVCon 2020

I am getting randomization failures when using array.sum()/array.product() reduction methods in constraints!

class trans;rand bit descr [];constraint c {descr.sum() == 50;descr.size() == 100;

}endclass

û

constraint c {descr.sum() with (int'(item)) == 50;descr.size() == 100;

}

ü

What is the width/precision of sum() result?

• sum()/product() results are computed with a width/precision of array base type

• Explicitly cast the array element(i.e. item) to an int data type whenneeded

!

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Page 17: SystemVerilog Constraints - DVCon 2020

Signed Expressions• Signedness affects extension and relational operators• Decimal numbers are 32-bit signed – 1 23 46• Based literals are default unsigned – ’h1 64’d23 32’d46• Expressions unsigned unless all operands in context are signed• Sign extension only applies to the signed part of the expression

bit signed [2:0] A = -1; bit [3:0] B = 14;A + B < 14

A + B evaluated in 32-bit context

A becomes unsigned 32’d7

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Page 18: SystemVerilog Constraints - DVCon 2020

Unexpected negative values are generated upon randomize!

class trans;rand int addr;constraint c {addr < MAX_ADDR;

}endclass

int, byte, and variables declared as signed can hold negative random values

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Values between 32’h1000_0000 and 32’hFFFF_FFFF are valid

Page 19: SystemVerilog Constraints - DVCon 2020

Bad Behavior• Results are not what we wanted

– getting values we don’t believe are correct– Expression semantics are just one cause

• Results are valid but seem over constrained– not getting all the values we expect– statistics and ordering

• Not getting any results—solver fails– Any of the above

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Page 20: SystemVerilog Constraints - DVCon 2020

Computing the Solution Space• ALL constraints are uniformly applied to all variables

• Conventional thinking would assume equal probability for all values

rand bit [2:0] X, Y;constraint C1 { X < Y;}

X and Y are solved at the same time

Y=7 X=6 or 5 or 4 or 3 or 2 or 1 or 0Y=6 X=5 or 4 or 3 or 2 or 1 or 0Y=5 X=4 or 3 or 2 or 1 or 0Y=4 X=3 or 2 or 1 or 0Y=3 X=2 or 1 or 0Y=2 X=1 or 0Y=1 X=0

There are 28 solutions-----------------------------------{7,6} {7,5} {7,4} … {7,0}{6,5} {6,4} … {6,0}…{1,0}

Probability of Y=7: 7/28

Probability of Y=1: 1/28

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Page 21: SystemVerilog Constraints - DVCon 2020

Achieving Results We Expect• If we want an even distribution on Y without disturbing the solution

space

• This tells the solver to first choose Y value and then pick X value• Y=1 now has an equal probability of occurring as Y=7• Think “Choose Y’s value from the solution set before choosing X’s

value” – everything is already solved!

rand bit [2:0] X, Y;constraint C1 {

X < Y;solve Y before X;

}

Add solve before constraint

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Page 22: SystemVerilog Constraints - DVCon 2020

More on Solution Space• SV standard requires solver must assure random values are selected

to give uniform value distribution over legal combinations

• There are 233 (8.5 billion) combinations of {ctrl,data}• “ctrl” only true for {1,0}• Probability that “ctrl” is true: 1 / 233 … practically zero

class A;rand bit ctrl;rand bit [31:0] data;constraint C0 {ctrl -> data == 0;}

endclass : A“ctrl” implies “data” equals zero

“ctrl” and “data” are solved together even though it appears “ctrl” determines “data”(! ctrl || data==0)

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Page 23: SystemVerilog Constraints - DVCon 2020

Variable Ordering Example• We can force “ctrl” to have an even distribution

• “ctrl” chosen first before “data”

• Since “data” now determined by “crtl”

class A;rand bit ctrl;rand bit [31:0] data;constraint C0 {

ctrl -> data == 0;solve ctrl before data;}

endclass : A

50% chance ctrl == 1, 50% chance ctrl == 0

~50% chance data == 0, ~50% chance data != 0

Use the variable ordering operator

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Page 24: SystemVerilog Constraints - DVCon 2020

Implication Example• Implication is also bi-directional

– Results may not be what you expect

typedef bit [5:0] addr_t;typedef enum {READ,WRITE,NOP} kind;

class Packet_c;rand addr_t address;rand bit [8:0] data;rand kind op;constraint data_range {

(op == READ) -> data inside {[1:100]};(op == WRITE) -> data inside {[101:300]};(op == NOP) -> data inside {0};

}endclass : Packet_c

301 Solutions100: op ═ READ200: op ═ WRITE1: op ═ NOP

1 in 301 chance ofop ═ NOP

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Page 25: SystemVerilog Constraints - DVCon 2020

Distribution Example• Could use variable ordering • With distribution, user has more control over variable values

typedef bit [7:0] addr_t;typedef enum {READ,WRITE,NOP} kind;class Packet_c;

rand addr_t address;rand bit [31:0] data;rand kind op;constraint data_range {

(op == READ) -> data inside {[1:100]};(op == WRITE) -> data inside {[101:300]};(op == NOP) -> data inside {0};solve op before data;

}endclass : Packet_c

op dist {READ :=2, WRITE:=2, NOP:=1};

READ, WRITE, & NOP have even probability of occurring

READ: 40% WRITE: 40% NOP: 20%25

Page 26: SystemVerilog Constraints - DVCon 2020

Exact distributions• Probability of getting exactly the distribution you want is low until you

try an infinite number of times• Flip a coin 10 times, only 25% chance of getting exactly 5H/5Ttypedef enum {HEADS,TAILS} coin_t;class C;

rand coin_t toss;randc int scale;constraint c {

scale inside {[0:99]};(scale < 50) -> toss == HEADS;(scale >=50) -> toss == TAILS;

}endclass : Packet_c

• randc cycles all values evenly in its solution set before repeating a value

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Page 27: SystemVerilog Constraints - DVCon 2020

Summary• Rules for evaluating constraint expressions much match rules for

synthesizing RTL expressions• Must understand how to parse context, precedence, bit-width and

signed arithmetic in expressions• Consider probabilities and statistics in results

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Page 28: SystemVerilog Constraints - DVCon 2020

References• Mentor Graphics Verification Academy, www.verificationacademy.com• The Top Most Common SystemVerilog Constrained Random Gotchas,

Ahmed Yehia, DVCon-Europe 2014.• IEEE Standard for SystemVerilog, Unified Hardware Design,

Specification, and Verification Language, IEEE Std 1800-2017.https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80

• Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them, Stuart Sutherland and Don Mills, Springer

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