table of contents revisions 1 toc/revision history rev … · 2016-11-01 · table of contents...

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D D

C C

B B

A A

RevisionsRev Description ApprovedDate

89 SENSORS

USB/OSBDM/VTRAN/PWRPERIPHERALSELEVATOR CONNECTORS

K70N1M MCU-1

7

1 TOC/REVISION HISTORY

45

Table of Contents

RESERVED2 NOTES3

10

K70N1M MCU-26

11 DDR POWER & TERMINATIONSDDR2 SDRAM, NAND FLASH

A Prototype release 22 Jul 11 TTC

B A085 Release 27 Oct 11

B1 A085 Release - MCU Marketing part number updated as per MCO30515

3 Nov 11 Peter

C A085 Release 8 Feb 12Kevin

Peter,

C1- Replaced obsolete resistor470-80310 with 470-75416

- Changed R326 to DNP

2 Jul 12Kevin

Peter,

Peter

C2- Changed R31, R32, R35, and R71 toDNP 6 Jul 12

Kevin

Peter,

Drawing Title:

Size Document Number Rev

Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:

Microcontroller Solutions Group

6501 William Cannon Drive WestAustin, TX 78735-8598

This document contains information proprietary to Freescale Semiconductor and shall not be used forengineering design, procurement or manufacture in whole or in part without the express written permissionof Freescale Semiconductor.

ICAP Classification: FCP: FIUO: PUBI:

SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C

Friday, July 06, 2012

Table of Contents/Revisions

ionDSN

Peter/Kevin

ionDSN

1 11

____X____Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:





SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

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ionDSN

Peter/Kevin

ionDSN

1 11

____X____Drawing Title:


Date: Sheet of

Page Title:

Designer:

Drawn by:

Approved:





SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

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ionDSN

Peter/Kevin

ionDSN

1 11

____X____

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1. Unless Otherwise Specified:

All resistors are in ohms

All capacitors are in uF

All voltages are DC

All polarized capacitors are aluminum electrolytic

2. Interrupted lines coded with the same letter or letter combinations are electrically connected.

3. Device type number is for reference only. The number varies with the manufacturer.

4. Special signal usage:

_B Denotes - Active-Low Signal

<> or [] Denotes - Vectored Signals

5. Interpret diagram in accordance with American National Standards Institute specifications, current revision, with the exception of logic block symbology.

Power & Ground Nets

P3V3 3.3V Output of regulator using USB power input (P5V_TRG_USB).

P3V3_MCU 3.3V MCU digital power. Filtered from P3V3.

VDDA 3.3V VDDA power for MCU and analog circuits. Filtered from P3V3_MCU.

VREFH 3.3V Upper reference voltage for ADC on the MCU. Filtered from VDDA.

VREFL 0V Lower reference voltage for ADC on the MCU. Filtered from VSSA.

VSSA 0V VSSA power for MCU and analog circuits. Filtered from GND.

P5V_USB 5V Primary input power. Filtered from USB connector. Input to USB power switch.

P5V_SW 5V Output of USB power switch controlled by the 5V_EN signal from the JM60 MCU. Used by OSBDM voltage translation circuits.

P5V_TRG_USB 5V Output of USB power switch controlled by the VTRG_EN signal from the JM60 MCU. Provides input to regulator.

GND 0V Digital Ground.

NET VOLTAGE DESCRIPTION

VDD_INT 3.3V MCU Internal supply

VREF_DDR2 0.9V DDR2 VREF = VDDQ/2 supply for MCU and SDRAM

VTT_DDR2 0.9V DDR2 VTT= VDDQ/2 termination supply for MCU and SDRAM

VDD_1V8 1.8V DDR2 VDDQ supply for MCU and SDRAM

Drawing Title:


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Notes

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Notes

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Notes

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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Drawing Title:


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Reserved

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Reserved

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Reserved

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___ ___X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK Input

SPI2_SCK/SDHC0_D4

SPI0_SOUT/I2C0_SDA

I2S0_TX_FS

SPI2_PCS1/SDHC0_D7

FB_AD24/UART4_TX

FB_AD9/

LCD_D15/UART5_RX

LCD_D16/UART5_TX

LCD_D14/UART0_TX

I2S0_RX_FS

FB_AD25/UART4_RX

FB_TA/ENET0_1588_TMR3

SPI1_SOUT/SDHC0_CMD

LCD_PCLK/

SPI0_SIN/I2C0_SCL

FB_AD2/

FB_AD6/

FB_AD14/TSI0_CH13

FB_CS0/

LCD_D18/UART5_CTS_B

LCD_D19/TRACE_CLKOUT

LCD_D17/UART5_RTS_B

LCD_D0

Reserved_K7

LCD_D3

I2S0_RX_BCLK

FB_AD26/UART4_CTS_B

ADC3_SE7A

FB_AD10/

ENET0_1588_TMR2

FB_AD5/I2C1_SCL

LCD_DE/

LCD_D21/TRACE_D2

LCD_D22/TRACE_D1

LCD_D20/TRACE_D3

FB_AD3/

FB_AD11/UART1_TX

VTT_SENSE

LCD_D4

FB_AD27/UART4_RTS_B

LCD_D23/TRACE_D0

FB_AD0/

FB_AD7/

FB_TS_N/pushbutton1

NFC_CLE

I2S0_TX_BCLK

LCD_HSYNC/

LCD_D1

LCD_D6/UART3_CTS_B

LCD_D7/UART2_RTS_B

LCD_D5/UART3_RTS_B

FB_AD4/

NFC_ALE

FB_RW/I2C1_SDA

UART3_RX/NFC_RnB

UART3_TX/NF_CE0

SPI1_PCS1/SDHC0_D1

FB_CLKOUT/UART1_RX

SPI0_PCS0

SPI2_SOUT/SDHC0_D5

SDHC0_D3

FB_AD8/

FB_AD12/TSI0_CH15

SPI1_SIN/SDHC0_D0

LCD_D9/UART2_RX

LCD_D10/UART2_TX

LCD_D8/UART2_CTS_B

NFC_RE

I2S0_MCLK

SPI0_SCK

SPI1_SCK/SDHC0_DCLK

SPI2_SIN/SDHC0_D6

I2S0_TXD0

LCD_VSYNC/

LCD_D12/UART0_CTS_B

LCD_D13/UART0_RX

LCD_D11/UART0_RTS_B

LCD_D2

FB_AD1/

SPI2_PCS0

SDHC0_D2

I2S0_RXD0

FB_AD13/TSI0_CH14

FB_AD17/TSI0_CH9

IRQ1

FB_AD22/ADC1_SD13

FB_AD18/

IRQ2

FB_AD23/ADC1_SD12

FB_AD19/

FB_OE_N/TSI0_CH12

FB_AD15/TSI0_CH11

TDI/EZP_DI/FTM0_CH6

FB_AD20/TWRPI_GPIO2

TRST\RMII0_RXER

EZP_CS_B/TSI0_CH5

RMII0_TXD1

TRACE_D0/ULPI_DATA0

RMII0_TXEN

TRACED3\ULPI_DIR

ULPI_DATA3

ULPI_DATA2

TDO/EZP_DO

TRACED1\ULPI_STP

TRACED2\ULPI_NXT

RMII0_TXD0

EXTAL_MAIN PTA18

ULPI_DATA4

TRACE_CLKOUT/ULPI_CLK

TWRPI_GPIO3

ULPI_DATA5

TCK/EZP_CLK

TMS

RMII0_RXD1

ULPI_DATA6

ULPI_DATA1

RMII0_RXD0

ULPI_DATA7

RMII0_CRS_DV

FB_AD28/

TSI0_CH7

FB_AD29/

TSI0_CH8

RMII0_MDIO/TSI0_WU

FB_AD16/TSI0_CH10

FB_AD30/

RMII0_MDC/TSI0_CH6

FB_AD21/TWRPI_GPIO1

FB_AD31/

Place Y4 and related components as closeas possible to U53

Place R89 and R90 and related componentsas close as possible to U53

Place Y5 and relatedcomponents as close aspossible to U53

pushbutton0

Default : short 1-2

J18 OFF -> Y1 Enabled

J18 ON -> Y1 Disabled

USB0R_DN

32KHz_XTL

32KHz_EXTL EXTAL32_RTC

ADC1_DM0ADC0_DP1ADC0_DM1

ADC1_DP0ADC0_DM0ADC0_DP0

XTAL32_RTC

PTA12

PTA5

PTA1PTA2PTA3PTA4

PTA0

PTA19

PTA7

PTA15PTA16

PTA9

PTA6

PTA17

PTA11

PTA13PTA14

PTA8

PTA10

PTA27

PTA25PTA24

PTA26

PTA29PTA28

50MHz_OSC EXTAL_MAIN

PTA18

USB0R_DP

ADC1_DM1ADC1_DP1

PTF1PTF2PTF3PTF4PTF5PTF6PTF7PTF8PTF9PTF10PTF11PTF12PTF13PTF14PTF15PTF16PTF17PTF18PTF19

PTF0

PTC1PTC2PTC3PTC4PTC5PTC6PTC7PTC8PTC9PTC10

PTF21PTF22PTF23PTF24PTF25PTF26PTF27

PTF20

PTC12PTC13PTC14PTC15PTC16PTC17PTC18PTC19

PTD1PTD2PTD3PTD4PTD5PTD6PTD7PTD8PTD9PTD10PTD11PTD12PTD13PTD14PTD15

PTE0PTE1

PTD0

PTE4PTE5PTE6PTE7PTE8PTE9PTE10PTE11PTE12PTE16PTE17PTE18PTE19EXTAL1 EXTAL1

PTE26PTE27PTE28

PTE3

PTC0

PTB3

PTB22

PTB0PTB1PTB2

PTB4PTB5PTB6PTB7PTB8PTB9PTB10PTB11PTB16PTB17PTB18PTB19PTB20PTB21

PTB23

PTE2

PTC11

XTAL1 XTAL1

PTC19

+3_3V_OSC

RESET_B{6,8,9}

USB0_DP{8}USB0_DN{8}

PTA[0..29]{6,8,9}

PTB[0..23]{8,9,10}

PTC[0:19] {8,9,10}

PTD[0:15] {7,8,9,10}

PTE[0:28] {6,7,8,9}

P3V3

P3V3

ADC0_SE16{5}

ADC1_SE16{9}

ADC1_DP0{8,9}ADC1_DM0{8}ADC0_DP1{8,9}ADC0_DM1{8,9}ADC1_DP1{8,9}ADC1_DM1{8,9}

ADC0_DP0{8,9}ADC0_DM0{8,9}

DAC0_OUT{8}DAC1_OUT/CMP2_IN3{7,8}

CLKIN0{8}

PTF[0:27] {8}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

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PK70FN1M0VMJ15 MCU Part 1

4 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

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4 11



Date: Sheet of

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SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

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4 11

___ ___X

GND2

GND1

Y5

12MHZ

1 234

R122 68

CLK

OUT

VDD

GND

OE

50MHZ

Y1

42

31

R91 0

C81

10UF

TP36

R89 33

TP31

TP22DNP

R92 0

1 OF 2

U53A

PK70FN1M0VMJ12

PTC0/ADC0_SE14/TSI0_CH13/SPI0_PCS4/PDB0_EXTRG/FB_AD14/NFC_DATA11/I2S0_TXD1G16

PTC1/ADC0_SE15/TSI0_CH14/SPI0_PCS3/UART1_RTS/FTM0_CH0/FB_AD13/NFC_DATA10/I2S0_TXD0F13

PTC10/ADC1_SE6B/CMP0_IN4/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5/NFC_DATA2/I2S1_MCLKG11

PTC11/ADC1_SE7B/I2C1_SDA/FTM3_CH7/I2S0_RXD1/FB_RW/NFC_WEH11

PTC12/UART4_RTS/FB_AD27/FTM3_FLT0J12

PTC13/UART4_CTS/FB_AD26K13

PTC14/UART4_RX/FB_AD25J11

PTC15/UART4_TX/FB_AD24F10

PTC16/CAN1_RX/UART3_RX/ENET0_1588_TMR0/FB_CS5/FB_TSIZ1/FB_BE23_16_BLS15_8/NFC_RBF9

PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4/FB_TSIZ0/FB_BE31_24_BLS7_0/NFC_CE0E9

PTC18/UART3_RTS/ENET0_1588_TMR2/FB_TBST/FB_CS2/FB_BE15_8_BLS23_16/NFC_CE1M9

PTC19/UART3_CTS/ENET0_1588_TMR3/FB_CS3/FB_BE7_0_BLS31_24/FB_TAM8

DRYICE_TAMPER0/RTC_WAKEUPM5

DRYICE_TAMPER1L5

DRYICE_TAMPER2L6

DRYICE_TAMPER3R5

DRYICE_TAMPER4P6

DRYICE_TAMPER5R6

DRYICE_TAMPER6N6

DRYICE_TAMPER7M6

PGA0DM_ADC0DM0_ADC1DM3R2 PGA0DP_ADC0DP0_ADC1DP3R1

PGA1DM_ADC1DM0_ADC0DM3T2 PGA1DP_ADC1DP0_ADC0DP3T1

PGA2DM_ADC2DM0_ADC3DM3_ADC0DM1N2 PGA2DP_ADC2DP0_ADC3DP3_ADC0DP1N1

PGA3DM_ADC3DM0_ADC2DM3_ADC1DM1P2 PGA3DP_ADC3DP0_ADC2DP3_ADC1DP1P1

PTA0/JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/UART0_CTS/UART0_COL/FTM0_CH5T7

PTA1/JTAG_TDI/EZP_DI/TSI0_CH2/UART0_RX/FTM0_CH6N8

PTA2/JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/UART0_TX/FTM0_CH7T8

PTA4/NMI/EZP_CS/TSI0_CH5/FTM0_CH1R8

PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/I2S0_TX_BCLK/JTAG_TRSTT12

PTA6/ADC3_SE6A/ULPI_CLK/FTM0_CH3/I2S1_RXD0/TRACE_CLKOUTR12

PTA7/ADC0_SE10/ULPI_DIR/FTM0_CH4/I2S1_RX_BCLK/TRACE_D3P12

PTA8/ADC0_SE11/ULPI_NXT/FTM1_CH0/I2S1_RX_FS/FTM1_QD_PHA/TRACE_D2N12

PTA9/ADC3_SE5A/ULPI_STP/FTM1_CH1/MII0_RXD3/FTM1_QD_PHB/TRACE_D1T13

PTA10/ADC3_SE4A/ULPI_DATA0/FTM2_CH0/MII0_RXD2/FTM2_QD_PHA/TRACE_D0P13

PTA11/ADC3_SE15/ULPI_DATA1/FTM2_CH1/MII0_RXCLK/FTM2_QD_PHBR13

PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2S0_TXD0/FTM1_QD_PHAM10

PTA13/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2S0_TX_FS/FTM1_QD_PHBN10

PTA14/CMP3_IN0/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2S0_RX_BCLK/I2S0_TXD1R11

PTA15/CMP3_IN1/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0P11

PTA16/CMP3_IN2/SPI0_SOUT/UART0_CTS/UART0_COL/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1N11

PTA17/ADC1_SE17/SPI0_SIN/UART0_RTS/RMII0_TXD1/MII0_TXD1/I2S0_MCLKT11

PTA18/EXTAL/FTM0_FLT2/FTM_CLKIN0T15

PTA19/XTAL/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1T16

PTA3/JTAG_TMS/SWD_DIO/TSI0_CH4/UART0_RTS/FTM0_CH0P8

PTA24/CMP3_IN4/ULPI_DATA2/MII0_TXD2/FB_A29N13

PTA25/CMP3_IN5/ULPI_DATA3/MII0_TXCLK/FB_A28R14

PTA26/ADC2_SE15/ULPI_DATA4/MII0_TXD3/FB_A27M13

PTA27/ADC2_SE14/ULPI_DATA5/MII0_CRS/FB_A26R15

PTA28/ADC2_SE13/ULPI_DATA6/MII0_TXER/FB_A25P14

PTA29/ADC2_SE12/ULPI_DATA7/MII0_COL/FB_A24N14

PTB0/ADC0_SE8/ADC1_SE8/ADC2_SE8/ADC3_SE8/TSI0_WU/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHAM12

PTB1/ADC0_SE9/ADC1_SE9/ADC2_SE9/ADC3_SE9/TSI0_CH6/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHBM11

PTB10/ADC1_SE14/SPI1_PCS0/UART3_RX/I2S1_TX_BCLK/FB_AD19/FTM0_FLT1J13

PTB11/ADC1_SE15/SPI1_SCK/UART3_TX/I2S1_TX_FS/FB_AD18/FTM0_FLT2J14

PTB16/TSI0_CH9/SPI1_SOUT/UART0_RX/I2S1_TXD0/FB_AD17/EWM_INJ15

PTB17/TSI0_CH10/SPI1_SIN/UART0_TX/I2S1_TXD1/FB_AD16/EWM_OUTH13

PTB18/TSI0_CH11/CAN0_TX/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/FTM2_QD_PHAH14

PTB19/TSI0_CH12/CAN0_RX/FTM2_CH1/I2S0_TX_FS/FB_OE/FTM2_QD_PHBH15

PTB20/ADC2_SE4A/SPI2_PCS0/FB_AD31/NFC_DATA15/CMP0_OUTG13

PTB21/ADC2_SE5A/SPI2_SCK/FB_AD30/NFC_DATA14G14

PTB22/SPI2_SOUT/FB_AD29/NFC_DATA13G15

PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28/NFC_DATA12/CMP3_OUTH16

PTB2/ADC0_SE12/TSI0_CH7/I2C0_SCL/UART0_RTS/ENET0_1588_TMR0/FTM0_FLT3P15

PTB3/ADC0_SE13/TSI0_CH8/I2C0_SDA/UART0_CTS/UART0_COL/ENET0_1588_TMR1/FTM0_FLT0M14

PTB4/ADC1_SE10/GLCD_CONTRAST/ENET0_1588_TMR2/FTM1_FLT0N15

PTB5/ADC1_SE11/ENET0_1588_TMR3/FTM2_FLT0M15

PTB6/ADC1_SE12/FB_AD23L14

PTB7/ADC1_SE13/FB_AD22L15

PTB8/UART3_RTS/FB_AD21K14

PTB9/SPI1_PCS1/UART3_CTS/FB_AD20K15

PTD0/SPI0_PCS0/UART2_RTS/FTM3_CH0/FB_ALE/FB_CS1/FB_TS/I2S1_RXD1L8

PTD1/ADC0_SE5B/SPI0_SCK/UART2_CTS/FTM3_CH1/FB_CS0/I2S1_RXD0F8

PTD10/UART5_RTS/FB_A18/NFC_REE6

PTD11/SPI2_PCS0/UART5_CTS/SDHC0_CLKIN/FB_A19/GLCD_CONTRASTG5

PTD12/SPI2_SCK/FTM3_FLT0/SDHC0_D4/FB_A20/GLCD_PCLKF5

PTD13/SPI2_SOUT/SDHC0_D5/FB_A21/GLCD_DEF4

PTD14/SPI2_SIN/SDHC0_D6/FB_A22/GLCD_HFSE5

PTD15/SPI2_PCS1/SDHC0_D7/FB_A23/GLCD_VFSE4

PTF0/ADC2_SE11/CAN0_TX/FTM3_CH0/I2S1_RXD1/GLCD_PCLKP16

PTF1/ADC2_SE10/CAN0_RX/FTM3_CH1/I2S1_RX_BCLK/GLCD_DEL13

PTF10/UART3_CTS/GLCD_D6L12

PTF11/UART2_RTS/GLCD_D7K11

PTF12/UART2_CTS/GLCD_D8L11

PTF13/UART2_RX/GLCD_D9H6

PTF14/UART2_TX/GLCD_D10G6

PTF15/UART0_RTS/GLCD_D11F6

PTF16/SPI2_PCS0/FTM0_CH3/UART0_CTS/UART0_COL/GLCD_D12E1

PTF17/SPI2_SCK/FTM0_CH4/UART0_RX/GLCD_D13F1

PTF18/SPI2_SOUT/FTM1_CH0/UART0_TX/GLCD_D14G1

PTF19/SPI2_SIN/FTM1_CH1/UART5_RX/GLCD_D15H1

PTC2/ADC0_SE4B/TSI0_CH15/SPI0_PCS2/UART1_CTS/FTM0_CH1/FB_AD12/NFC_DATA9/I2S0_TX_FSF14

PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/FB_CLKOUT/I2S0_TX_BCLKE13

PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/NFC_DATA8/I2S1_TX_BCLKE14

PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/NFC_DATA7/CMP0_OUT/I2S1_TX_FSE15

PTC6/CMP0_IN0/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/NFC_DATA6/I2S0_MCLKF12

PTC7/CMP0_IN1/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS/FB_AD8/NFC_DATA5G12

PTC8/ADC1_SE4B/CMP0_IN2/FTM3_CH4/I2S0_MCLK/FB_AD7/NFC_DATA4H12

PTC9/ADC1_SE5B/CMP0_IN3/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/NFC_DATA3/FTM2_FLT0F11

PTD2/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/I2S1_RX_FSK6

PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/I2S1_RX_BCLKJ6

PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/FB_AD2/NFC_DATA1/EWM_INK5

PTD5/ADC0_SE6B/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/FB_AD1/NFC_DATA0/EWM_OUTJ5

PTD6/ADC0_SE7B/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0K4

PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1E7

PTD8/I2C0_SCL/UART5_RX/FB_A16/NFC_CLEJ4

PTD9/I2C0_SDA/UART5_TX/FB_A17/NFC_ALEF7

PTE0/ADC1_SE4A/SPI1_PCS1/UART1_TX/SDHC0_D1/GLCD_D0/I2C1_SDA/RTC_CLKOUTE2

PTE1/ADC1_SE5A/SPI1_SOUT/UART1_RX/SDHC0_D0/GLCD_D1/I2C1_SCL/SPI1_SINF2

PTE10/UART5_CTS/I2S0_TXD0/GLCD_D10/FTM3_CH5J2

PTE11/ADC3_SE16/UART5_RTS/I2S0_TX_FS/GLCD_D11/FTM3_CH6K1

PTE12/ADC3_SE17/I2S0_TX_BCLK/GLCD_D12/FTM3_CH7K3

PTE16/ADC0_SE4A/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3J3

PTE17/ADC0_SE5A/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3K2

PTE18/ADC0_SE6A/SPI0_SOUT/UART2_CTS/I2C0_SDAL4

PTE19/ADC0_SE7A/SPI0_SIN/UART2_RTS/I2C0_SCL/CMP3_OUTM3

PTE24/ADC0_SE17/EXTAL1/CAN1_TX/UART4_TX/I2S1_TX_FS/GLCD_D13/EWM_OUT/I2S1_RXD1P7

PTE25/ADC0_SE18/XTAL1/CAN1_RX/UART4_RX/I2S1_TX_BCLK/GLCD_D14/EWM_IN/I2S1_TXD1R7

PTE26/ADC3_SE5B/ENET_1588_CLKIN/UART4_CTS/I2S1_TXD0/GLCD_D15/RTC_CLKOUT/USB_CLKINM7

PTE27/ADC3_SE4B/UART4_RTS/I2S1_MCLK/GLCD_D16K7

PTE28/ADC3_SE7A/GLCD_D17L7

PTE3/ADC1_SE7A/SPI1_SIN/UART1_RTS/SDHC0_CMD/GLCD_D3/SPI1_SOUTG2

PTE4/SPI1_PCS0/UART3_TX/SDHC0_D3/GLCD_D4G3

PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2/GLCD_D5/FTM3_CH0G4

PTE6/SPI1_PCS3/UART3_CTS/I2S0_MCLK/GLCD_D6/FTM3_CH1/USB_SOF_OUTH2

PTE7/UART3_RTS/I2S0_RXD0/GLCD_D7/FTM3_CH2H3

PTE8/ADC2_SE16/I2S0_RXD1/UART5_TX/I2S0_RX_FS/GLCD_D8/FTM3_CH3H4

PTE9/ADC2_SE17/I2S0_TXD1/UART5_RX/I2S0_RX_BCLK/GLCD_D9/FTM3_CH4J1

PTE2/ADC1_SE6A/SPI1_SCK/UART1_CTS/SDHC0_DCLK/GLCD_D2F3

RESETR16

USB0DMM2 USB0DPM1

EXTAL32T5

XTAL32T6

DAC0OUT_CMP1IN3_ADC0SE23R3

DAC1OUT_CMP2IN3_ADC1SE23R4

PTF2/ADC2_SE6A/I2C1_SCL/FTM3_CH2/I2S1_RX_FS/GLCD_HFSN16

PTF4/ADC2_SE4B/FTM3_CH4/I2S1_TXD0/GLCD_D0L16

PTF5/ADC2_SE5B/FTM3_CH5/I2S1_TX_FS/GLCD_D1K16

PTF6/ADC2_SE6B/FTM3_CH6/I2S1_TX_BCLK/GLCD_D2J16

PTF7/ADC2_SE7B/FTM3_CH7/UART3_RX/I2S1_TXD1/GLCD_D3F15

PTF8/FTM3_FLT0/UART3_TX/I2S1_MCLK/GLCD_D4F16

PTF9/UART3_RTS/GLCD_D5K12

PTF20/SPI2_PCS1/FTM2_CH0/UART5_TX/GLCD_D16H5

PTF21/ADC3_SE6B/FTM2_CH1/UART5_RTS/GLCD_D17P9

PTF22/ADC3_SE7B/I2C0_SCL/FTM1_CH0/UART5_CTS/GLCD_D18N9

PTF23/ADC3_SE10/I2C0_SDA/FTM1_CH1/TRACE_CLKOUT/GLCD_D19P10

PTF24/ADC3_SE11/CAN1_RX/FTM1_QD_PHA/TRACE_D3/GLCD_D20R10

PTF25/ADC3_SE12/CAN1_TX/FTM1_QD_PHB/TRACE_D2/GLCD_D21R9

PTF26/ADC3_SE13/FTM2_QD_PHA/TRACE_D1/GLCD_D22T9

PTF27/ADC3_SE14/FTM2_QD_PHB/TRACE_D0/GLCD_D23T10

PTF3/ADC2_SE7A/I2C1_SDA/FTM3_CH3/I2S1_RXD0/GLCD_VFSM16

ADC0SE16_CMP1IN2_ADC0SE21N3

ADC1SE16_CMP2IN2_ADC0SE22P3

TP38

TP35

TP33

TP37

R90 33

R133 10M

R212 22

J19

HDR 1X2 TH

1 2

R338

10.0K

R93

1.0M

DNP

C80

0.1UF

C77 18PF

DNP

R94 68

TP34

TP21DNP

C78 18PF

DNP

J21

HDR 1X2 TH

1 2

Y4

32.768KHz

12

C20

27pF

J18

HDR 1X2 TH

1 2

TP26TP27

L12

120OHM

12

TP30

C19

27pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

2016/25/32Coin Cell

Default: 1-2(use P3V3_MCU)

Default: 1-2(use P3V3)

VREGIN

DDR2_ADD4DDR2_ADD5DDR2_ADD6DDR2_ADD7DDR2_ADD8DDR2_ADD9DDR2_ADD10DDR2_ADD11DDR2_ADD12

DDR2_ADD0DDR2_ADD1DDR2_ADD2DDR2_ADD3

VBATD

VCOIN

VBAT

DDR2_CKDDR2_CK_B

DDR2_DQ0DDR2_DQ1

DDR2_DQ10DDR2_DQ11

DDR2_DQ2DDR2_DQ3DDR2_DQ4DDR2_DQ5DDR2_DQ6DDR2_DQ7DDR2_DQ8DDR2_DQ9

DDR2_DQ12DDR2_DQ13DDR2_DQ14DDR2_DQ15

VREF_OUT

DDR2_CS_B

P3V3R

VOUT_3V3

VDDINT

DDR2_CKEDDR2_ODT

DDR2_DQS1

DDR2_DQM0DDR2_DQM1

DDR2_WE_B

DDR2_CAS_B

DDR2_RAS_B

DDR2_BA0DDR2_BA1DDR2_BA2

DDR2_DQS0DDR2_DQS0{10}DDR2_DQS1{10}

DDR2_DQ[15:0] {10}

P3V3_MCU

P3V3_MCU

P3V3_MCU

P3V3

VREFH

VREFL

VSSA

VDDA

VREF_DDR2

VDD_1V8

ADC0_SE16 {4}

DDR2_ADD[12:0]{10}

VREGIN {8}

DDR2_CKE{10}

DDR2_ODT {10}

DDR2_DQM0{10}

DDR2_WE_B {10}

DDR2_DQM1{10}

DDR2_CAS_B {10}

DDR2_RAS_B {10}

DDR2_CK_B{10}

DDR2_BA1{10}DDR2_BA2{10} DDR2_CS_B {10}

DDR2_BA0{10}

DDR2_CK{10}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C



5 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C



5 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C



5 11

___ ___X

TP28

R880DNP

C17

0.1UF

C75

0.1UF

+

-BT2

BK-883

13 2

C73

0.1UFC24

0.1UF

J20HDR 1X2 TH

1 2

J8

HDR 1X2 TH

12

C23

0.1UF

C22

0.01UF

BAT54CD13

3

1

2

L6

100 OHM@100MHZ12

C4

0.1UF

R86

10.0K

J17

HDR TH 1X3

123

C74

2.2UF

C29

0.1UF

TP20DNP

C18

0.1UF

L4

100 OHM@100MHZ12

L8

100 OHM@100MHZ12

2 OF 2

U53B

PK70FN1M0VMJ12

DDR_A0D10

DDR_A1C11

DDR_A10B13

DDR_A2B11

DDR_A3C12

DDR_A4C10

DDR_A5A13

DDR_A6A14

DDR_A7D11

DDR_A8A15

DDR_A9B15

DDR_DM0D9

DDR_DM1A3

DDR_ODTA7

DDR_VDD1B1

DDR_VDD10C16

DDR_VDD2D2

DDR_VDD3D4

DDR_VDD4B5

DDR_VDD5D7

DDR_VDD6B8

DDR_VDD7E10

DDR_VDD8B12

DDR_VDD9E12

DDR_VREFC6

DDR_CASC13

DDR_CSD14

DDR_RASE16

DDR_WED13

DDR_VSS1A1

DDR_VSS10A16

DDR_VSS2E3

DDR_VSS3A5

DDR_VSS4C7

DDR_VSS5D8

DDR_VSS6C9

DDR_VSS7A12

DDR_VSS8D12

DDR_VSS9C14

DDR_VSS_BULK1D5

DDR_VSS_BULK2E8

DDR_VSS_BULK3E11

VDD1G7

VDD2J7

VDD3G8

VDD4G9

VDD5G10

VDD6J10

VDD7K10

VDD8L10

VDDAN5

VSS1L2

VSS10L9

VSS11T14

VSS2T4

VSS3N7

VSS4H8

VSS5J8

VSS6K8

VSS7H9

VSS8J9

VSS9K9

VSSAN4

DDR_CKA10

DDR_CKEB16

DDR_CKA11

DDR_BA1B10 DDR_BA0A9

DDR_BA2B9

DDR_DQS1D3

DDR_DQ0C5

DDR_DQ1B4

DDR_DQ10C2

DDR_DQ11B2

DDR_DQ2A4

DDR_DQ3B6

DDR_DQ4D6

DDR_DQ5A6

DDR_DQ6B7

DDR_DQ7A8

DDR_DQ8D1

DDR_DQ9C1

DDR_DQS0C8

DDR_DQ12C3

DDR_DQ13C4

DDR_DQ14B3

DDR_DQ15A2

DDR_A11B14

DDR_A12C15

DDR_A13D16

DDR_A14D15

VDDINT1H7

VDDINT2H10

VOUT33L1

VREFHP4

VREFLM4

VREFOUT_CMP1IN5_CP0IN5_ADC1SE18T3

VREGINL3

VBATP5

C71

0.1UF

R87

10.0K

C72

0.1UF

L7

100 OHM@100MHZ12

TP13

TP29

C26

0.1UF

T1DNP

C30

0.1UFL1

100 OHM@100MHZ12

C31

0.1UF

C25

0.01UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RESET

Board ID

LT1129-3.3V

JTAG

On Board OSBDM/Serial Bridge

JM60 BDM

JM60Bootload Enable

RXD Source Select

POWER ON

TXD Destination Select

KEY - PIN 7

MANUALRESET

Board Rev

Default: no shunt

(Disable Bootload)

Default: no shunt(Disconnect Target Power)

Place R137 and R138 as close aspossible TOGETHER and close to U53

PTD0

PTD1

PTD1

PTD0

TMS

TCK/EZP_CLK

TDI/EZP_DI/FTM0_CH6

TDO/EZP_DO

TDO

TMS

TCK/EZP_CLK

TDO/EZP_DO

TDI/EZP_DI/FTM0_CH6

VTRG_IN

VTRG_IN

BRD_REV0

BRD_REV1

BRD_REV2

TRESET_OUT

TRESET_IN

TXD_RXD_EN_B

TRESET_IN

OUT_EN_B

T_RXD1

DIN

OUT_EN_B

BRD_ID0

BRD_ID1

BRD_REV0

BRD_REV1

BRD_REV2

T_TXD1

T_RXD1

TCLK_EN

DIN

DOUT

SCLK_OUT

5V_FAULT

VTRG_FAULT

TXD_RXD_EN_B

OUT_EN_B

TRACED3\ULPI_DIR

TRACED2\ULPI_NXT

TRACED1\ULPI_STP

TRACE_D0/ULPI_DATA0

UART2_TX

TRESET_OUT

T_TXD1

TXD_RXD_EN_B

BRK_TMS

OUT_EN_B

DOUT

TCLK_EN

SCLK_OUT

5V_EN

VTRG_EN

BRD_ID0

BRK_TMS

BRD_ID1

EZP_CS_B/TSI0_CH5

TMS

5V_EN

VTRG_EN

VTRG_EN

5V_EN

VTRG_FAULT

5V_FAULT

UART2_RX

JM25JM25

JM33

JM15

USB_PWR

JM12

JM15

RST_BDJM40JM40

EZP_CSR_B

JM41JM41

RS

TR

USB_DNUSB_DN

BRDG_RXD

JM23JM23

PTA3

JM24JM24

JM14

JM24

JM8

PTA0PTA0

JM23JM23

JM26

JM[1..44]

JM24JM24

JM21

JM22

JM34

PTA3

PU_ST

JM60_IRQ_B

JM11

JM13

PU_TP

USB_DPUSB_DP

PU_PO_LED

JM26JM26

ELE_PS_B

JM

60_R

ES

ET

_B

JM1

JM23

JM21JM22

JM29JM29JM30JM30JM33JM33

JM1JM1

JM8JM9

USB_VBUSUSB_VBUS

JM11

JM28JM28

JM29

JM30

JM60_DNJM60_DP

JM14

JM12JM13

JM9

JM42JM42

PTA10PTA10

PTA7PTA7PTA8PTA8PTA9PTA9

JM34

JM15

PTA0PTA0

RESET_BPTA1PTA2

JM27JM27

VUSB3V3

PU2PU2

P5V_TRG_USB

ELE_PS_SENSE

JM25

JM41JM42

RESET_B

PU1

PTA3PTA3

PTE16

JM60_EXTAL

PU3PU3

JM27

JM40

PU5PU5

JM60_XTAL

JM28JM28

PU4PU4

OUT_EN

RTS

JM_BKGD

PTA2PTA2

PTA1PTA1

JM34

JM15

BRDG_TXD

PTE17

TRACE_CLKOUT/ULPI_CLKTGT_PWR

USB-SHLD

PTA6PTA4

RESET_B

PTA[0..29]{4,8,9}

PTE[0..28]{4,7,8,9}

RESET_B {4,8,9}

P5V_USB

P5V_SWP3V3

P3V3

P5V_TRG_USBP3V3_MCU

P5V_USB

P5V_SWP5V_USB

P3V3

P5V_USB

P3V3

P3V3

P3V3_MCU

P5V_USB

P3V3

P5V_USB

P3V3

P5V_TRG_USB

P5V_SW

P3V3

P5V_ELEV {8}

ELE_PS_SENSE{8}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


USB/OSBDM/VTRAN/PWR

6 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


USB/OSBDM/VTRAN/PWR

6 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


USB/OSBDM/VTRAN/PWR

6 11

___ ___X

R26

10.0K

R41 33

C39

10UF

C2710UF

J14

HDR_2X3

1 23 4

65

TP17

U8

MC9S08JM60CLD

PTC41

IRQ/TPMCLK2

RESET3

PTF0/TPM1CH24

PTF1/TPM1CH35

PTF4/TPM2CH06

PTF5/TPM2CH17

PTE0/TxD18

PTE1/RxD19

PTE2/TPM1CH010

PTE3/TPM1CH111

PTE4/MISO112

PTE5/MOSI113

PTE6/SPSCK114

PTE7/SS115

VD

D1

16

VS

S1

17

USBDN18

USBDP19

VUSB3320

PTG0/KBIP021

PTG1/KBIP122

PTB0/MISO2/ADP023

PTB1/MOSI2/ADP124

PTB2/SPSCK2/ADP225

PTB3/SS2/ADP326

PTB4/KBIP4/ADP427

PTB5/KBIP5/ADP528

PTD0/ADP8/ACMP+29

PTD1/ADP9/ACMP-30

VD

DA

D/V

RE

FH

31

VS

SA

D/V

RE

FL

32

PTD2/KBIP2/ACMPO33

PTG2/KBIP634

PTG3/KBIP735

BKGD/MS36

PTG4/XTAL37

PTG5/EXTAL38

VS

SO

SC

39

PTC0/SCL40

PTC1/SDA41

PTC242

PTC3/TxD243

PTC5/RxD244

R33

10.0K

D2

ORANGE

AC

C38

0.1UF

VBUS

D-

D+

ID

G

USB_MINI_B 5

J13

1

2

3

4

S2

5

S1

S3

S4

C34

0.1UF

R78 10M

R15330

R76

10.0K

R38

18K

C8

18PF

R75

10.0K

R80

10.0K

C43

1000PF

TP19DNP

U3

MIC2920A-3.3WS

GND

2

OUTPUT3VIN

1TAB

4

R40 4.99K

U4C

SN74LVC04APWE4

5 6

J10HDR 1X2 TH

12

C420.1UF

C130.1UF

R27

10.0K

U4E

SN74LVC04APWE4

11 10

TP14DNP

R82

10.0K

U6C

74HCT125

98

10

C44

0.1UF

U7

SP0503B

4

1

2 3

D4 YEL/GRN

STATUS

AC

R16 1.0K

J12

HDR 1X2 TH

12

R42 33

C15

0.1UF

D5

YEL/GRN

AC

C11

10UF

R70

10.0K

SW3

PB switch

1 4

2 3

R1

Q3

PDTC115T

3

2

1

C14

0.1UF

BAT54CD9

3

1

2

R37

10.0K

D10

MSS1P3L

A C

C37

0.1UF

U9

74LVC125

1OE1

1A2

2OE4

2A5

3OE10

3A9

4OE13

4A12

1Y3

2Y6

3Y8

4Y11

VC

C14

GN

D7

R36

10.0K

R3110.0K

DNP

L2

330 OHM

1 2

R34

10.0K

R39

0

Y3 4MHz1 2

R30

10.0K

U6D

74HCT125

12 11

13

TP8DNP

D3 LED_YELLOW

TPWR

AC

VCC

GND

U6A

74HCT125

23

14

17

R143 0

R630

R79

10.0K

R72 0DNP

R73

10.0K

U4D

SN74LVC04APWE4

9 8

C33

0.1UF

R74

10.0K

R84

10.0K

VCC

GND

U4A

SN74LVC04APWE4

1 2

14

7

R83 2.2K

C35

10UF

J11

HDR_19P

1 23 4

658

9 1011 1213 1415 1617 1819 20

TP15

R69

10.0K

U6B

74HCT125

56

4

C10

18PF

R650

C9

0.1UF

R137 0DNP

R28

10.0K

R81

10.0K

C12

10UF

R7110.0K

DNP

R17 1.0K

R3210.0K

DNP

R18 270

TP18DNP

R3510.0K

DNP

U4B

SN74LVC04APWE4

3 4

U4F

SN74LVC04APWE4

13 12

C610UF

R29

10.0K

Q2MMBT3904LT1G

23

1

U2

MIC2026-1YM

ENA1

FLGA2

FLGB3

ENB4

OUTB5

GND6

IN7

OUTA8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IRDA

Default: no shunt(Disable IRDA)

I2S SAI HEADER

MICRO SD INTERFACE

Place R212 as close aspossible to U53

NOTE: Don't pushbutton if Flexbus orI2S1 is used

PUSH BUTTON

CMP2_IN3

SDHC0_D0

SDHC0_CMD

I2S0_RX_FS

I2S0_TXD0

I2S0_RX_BCLK

I2S0_MCLK

I2S0_TX_FS

I2S0_RXD0

I2S0_TX_BCLK

pushButton1

Pushbutton0

CMT_IRO

PTD0

PTE26

IRDARIRDA_SEN

PTE6

PTE11PTE7PTE12PTE9

PTE8PTE10

PTE3

PTD7 IRDAJ

PTE28

PTE0PTE1

PTE2

PTE4PTE5

PTE[0..28]{4,6,8,9}

PTD[0..15]{4,8,9,10}

P3V3

P3V3

DAC1_OUT/CMP2_IN3 {4,8}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Peripherals

7 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Peripherals

7 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Peripherals

7 11

___ ___X

SW2

PB switch

14

23

C2

0.01UF

J2HDR 1X2 TH

12

J15

Conn MicroSD

DAT21

CD/DAT32

CMD3

VDD4

CLK5

VSS16

DAT07

DAT18

CD

_S

W9

CD

_C

OM

MO

N10

VS

S2

11

VS

S3

12

VS

S4

13

VS

S5

14

R14

10.0K

J16HDR 1X2 TH

12

C3

0.1UF

Q1QTLP610CPD

12

+

C1

4.7uF

D1

QTLP610CIR

A C

SW1

PB switch

14

23

J6

HDR_2x4

1 23 4

657 8

R12 33

R313

10.0K

R132 0

R13

10.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

***NOTE: EBI bus is equivalent to FB (FLEX BUS) from MCU

Place R11as closeto R137and R138aspossible

Default: 1-2(VBUS enabled)

LCD_HSYNC

LCD_CLK

Notes:Place R107,R108 near to J7BPlace these R, If flow control needs to be tested,and remove R43,R44

LCD_D15

LCD_D16

LCD_D17

LCD_D11

LCD_D10

LCD_D9

LCD_D8

LCD_D7

LCD_D6

LCD_D5

LCD_D4

LCD_D23

LCD_D20

LCD_D21

LCD_D22

LCD_D18

LCD_D19

LCD_D12

LCD_D13

LCD_D14

LCD_D3

LCD_D2

LCD_D1

LCD_D0

LCD_DE

LCD_VSYNC

EBI_AD4

EBI_AD3

EBI_AD2

EBI_AD1

EBI_AD0

EBI_AD5

EBI_AD6

EBI_AD7

EBI_AD8

EBI_AD9

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

EBI_D0

EBI_D1

EBI_D2

EBI_D3

EBI_D4

EBI_D5

EBI_D6

EBI_D7

EBI_OE_B

EBI_R/W_B

EBI_AD19

EBI_AD18

EBI_AD17

EBI_AD16

EBI_AD15

EBI_ALE / EBI_CS1_B

EBI_CS0_B

SD_CARD_DETECT

SPI2_CLK

SPI2_CS1

SPI2_CS0

SPI2_MOSI

SPI2_MISO

TMR2

RTC_CLKOUT

SPI1_SCK

SPI1_PCS0

SPI1_SOUT

SPI1_SIN

ULPI_DATA4

ULPI_DATA3

ULPI_DATA2

ULPI_DATA1

TRST/RMII0_RXER

RMII0_TXEN

RMII0_TXD1

RMII0_TXD0

I2S0_TXD0

I2S0_RXD0

I2S0_TX_FS

I2S0_TX_BCLK

I2S0_MCLK

RMII0_RXD0

RMII0_RXD1

RMII0_CRS_DV

UART2_CTS_B

ULPI_DATA7

ULPI_DATA6

ULPI_DATA5

TRACED3\ULPI_DIR

TRACED2\ULPI_NXT

SPI2_CLK

SPI2_CS1

SPI2_CS0

SPI2_MOSI

SPI2_MISO

TRACE_D0/ULPI_DATA0

TRACED1\ULPI_STP

FTM0_CH5

FTM0_CH4

EBI_CLKOUT

TRACE_CLKOUT/ULPI_CLK

UART3_RX

UART3_TX

FTM1_CH1

FTM1_CH0

GPIO3

I2S0_RX_BCLK

I2S0_RXFS

UART2_RX

UART2_TX

GPIO1/UART2_RTS_B

PTE12

PTB16

PTD2PTD2

PTD1PTD0

PTC4

PTB22

PTE18

PTC14

PTC3

PTE5R

FTM0_CH2 PTC3

PTC5

PTD11

PTE18

P5V_ELEV

CAN1_RX

PTE6

7R

PTD[0..15]

PTB17

PTB21

PTC7

PTC13

PTD13

PTC[0..19]

PTB19

I2C0_SDA PTE18

PTA7

PTE28

PTB10

6R

PTD6

PTE0

I2C0_SCL

PTB9

PTA[0..29]

PTC11

PTB20

PTC12PTD5

CAN1_TX

PTB18

FTM0_CH0

PTC15

PTA9

I2C0_SDA

3R

PTC1

PTE11

PTE2

PTE3PTE4

PTD14

PTB11

PTE0_R

FTM0_CH7R

PTC0

2R

PTD15

FTM0_CH1 PTC2

PTE19

PTB23

I2C0_SCL

1R

PTE7

PTC1

PTA8

PTE10

PTD3

PTD12

PTE19

0R5R

PTC2

PTC6

SD_CARD_WP

ETH_COL

ETH_TXCLKPTA15

ETH_TXERETH_TXD3ETH_TXD2

PTA17

PTE28

PTA16

PTC8PTC9PTC10

PTA6

PTB1PTB0

PTA14

PTA13

PTA12

ETH_RXCLK

ETH_RXD3

ETH_CRS

ETH_RXD2

PTD6

PTD4

PTE17

PTA2

FTM0_CH6RPTA1PTD5

PTE[0..28]

PTA5

PTE1PTE27

PTB8

PTB5

PTB4

IRQ2

PTB6 IRQ3

PTB7 IRQ4

PTF0

PTF25

PTF7

PTF1

PTF26

PTF4

PTF2PTF3

PTF24

PTF7PTC16PTC17 PTF8

PTE16

4R

IRQ1

PTB5

PTB4

PTB6 IRQ3PTB7 IRQ4

PTE5

RSTOUT_B

RMII0_MDC/MII0_MDCRMII0_MDIO/MII0_MDIO

PTE9USB0_VBUS

PTE8

PTE9PTE8I2S0_RXD1

I2S0_TXD1

FTM0_CH3

PTC18 LCD_CONTRAST

PTE26

PTB[0..23]

PTA7

PTA28

PTA8

PTA27

I2C0_SCL

PTF27

PTF21PTF20PTF19

PTF15PTF14PTF13

PTF10

PTF12PTF11

PTF8PTF9

PTA11PTA24

PTA26

PTA9PTA6

PTE19I2C0_SDA PTE18

PTA10

PTA25

PTD12PTD15PTD11PTD13PTD14

IRQ2

PTF18

PTF16

PTF23PTF22

PTF17

PTF6PTF5

PTB8

IRQ1

PTF[0:27]

PTE19

PTA29

PTA[0..29]{4,6,9}

PTB[0..23]{4,9,10}

PTC[0..19]{4,9,10}

PTF[0:27]{4}

PTE[0..28]{4,6,7,9}

PTD[0..15]{4,7,9,10}

RESET_B

{4,6,9}

P3V3

VSSA

P3V3

VDDA

P3V3P3V3

ADC0_DP0 {4,9}

USB0_DN {4}USB0_DP {4}

ADC0_DM0 {4,9}

ELE_PS_SENSE{6,8} ELE_PS_SENSE{6,8}

ADC1_DP0 {4,9}ADC1_DM0 {4}

P5V_ELEV{6}

VREGIN {5}

DAC0_OUT {4}DAC1_OUT/CMP2_IN3{4,7}

ADC0_DP1{4,9}ADC0_DM1{4,9}ADC1_DP1{4,9}ADC1_DM1{4,9}

CLKIN0{4}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Elevator Connector

8 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Elevator Connector

8 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Elevator Connector

8 11

___ ___X

R1150

R141 0 DNP

R480

R139 0

TP4 DNP

R980

R460

TP10 DNP

TP2DNP

TP11 DNP

R62 0

R106 0DNP

TP3 DNP

R500R510

R490

R970

R22 0DNP

R142 0 DNP

R470

R1340 DNP

R23 0DNP

R1000

R1040

TP12DNP

R1090 DNPR440

R5 0DNP

R1350 DNP

R9 0

R101 0

SECONDARYPCI EXPRESS TOWER SYSTEM

J7B

5V_3D1

GND_17D2

3.3V_8D3

ELE_PS_SENSE_2D4

GND_18D5

GND_19D6

SPI2_CLKD7

SPI2_CS1D8

SPI2_CS0D9

SPI2_MOSID10

SPI2_MISOD11

ETH_COL_2D12

ETH_RXER_2D13

ETH_TXCLK_2D14

ETH_TXEN_2D15

GPIO18D16

GPIO19/SDHC_D4D17

GPIO20/SDHC_D5D18

ETH_TXD1_2D19

ETH_TXD0_2D20

ULPI_NEXT/USB_HS_DMD21

ULPI_DIR/USB_HS_DPD22

UPLI_DATA5/USB_HS_VBUSD23

ULPI_DATA6/USB_HS_IDD24

ULPI_DATA7D25

GND_20D26

LCD_HSYNC/LCD_P24D27

LCD_VSYNC/LCD_P25D28

AN13D29

AN12D30

GND_21D31

LCD_CLK/LCD_P26D32

TMR11D33

TMR10D34

GPIO21D35

3.3V_9D36

PWM15D37

PWM14D38

PWM13D39

PWM12D40

CAN2_RXD41

CAN2_TXD42

LCD_CONTRASTD43

LCD_OE/LCD_P27D44

LCD_D0/LCD_P0D45

LCD_D1/LCD_P1D46

LCD_D2/LCD_P2D47

LCD_D3/LCD_P3D48

GND_22D49

GPIO23D50

GPIO24D51

LCD_D12/LCD_P12D52

LCD_D13/LCD_P13D53

LCD_D14/LCD_P14D54

IRQ_P/SPI2_CS2D55

IRQ_O/SPI2_CS3D56

IRQ_ND57

IRQ_MD58

IRQ_LD59

IRQ_KD60

IRQ_JD61

IRQ_ID62

LCD_D18/LCD_P18/SD_RX_0+D63

LCD_D19/LCD_P19/SD_RX_0-D64

GND_23D65

EBI_AD20/LCD_P42/SD_GNDD66


EBI_AD22/LCD_P44/SD_RX_1+D68

EBI_AD23/LCD_P45/SD_RX_1-D69









LCD_D20/LCD_P20/SD_GNDD78

LCD_D21/LCD_P21/SD_REFCLK+D79

LCD_D22/LCD_P22/SD_REFCLK-D80

GND_24D81

3.3V_10D82

5V_4C1

GND_25C2

3.3V_11C3

3.3V_12C4

GND_26C5

GND_27C6

I2C2_SCLC7

I2C2_SDAC8

GPIO25C9

ULPI_STOPC10

ULPI_CLKC11

GPIO26C12

ETH_MDC_2C13

ETH_MDIO_2C14

ETH_RXCLK_2C15

ETH_RXDV_2C16

GPIO27/SDHC_D6C17

GPIO28/SDHC_D7C18

ETH_RXD1_2C19

ETH_RXD0_2C20

ULPI_DATA0/I2S1_MCLKC21

ULPI_DATA1/I2S1_DOUT_SCKC22

ULPI_DATA2/I2S1_DOUT_WSC23

ULPI_DATA3/I2S1_DIN0C24

ULPI_DATA4/I2S1_DOUT0C25

GND_28C26

AN11C27

AN10C28

AN9C29

AN8C30

GND_29C31

GPIO29/UART2_DCDC32

TMR9C33

TMR8C34

GPIO30/UART3_DCDC35

3.3V_13C36

PWM11C37

PWM10C38

PWM9C39

PWM8C40

UART2_RXD/TSI0C41

UART2_TXD/TSI1C42

UART2_RTS/TSI2C43

UART2_CTS/TSI3C44

UART3_RXD/TSI4C45

UART3_TXD/TSI5C46

UART3_RTS/CAN3_RXC47

UART3_CTS/CAN3_TXC48

GND_30C49

LCD_D4/LCD_P4C50

LCD_D5/LCD_P5C51

LCD_D6/LCD_P6C52

LCD_D7/LCD_P7C53

LCD_D8/LCD_P8C54

LCD_D9/LCD_P9C55

LCD_D10/LCD_P10C56

LCD_D11/LCD_P11C57

I2S1_DIN_SCKC58

I2S1_DIN_WSC59

I2S1_DIN1C60

I2S1_DOUT1C61

LCD_D15/LCD_P15C62

LCD_D16/LCD_P16/SD_GNDC63


GND_31C65

EBI_BE_32_24/LCD_P28/SD_TX_0+C66

EBI_BE_23_16/LCD_P29/SD_TX_0-C67

EBI_BE_15_8/LCD_P30/SD_GNDC68

EBI_BE_7_0/LCD_P31/SD_GNDC69

EBI_TSIZE0/LCD_P32/SD_TX_1+C70

EBI_TSIZE1/LCD_P33/SD_TX_1-C71

EBI_TS/LCD_P34/SD_GNDC72

EBI_TBST/LCD_P35/SD_GNDC73

EBI_TA/LCD_P36/SD_TX_2+C74

EBI_CS4/LCD_P37/SD_TX_2-C75

EBI_CS3/LCD_P38/SD_GNDC76

EBI_CS2/LCD_P39/SD_GNDC77

EBI_CS1/LCD_P40/SD_TX_3+C78

GPIO31/LCD_P41/SD_TX_3-C79


GND_32C81

3.3V_14C82

R450

R6 0R7 0

R102 0

R3 0

R8 0

R105 0

PRIMARYPCI EXPRESS TOWER SYSTEM

J7A

5V_1B1

GND_1B2

3.3V_1B3

ELE_PS_SENSE_1B4

GND_2B5

GND_3B6

SDHC_CLK/SPI1_CLKB7

SDHC_D3/SPI1_CS1B8

SDHC_D3/SPI1_CS0B9

SDHC_CMD/SPI1_MOSIB10

SDHC_D0/SPI1_MISOB11

ETH_COL_1B12

ETH_RXER_1B13

ETH_TXCLK_1B14

ETH_TXEN_1B15

ETH_TXERB16

ETH_TXD3B17

ETH_TXD2B18

ETH_TXD1_1B19

ETH_TXD0_1B20

GPIO1/UART1_RTSB21

GPIO2/SDHC_D1B22

GPIO3B23

CLKIN0B24

CLKOUT1B25

GND_4B26

AN7B27

AN6B28

AN5B29

AN4B30

GND_5B31

DAC1B32

TMR3B33

TMR2B34

GPIO4B35

3.3V_2B36

PWM7B37

PWM6B38

PWM5B39

PWM4B40

CAN0_RXB41

CAN0_TXB42

1WIREB43

SPI0_MISO/IO1B44

SPI0_MOSI/IO0B45

SPI0_CS0B46

SPI0_CS1B47

SPI0_CLKB48

GND_6B49

I2C1_SCLB50

I2C1_SDAB51

GPIO5/SPI0_HOLD/IO3B52

RSRV_B53B53

RSRV_B54B54

IRQ_HB55

IRQ_GB56

IRQ_FB57

IRQ_EB58

IRQ_DB59

IRQ_CB60

IRQ_BB61

IRQ_AB62

EBI_ALE/EBI_CS1B63

EBI_CS0B64

GND_7B65

EBI_AD15B66

EBI_AD16B67

EBI_AD17B68

EBI_AD18B69

EBI_AD19B70

EBI_R/WB71

EBI_OEB72

EBI_D7B73

EBI_D6B74

EBI_D5B75

EBI_D4B76

EBI_D3B77

EBI_D2B78

EBI_D1B79

EBI_D0B80

GND_8B81

3.3V_3B82

5V_2A1

GND_9A2

3.3V_4A3

3.3V_5A4

GND_10A5

GND_11A6

I2C0_SCLA7

I2C0_SDAA8

GPIO9/UART1_CTSA9

GPIO8/SDHC_D2A10

GPIO7/SD_WP_DETA11

ETH_CRSA12

ETH_MDC_1A13

ETH_MDIO_1A14

ETH_RXCLK_1A15

ETH_RXDV_1A16

ETH_RXD3A17

ETH_RXD2A18

ETH_RXD1_1A19

ETH_RXD0_1A20

I2S0_MCLKA21

I2S0_DOUT_SCKA22

I2S0_DOUT_WSA23

I2S0_DIN0A24

I2S0_DOUT0A25

GND_12A26

AN3A27

AN2A28

AN1A29

AN0A30

GND_13A31

DAC0A32

TMR1A33

TMR0A34

GPIO6A35

3.3V_6A36

PWM3A37

PWM2A38

PWM1A39

PWM0A40

UART0_RXA41

UART0_TXA42

UART1_RXA43

UART1_TXA44

VSSAA45

VDDAA46

CAN1_RXA47

CAN1_TXA48

GND_14A49

GPIO14A50

GPIO15A51

GPIO16/SPI0_WP/IO2A52

GPIO17A53

USB0_DMA54

USB0_DPA55

USB0_IDA56

USB0_VBUSA57

I2S0_DIN_SCKA58

I2S0_DIN_WSA59

I2S0_DIN1A60

I2S0_DOUT1A61

RSTINA62

RSTOUTA63

CLKOUT0A64

GND_15A65

EBI_AD14A66

EBI_AD13A67

EBI_AD12A68

EBI_AD11A69

EBI_AD10A70

EBI_AD9A71

EBI_AD8A72

EBI_AD7A73

EBI_AD6A74

EBI_AD5A75

EBI_AD4A76

EBI_AD3A77

EBI_AD2A78

EBI_AD1A79

EBI_AD0A80

GND_16A81

3.3V_7A82

R61 0

TP5DNP

R10 0

R950

R103 0

R850

R1 0

R110R4 0DNP

R960

J1

HDR 1X2 TH

12

R140 0

R138 0

TP9DNP

R20

R430

R1160

TP6 DNP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ACCELEROMETER

POTENTIOMETER

TOUCH ELECTRODES WITH LEDS

TOUCH PAD TWRPI

GENERAL PURPOSE TWRPI

VREF BYPASS

PTB

PTA

PTD

PTE

PTB

PTA

PTD

I2C0_SDA

I2C0_SCL

SPI2_MOSI

SPI2_CLK

TWRPI_GPIO1

TWRPI_GPIO3

SPI2_MISO

SPI2_CS1_B

TWRPI_GPIO2

TWRPI_GPIO4

TSI0_CH0

TSI0_CH6

TSI0_CH7

TSI0_CH13

TSI0_CH15

TSI0_CH9

TSI0_CH11

TSI0_CH8

TSI0_CH14

TSI0_CH5

TSI0_CH10

TSI0_CH12

IRQ1

IRQ4

TSI0_CH9

TSI0_CH7

TSI0_CH8

TSI0_CH5

TWRPI_GPIO0/IRQ

I2C0_SDA

TWRPI-ADC0

TWRPI-ADC2

TWRPI-ID1

TOUCH TWRPI-ID0

I2C0_SCL

TWRPI-ADC1

TWRPI-ID0

TOUCH TWRPI-ID1

PTB3

PTA4R

PTC2 PTA4

PTB18 PTB19

PTB2R

PTB2

PTB0

PTB3

PTD12

RESET_B

PTD15

PTE26

PTC0

PTA29

PTA4

RESET_B

PTB1

LE

DO

R

PTB2

LE

DG

R

PTA11PTA28

PTD13

PTC1

PTD14

PTB3R

PTB16 PTB17

PTE18

PTB9PTB8

PTA19

PTA10

PTB16

PTB16RLE

DY

R

PTE19

PTB4

PTB4PTB7

ACC_SA0

ACC_BYP

PTE18PTE19

LE

D2R

PTD[0..15]{4,7,8,10}

PTB[0..23]{4,8,10}

PTA[0..29]{4,6,8}

PTC[0..19]{4,8,10}

PTE[0..28]{4,6,7,8}

P3V3

P3V3

VSSA

VDDA

VDDA

P5V_TRG_USB P3V3

P5V_TRG_USB P3V3

VSSA VSSA

P3V3 P3V3 P3V3

P3V3

P3V3

P3V3

P3V3 P3V3

VREFH

VREFL

P3V3

P3V3

P3V3

ADC0_DM1{4,8}

ADC0_DP0{4,8}

RESET_B{4,6,8}

ADC1_DP1{4,8}

ADC0_DP1{4,8}

ADC1_DM1 {4,8}

ADC0_DM0{4,8}

ADC1_DP0{4,8}

ADC1_SE16{4}

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Sensors

9 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Sensors

9 11



Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

TWR-K70F120M

C


Sensors

9 11

___ ___X

J3

CON_2X10

1 23 4

657 89 10

11 1213 1415 1617 1819 20

U5

MMA8451Q

VD

DIO

1

BYP2

VD

D14

GN

D1

5

GN

D2

10

GN

D3

12

NC33

NC88

NC1313

NC1515

NC1616

INT111

INT29

SCL4

SDA6

SA07

J5

CON_2X10

1 23 4

657 89 10

11 1213 1415 1617 1819 20

R21 0

R20

10.0K

D8

LED_YEL + ELECTRODE

AC

1

R59

0

R52

5K

13

2

R57

0

R2510.0K

R19

10.0K

C28

0.1UF

R60

10.0K

DNP

C450.1UF

R68

0

R581.0K

D12

LED2_ELECTRODE

AC

1

R53

10.0K

R77

1.0K

C5

0.1UF

R641.0K

D7

LED_OR + ELECTRODE

AC

1

R66

0

D11

LED_GRN + ELECTRODE

AC

1

R671.0K

C7

0.1UF

R56

10.0K

R99 0

R544.70K

J4

CON_2X10

1 23 4

657 89 10

11 1213 1415 1617 1819 20

C160.1UF

+C21

4.7uF

R554.70K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Note:------Place the DDR2 CLK Termination resistor R337 close the Chips

DDR-2 MEMORIES AND TERMINATIONS

NAND FLASH

Note:Place R342,R343 near to U14 pins

NFC_D15

NFC_D14

NFC_D13

NFC_D12

NFC_D11

NFC_D10

NFC_D9

NFC_D8

NFC_D7

NFC_D6

NFC_D5

NFC_D4

NFC_D3

NFC_D2

NFC_D1

NFC_D0

NFC_ALE

NFC_CLE

NFC_WE

NFC_RE

DDR2_DQ1

DDR2_DQS1

DDR2_ODT

DDR2_DQ2DDR2_DQ3DDR2_DQ4DDR2_DQ5DDR2_DQ6

DDR2_CK

DDR2_DQ7

DDR2_CK_B

DDR2_DQ8DDR2_DQ9

DDR2_DQM0

DDR2_DQ10

DDR2_DQM1

DDR2_DQ11DDR2_DQ12DDR2_DQ13DDR2_DQ14DDR2_DQ15

DDR2_WE_BDDR2_CAS_BDDR2_RAS_B

DDR2_BA0

DDR2_CS_B

DDR2_BA1DDR2_BA2

DDR2_DQ0

DDR2_DQS0

DDR2_CK

DDR2_CK_B

DDR2_RAS_B

DDR2_CAS_B

DDR2_BA1

DDR2_BA2

DDR2_CS_B

DDR2_CKE

DDR2_WE_B

DDR2_ODT

DDR2_CKE

PTC1PTC0

NFC_WP_B

PTB23

PTC11

PTB22PTB21PTB20

PTD5PTD4

PTC10PTC9PTC8PTC7PTC6PTC5

NFC_CE_B

PTC4PTC2

DDR2_ADD4DDR2_ADD5DDR2_ADD6DDR2_ADD7DDR2_ADD8DDR2_ADD9DDR2_ADD10DDR2_ADD11DDR2_ADD12

DDR2_ADD0DDR2_ADD1DDR2_ADD2DDR2_ADD3

PTD10

PTD8PTD9

NFC_R/B_N

DDR2_BA0

PTC16

PTC17

PTC16PTC17

PTC11

PTC1PTC0

PTC10PTC9PTC8PTC7PTC6PTC5PTC4PTC2

PTD10PTD9PTD8

PTD5PTD4

PTB23PTB22PTB21PTB20

PTC[16:17]{4,8}PTD[8:10]{4}

PTD[4:5]{4,8}PTC[0:11]{4,8,9}

PTB[20:23]{4,8}

P3V3

P3V3

VREF_DDR2 VDD_1V8

VTT_DDR2

VDD_1V8

VDD_1V8

VTT_DDR2

DDR2_DQM0{5}

DDR2_WE_B{5}

DDR2_DQM1{5}

DDR2_CAS_B{5}DDR2_RAS_B{5}

DDR2_CK_B{5}

DDR2_BA1{5}DDR2_BA2{5}

DDR2_CS_B{5}DDR2_CKE {5}

DDR2_ODT {5}

DDR2_BA0{5}

DDR2_DQS0{5}

DDR2_DQS1{5}

DDR2_CK{5}

DDR2_DQ[15:0] {5}

DDR2_ADD[12:0]{5}

Drawing Title:


Date: Sheet of

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SCH-27166 PDF: SPF-27166 C2

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DDR2 SDRAM, NAND FLASH

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10 11

___ ___X

C82

0.01UFC47

0.1UFU14

MT29F2G16ABAEAWP:E

I/O029

I/O130

I/O231

I/O332

I/O441

I/O542

I/O643

I/O744

RE8 CE9

CLE16

ALE17

WE18

WP19

VC

C1

12

VC

C3

37

VS

S1

13

VS

S3

36

R/B7

NC66 NC55 NC44

NC1010

NC1414

NC1515

NC11

NC22

NC33

NC1111

NC2020

NC2121

NC2222

NC2323

NC2424

VS

S2

25

I/O826

I/O927

I/O1028

I/O1133

VC

C2

34

NC3535

NC3838

VC

C4

39

I/O1240

I/O1345

I/O1446

I/O1547

VS

S4

48

R310 10.0K

R337

100

C61

0.1UF

R128

4.7K

R311 10.0K

C62

0.1UF

C48

0.1UF

R317 10.0K

R326

10.0K

DNP

C49

0.1UF

R118

4.7K

+

C54

47uF

C760.1UF

R318 10.0K

C50

0.1UF

R327 10.0K

C64

0.1UF

R319 10.0K

C51

0.1UF

C65

0.1UF

C87

0.1UF

C86

0.1UF

C66

0.1UF

C56

0.1UF

R325 10.0K

C63

0.1UF

C67

0.1UF

R343 0 R130 4.7K

C52

0.1UF

DDR2 MEMORY

MT47H64M16HR-25:H

U10

DQ6F1

DQ4H1

DQ9C2

DQ1G2

VR

EF

J2

CKEK2

BA0L2

A10/APM2

A3N2

A7P2

A12R2

UDMB3

DQ11D3

LDMF3

DQ3H3

A1M3

A5N3

A9P3

UDQSB7

DQ10D7

LDQSF7

DQ2H7A2

M7

A6N7

A11P7

UDQSA8

DQ8C8

LDQSE8

DQ0G8

CKK8

A0M8

A4N8

A8P8

BA2L1

DQ7F9

DQ5H9

ODTK9

DQ12D1

DQ13D9

DQ14B1

DQ15B9

NC5R8

NC4R3

NC3R7

NC2E2

NC1A2

BA1L3

CSL8

WEK3

CASL7

RASK7

CKJ8

VD

D1

A1

VD

D2

E1

VD

D3

R1

VD

D4

M9

VD

D5

J9

VD

DQ

1C

1

VD

DQ

2G

1

VD

DQ

3C

3

VD

DQ

4G

3

VD

DQ

5C

7

VD

DQ

6G

7

VD

DQ

7A

9

VD

DQ

8C

9

VD

DQ

9E

9

VD

DQ

10

G9

VD

DL

J1

VS

SQ

2D

2

VS

SQ

3F

2

VS

SQ

4H

2

VS

SQ

5A

7

VS

SQ

6E

7

VS

SQ

7B

8

VS

SQ

8D

8

VS

SQ

9F

8

VS

SQ

10

H8

VS

S1

N1

VS

S2

A3

VS

S3

E3

VS

S4

J3

VS

S5

P9

VS

SQ

1B

2

VS

SD

LJ7

C88

0.1UF

C57

0.1UF

C68

0.1UF

C53

0.1UF

C58

0.1UF

R336 10.0K

C55

0.1UF

C69

0.1UF

C46

0.1UF

R306 10.0K

C59

0.1UF

C70

0.1UF

R342 0

C60

0.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR-2 TERMINATION REG (3A)

Place C135 next to pins 21 and22, C136 next to pins 9 and 10,C137 next to pin 23 of U56

P3V3

VDD_1V8

VREF_DDR2

VTT_DDR2

Drawing Title:


Date: Sheet of

Page Title:


SCH-27166 PDF: SPF-27166 C2

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DDR Termination & Power

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C133

47uF

R341 210.0K

C136

47uF

C134

47uF

C137

1UF

U56

LTC3618

PV

IN2_2

10

SG

ND

8

FB11

FB25

PHASE4 MODE/SYNC3

ITH12

VDDQIN7

PGOOD118

VTTR17

TRACK/SS124

PG

ND

25

PV

IN1_1

21

PV

IN1_2

22

SV

IN23

ITH26

PV

IN2_1

9

RUN213 RUN114 RT15

PGOOD216

SW2_111

SW2_212

SW1_119

SW1_220

L9

0.47uH1 2

C79

0.1UF

L10

0.47uH1 2

R339

422.0K

C135

47uF

Freescale Semiconductor Inc. Microcontroller Solutions Group

TWR-K70FN1M Tower Module Schematic Executive Summary

Rev. 0.2

TWR-K70F120M Executive Summary Page 2 of 12

Revision History

Revision Author Date Changes

0.1 MH 06/28/2013 Preliminary version

0.2 MH 07/19/2013 First release


1 Purpose

The purpose of this document is to provide a written overview of the TWR-K70F120M board. The schematic source, BOM, layout, and other design files are all available for download from the Freescale website (TWR-K70F120M-PWB). The schematics and board design package are useful for reference, but notes embedded in the schematic are not sufficient to document important items and explain design decisions. This document will walk through the schematic for the TWR-K70F120M rev C2 board page by page providing explanation for connections on the board and pointing out design rules and tips.

1 Abbreviations

This summary will refer to components using the reference designators in the schematics. The beginning letters or letters identify the type of components as follows:

C = Capacitor ex: C1 D = LED ex: D1 J = Connector (male) ex: J1 P = Plug (female) ex: P1 R = Resistor ex: R1 T = Transformer ex: T1 U = Device ex: U1 Y = Crystal ex: Y1 RP = Resistor pack ex: RP1 SW = Switch ex: SW1 TP = Test point ex: TP1 DNP = Do not populate. There is a footprint present on the board for the component, but it is not installed on the board.

2 Schematic Page 1 – Table of Contents and Revision History

3 Schematic Page 2 - Notes

In addition to some notes on units and signal nomenclature, this page provides a list of the power and ground nets used in the design. This includes the nominal voltage for each rail and a brief description of the usage.


4 Schematic Page 3 - Unused

5 Schematic Page 4 – K70 Processor (Non-DDR signals)

This page is the first part of the symbol for the K70 processor. In general most of the signals are routed to buses or other off page connectors so that the signal names can be references for making connections to circuitry on other pages of the schematic.

5.1 Clocks There are three clock inputs available on the K70 processor, all of which have circuitry on this page of the schematic.

TIP: All signals on your board should be properly coupled to a plane with enough distance between traces to make sure the traces couple to planes instead of each other. This is particularly important for clock signals, so pay special attention to the layout of all clock traces.

5.1.1 EXTAL0/EXTAL_MAIN

The circuit in the lower, left hand side of this page provides the primary clock input to the processor on the EXTAL0 pin (EXTAL_MAIN net). This board is designed to support an RMII Ethernet connection. In order to support RMII, the 50MHz clock used for the Ethernet PHY must also be routed to the processor on EXTAL0. For the tower system, a TWR-SER or TWR-SER2 card configured for RMII operation would drive the 50 MHz PHY clock on the CLKIN0 net shown here. Because the tower needs to run in stand-alone mode (no other tower cards present), there is also an option to use an on-board 50 Mhz oscillator to provide the main input clock. Jumpers (J18 and J19) and/or 0 ohm resistor population options (R94 and R122) can be used to select between the two clock sources. In order to support the flexibility of the tower system, the circuit here is more complicated than what would be used in a typical end system where the input clock would usually come from a single, fixed source.

TIP: Keep in mind that if RMII is being used the EXTAL0 input must be 50 MHz and the clock trace length should be setup so that the clock reaches the Ethernet PHY and processor at the same time. Skew between the two clocks could result in timing violations on the RMII signals.


5.1.2 EXTAL1/XTAL1

The K70 supports a secondary high frequency clock input on the EXTAL1/XTAL1 pins. The Kinetis Peripheral Module Quick Reference document (KQRUG) available from the Freescale website, contains useful information and board layout guidelines for crystal circuits. Please refer to “Section 2.1.3.3 Oscillators” in the KQRUG for more information.

TIP: OSC1 can be used as the reference clock source for one or both of the PLLs, but there are some restrictions on its use. The following items should be taken into account if you are considering using OSC1 as the main clock input on your board:

Either OSC0 or OSC1 can be used as the reference clock source for the PLL being used as MCGCLKOUT.

Only OSC0 or the RTC OSC can be used as the FLL reference clock so one of those clock sources MUST be available to the MCG if using FEE, FBE, or BLPE clock modes or when transitioning from the reset default FEI mode to PBE mode (or any “external” clocked MCG mode). You must transition through FBE mode to enter PEE mode and use the PLL as the MCGCLKOUT source.

If OSC1 is to be used it must be configured in MCG_C10 and enabled in OSC1_CR.

If OSC1 is the only external clock source then the only MCG clock modes available are FEI, FBI and BLPI.

5.1.3 EXTAL32/XTAL32

The final clock is the 32 kHz oscillator. This input is primarily used as the reference clock for the real-time clock (RTC), but in some modes it can be used as the main reference for the entire processor. The schematic includes loading capacitors and a resistor for the crystal circuit (C77, C78, and R93), but these components are not populated (DNP). The loading caps are not required because the K70’s internal oscillators include programmable loading caps up to 30pF. In this case the internal loading caps can be used, and so the external caps are not necessary.

5.2 USB In order to maximize the eye for the USB signals, it is important that the on-chip FS/LS transceiver signals (USB0_DP and USB0_DM) include 33 ohm series termination resistors. These resistors need to be placed as close to the processor as possible. The USB signals should also be routed as a 90 ohm differential pair.


6 Schematic Page 5 - K70 Processor (DDR signals and Power)

This page is the second and final part of the symbol for the K70 processor. This portion of the symbol includes all of the power and ground signals for the processor and the signals for the DDR memory interface. The DDR signals will be discussed later on the DDR memory page.

6.1 DDR_VDD The DDR_VDD pins are used to power the I/O pads for the DDR signals. This net can be 1.8V or 2.5V nominal depending on the type of memory being used. 1.8V is used for DDR2 or LPDDR1. 2.5V is used for DDR1. The TWR-K70F120M uses DDR2 memory, so DDR_VDD is 1.8V nominal.

6.2 DDR_VREF The DDR_VREF net is actually not used as a reference for the DDR pads on the processor. The DDR2 memory on the TWR-K70F120M does require DDR_VREF, so there is a special regulator included to generate this voltage (on page 11). For DDR1 and DDR2 designs, the DDR_VREF net can be tied to the VREF used for the memory. For LPDDR1 designs, the memory does not need VREF, so the DDR_VREF net on the processor can be tied to VDD_DDR. A midpoint VREF voltage is not required.

6.3 VDD_INT In order to allow for reduction of power without affecting the I/O rails, the K70 includes VDD_INT pins. The VDD_INT pins are used to supply power to the internal logic on the chip. J20 is provided so that the current draw on VDD_INT can be measured and/or a different voltage can be used to supply VDD_INT than what is being used for VDD. In a typical design VDD_INT would be connected directly to its power supply circuit or the VDD rail.

6.4 VDD The VDD pins are used to supply the power for the I/O pads on the processor with the exception of the DDR pads and the RTC/tamper pins. J8 is provided so that the current draw on VDD can be measured and/or a different voltage can be used to supply VDD than the 3.3V supply that is provided. In a typical design VDD would be connected directly to the main power supply circuit. Separation of the power into P3V3 and P3v3_MCU nets is not recommended unless there is a specific need for separate nets.


6.5 AVDD/AVSS The AVDD and AVSS pins are the power and ground for the analog blocks on the K70. In order to minimize noise to the analog blocks both AVDD and AVSS are a filtered nets derived from the main VDD and VSS nets for the processor.

6.6 VREGIN The VREGIN pin is the input to the on-chip USB regulator. In this case the USB connector is off-board so the VREGIN net comes from the elevator connectors (page 8). A jumper is supplied so that VBUS can be disconnected and/or a voltage can be supplied directly. For a typical USB device system, VREGIN would be connected to VBUS from the USB plug. The USB connector is subjected to ESD from users plugging/unplugging cables, so some ESD protection on USB signals including VBUS is strongly recommended. For a USB host system, VREGIN would still connect to the USB plug, but as the host needs to supply power a 5V power source on the board would be used to power both VREGIN and the VBUS at the plug. ESD is still an issue for hosts, so again, ESD protection on the USB lines including VBUS is strongly recommended.

TIP: VREGIN is used to provide power to the on-chip FS/LS transceiver. In order to use USB0_DP and USB0_DM VREGIN MUST be powered.

6.7 VOUT33 The VOUT33 pin is the output from the on-chip USB regulator. The USB regulator can supply 3.3V and up to 120mA that can be used as the main power for the processor (VDD) and powering the board. Because the total current for the tower system with peripheral cards plugged in can exceed 120mA, the tower board is not setup to be powered by VOUT33 by default. R88 can be populated to experiment with this feature.

6.8 VBAT The final power domain for the K70 is the VBAT domain. The VBAT powers the RTC, DryIce, and a small register file. On the tower board the VBAT can be powered directly from the same supply as VDD or you can use the coin cell circuit. The diodes in the circuit allow the VBAT to be supplied by P3V3_MCU (VDD) when the net is powered or by the coin cell if the main power is not present. For a typical end application, only one approach is needed, so J17 would be removed and VBAT would be connected as needed for the specific system.


6.9 Decoupling/Bypass caps The exact amount and value of decoupling/bypass caps required for a design will vary. The values used on the tower board should only be used as a reference. The value and quantity of bypass caps needed for your own design will most likely not be the same.

6.10 Test Points The tower board is an evaluation system, so test points, jumpers, headers, and connectors are available on most signals to allow for monitoring and debugging. While some applications might not allow for liberal use of test points and other means of monitoring signals (especially if the application has size constraints), keeping test points on critical signals can make debugging a much smoother process.

7 Schematic Page 6 – OS-BDM/JTAG

This page is the open source JTAG circuit. This on-board debug circuit provides a JTAG debug interface and a power supply input through a single USB mini-B connector. The OS-JTAG also includes a virtual serial port. For most designs inclusion of a full JTAG debugging circuit is not needed. A typical end application would only include a standard ARM JTAG header, and in many cases the header would not be populated on production units. ARM has standards for several different connectors in different form factors. The number of pins and size of the connector can be selected based on design constraints and debugging capability required for the application.

8 Schematic Page 7 – SD Card, IrDA, and Pushbuttons

8.1 SD Card The SDHC module on the K70 can be used with either a full size SD connector or a micro connector. The TWR-K70F120M board has a micro SD card connector. The card detection is done using a GPIO signal. There is an erratum that affects detection of SD card insertion and removal, so use of a GPIO signal for card detection is recommended over using the card detection features of the SDHC module. Refer to device errata e6934 for more information.

8.2 IrDA The TWR-K70F120M includes an IR transmitter and receiver. The PTD7 pin was selected for the IR transmitter specifically because there is an option in the processor for extra drive capability on this pin. The PDT7 pin is double bonded to two pads within the package, so it can be configured for dual-pad drive strength. This setting is configured using the SIM_SOPT2[CMTUARTPAD] bit.


8.3 Pushbuttons There are two simple pushbuttons included on the board for use as general inputs to control an application. The signals used for the pushbuttons were selected to minimize conflicts with other functions of the pins being used elsewhere on the board. In general all GPIO pins have the same functionality, so any free GPIO would be suitable for use as a pushbutton input. Keep in mind that there is only one interrupt line per GPIO port, so when possible try to use GPIOs from different ports if interrupt capability is needed. This will prevent/reduce the need for polling inside of the interrupt handler to determine the specific pin that triggered the interrupt.

9 Schematic Page 8 – Elevator Connectors

While the TWR-K70F120M is designed so that it can be used by itself, the functionality of the board can be expanded by building a tower comprised of the MCU card and peripheral cards. The tower peripheral card schematics are useful references to see how peripheral circuitry that is not included on the main MCU card can be connected to the processor. The backside of the elevator connectors provide excellent access to all Tower card signals to assist with hardware debugging. Note that the Kinetis K70 is highly integrated and uses signals on the secondary elevator card where many lower end devices do not.

10 Schematic Page 9 – Sensors

10.1 TWRPI connectors In addition to adding tower peripheral boards, the tower functionality can also be expanded by adding tower system plug-in boards (TWRPIs). Like the tower peripheral cards, TWRPI boards can be a good reference to see how various sensors and other devices can be connected to the processor.

10.2 Sensors The TWR-K70F120M includes an accelerometer and touch electrodes with LEDs. The accelerometer communicates with the processor using an I2C interface. The I2C bus is designed as a multi-master/multi-slave bus, so the same I2C bus used to communicate with the accelerometer is also used for the TWRPI and the elevator connectors. The touch electrodes used on the tower board are simple rectangular electrodes with a small hole in the middle so that an LED can be populated under the board to shine through the electrode. A large variety of electrode patterns and arrangements can be supported. Refer to AN3863 “Designing Touch Sensing Electrodes” for more examples and hardware guidelines for touch electrodes.


11 Schematic Page 10 – DDR and NAND

11.1 DDR2 The K70 includes an SDRAM controller that supports DDR2, LPDDR1, and DDR1. The tower board uses DDR2 memory, but in general the rules for connecting any of the three memory types are the same. Making the schematic connections for the memory is simple, but the layout can be tricky.

11.1.1 DDR Layout Recommendations

Try to minimize the overall trace lengths. The DDR should be placed as close to the processor as possible.

The data, DQS, and DQM signals for each byte lane should be matched. Ex: DDR_DQ[7:0], DDR_DQS0, and DDR_DM0 should be matched.

Data bits can be swapped to make layout simpler, but any data line swaps must be within the same byte lane. You can swap DDR_DQ0 and DDR_DQ1, but not DDR_DQ0 and DDR_DQ8.

The address and command signals should be matched--DDR_A[14:0], DDR_BA[2:0], DDR_CK, /DDR_CK, /DDR_CAS, /DDR_CS, /DDR_RAS, /DDR_WE, and DDR_ODT (if used).

DDR_CK and /DDR_CK should be routed as a pair.

11.1.2 DDR Simulation

Freescale recommends using your board layout file, the processor IBIS model, and the memory IBIS model to perform signal integrity simulations of DDR signals whenever possible. These simulations are the best means of determining if termination resistors are required on any of the DDR lines before spinning a board.

11.1.3 Terminations

The exact terminations required for the DDR signals can vary depending on your specific board and the type of DDR that is being used. For many designs, especially if the overall DDR trace lengths are short (recommended less than 2 inches), terminations might not be required at all. NOTE: LPDDR1 designs should never need any parallel terminations. For longer trace lengths series terminations might be needed. All parallel DDR termination resistors consume power, so elimination of external termination resistors is desired whenever possible. In addition to reducing power, removing parallel terminations also simplifies the BOM and the board layout. DDR1 designs might require parallel terminations on all signals (both data and address/control). DDR2 designs can make use of on-die terminations for the data, DQS, and DQM signals, so if parallel terminations are needed they would only be used on the address and control signals.

TIP:


Keep the overall trace lengths short should be one of the key goals for the DDR layout. If the trace lengths are short, then the design most likely won’t need any external termination resistors.

11.2 NAND The K70 includes an on-chip NAND flash controller. The NAND signals are shared with the FlexBus interface; however, the processor can switch between functions dynamically. This means that a board can use the FlexBus and NAND with no pin conflicts, but you cannot access memories or devices on the FlexBus and the NAND simultaneously.

12 Schematic Page 11 – DDR Regulator

Use of a regulator specially designed to supply Vref and Vtt voltages is recommended for any DDR design that requires parallel terminations. Designs that do not require a Vtt voltage for parallel terminations can use a voltage divider circuit like the following:

TIP: Never use the Vref net for parallel termination resistors. It is important to have very little noise on the Vref as this voltage reference is used by the DDR1 or DDR2 memory to determine if a signal is high or low.


The current draw through the parallel terminations will cause the Vref voltage to move and can cause signals to be incorrectly sampled by the memory.

table of contents revisions 1 toc/revision history rev … · 2016-11-01 · table of contents...

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