×
Log in
Upload File
Most Popular
Study
Business
Design
Technology
Travel
Explore all categories
The top documents tagged [global wire]
Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
33 views
High-Speed and Low-Power On-Chip Global Link Using Continuous-Time Linear Equalizer
34 views
High-Speed and Low-Power On-Chip Global Link Using Continuous-Time Linear Equalizer Yulei Zhang 1, James F. Buckwalter 1, and Chung-Kuan Cheng 2 1 Dept
214 views
EEWeb Pulse - Issue 72
221 views
EEWeb Pulse - Issue 72
218 views
Wire Bulletin - Jan 11
234 views