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The top documents tagged [leakage power variation]
Low-power FinFET Circuit Design Niraj K. Jha Dept. of Electrical Engineering Princeton University Joint work with: Anish Muttreja and Prateek Mishra
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Jan 4-8, 2008 VLSI Design Conference 1 Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation Yuanlin Lu Intel Corporation,
214 views