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The top documents tagged [leakage power]
Dsa Up Ld 00007101
249 views
Reducing Leakage Power in Peripheral Circuits of L2 Caches Houman Homayoun and Alex Veidenbaum Dept. of Computer Science, UC Irvine {hhomayou, alexv}@ics.uci.edu
214 views
Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University
216 views
Slim crab cavity development Luca Ficcadenti, Joachim Tuckmantel CERN – Geneva LHC-CC11, 5th LHC Crab Cavity Workshop
221 views
Benton H. Calhoun Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 9 Optimizing Power @ Standby Memory
217 views
1 Dynamic thermal clock skew compensation using Tunable Delay Buffers (TDBs) Enrico Macii EDA GROUP POLITECNICO DI TORINO
[email protected]
216 views
Device and architecture co-optimization – Large search space – Need fast yet accurate power and delay estimator for FPGAs Trace-based power and delay
215 views
Software Optimization for Performance, Energy, and Thermal Distribution: Initial Case Studies Md. Ashfaquzzaman Khan, Can Hankendi, Ayse Kivilcim Coskun,
219 views
Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power
215 views
LOW-LEAKAGE REPEATERS FOR NETWORK-ON-CHIP INTERCONNECTS Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel Institute of
219 views
Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn
215 views
1 adaptive body bias for reducing process variations nuno alves 19 / october / 2006
213 views
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