tap controller for cell-based design myrna bussiere, project leader meagan morrell
TRANSCRIPT
TAP Controller for Cell-Based Design
Myrna Bussiere, Project Leader
Meagan Morrell
Purpose
To develop and implement a Test Access Port (TAP) Controller for use in the IEEE 1149.4 Boundary Scan tiny chip testing device
To understand Boundary Scan and to implement test sequences when chip has been fabricated
Topics of Discussion
TAP Controller overview Initial design for digital logic Layout of digital logic using Design
Architect in Mentor Graphics Simulation results from QuickSim
in comparison to expected results Layout of transistor level in IC
Station
TAP Controller Overview
16-State simple finite state machine
Three inputs Nine outputs
TAPController
TCK
TMS
TRST
ClockIR
UpdateIR
ShiftIR
Reset
Select
Enable
ShiftDR
UpdateDR
ClockDR
Initial Design Process
Assigned 4-bit binary codes to each state of the TAP Controller
Produced a state table Karnaugh maps were then derived Simplified Boolean expressions
were found Digital logic design was formed
State Table DiagramTest_Logic Reset
(0000)
Run_Test/Idle(0001)
Select DR_Scan(0010)
Select IR_Scan(1001)
Capture_DR(0011)
Shift_DR(0100)
Exit1_DR(0101)
Pause_DR(0110)
Exit2_DR(0111)
Update_DR(1000)
Capture_IR(1010)
Shift_IR(1011)
Exit1_IR(1100)
Pause_IR(1101)
Exit2_IR(1110)
Update_IR(1111)
0
1
0
1 1 1
0 0
1 1
0 0
00
1 1
1 1
0 0
0 0
1 1
0 0
1 1
1 10 0
Digital Logic Design
Transistor Level of Gates
Transistor Level of D Flip-Flop
Simulation Results
Clock Frequency: 200ns Low Power Consumption
Contains about 450 transistors Total chip allows for 70,000
transistors
Simulation Results
Layout Design Process
Attempted to route manually to save space Too time consuming, and many
errors occurred Used AutoRoute
Optimized space Fast and no errors
IC Station Layout
Layered Layout
Detailed Layer Level
TAP Area Compared to Total Chip Area
Full Projected Layout of Tiny Chip
Summary
The TAP Controller for cell-based design has been successfully designed and laid out using the mentor graphics program
We have also tested it using two methods It has passed both tests successfully
and with no errors
Next Steps
Mach TA Simulation Add one more ABM to full layout Route all sub-components together
in full layout Submission to MOSIS for
fabrication