tas6421-q1 75-w, 2-mhz digital input 1-channel automotive

VDD VCOM VBAT GVDD PVDD

OUT_P

OUT_M

VREG

I2C_ADDR1

I2C_ADDR0

SDA

SCL

I2C Control

SDIN1

SCLK

FSYNC

MCLK

Serial

AudioPort

PLL and Clock

Management

STANDBY

WARN

FAULT

Digital Core

Reference

Regulators

Gate Drive

Regulator

Powerstage

Volume Control -100

to +24 dB,

0.5 dB steps

Gate

Driver

Digital to PWM

Clip

Detection

Closed Loop Class D Amplifier

Overcurrent Limit

Protection

Overcurrent

Overtemperature

Overvoltage and Undervoltage

DC Detection

Short to GND

DC Load Diagnostics

Short to Power

Open Load

Shorted Load

AC Load Diagnostics

MUTE

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS6421-Q1SLOSE32A –APRIL 2019–REVISED OCTOBER 2019

TAS6421-Q1 75-W, 2-MHz Digital Input 1-Channel Automotive Class-D Burr-Brown™Audio Amplifier with Load Dump Protection and I2C Diagnostics

1

1 Features1• Advanced load diagnostics

– DC Diagnostics run without input clocks– AC Diagnostic for tweeter detection with

impedance and phase response• Easily meet CISPR25-L5 EMC specification• AEC-Q100 Qualified for automotive applications

– Temperature grade: –40°C to +125°C• Audio inputs

– I2S or 4/8-channel TDM input– Input sample rates: 44.1 kHz, 48 kHz, 96 kHz– Input formats: 16-bit to 32-Bit I2S, and TDM

• Audio outputs– Single-channel bridge-tied load (BTL)– Up to 2.1 MHz output switching frequency– 27 W, 10% THD Into 4 Ω at 14.4 V BTL– 45 W, 10% THD Into 2 Ω at 14.4 V BTL

• Audio performance Into 4 Ω at 14.4 V BTL– THD+N < 0.02% at 1 W– 42 µVRMS Output Noise– –90 dB Crosstalk

• Load diagnostics with Host-independent operation– Output open and shorted load– Output-to-battery or ground shorts– Line output detection Up to 6 kΩ

• Protection– Output current limiting and short protection– 40 V Load dump– Open ground and power tolerant– Overtemperature warning and shutdown– Undervoltage and overvoltage, DC Offset

• General operation– 4.5 V to 26.4 V supply voltage– I2C control with 4 address options– Clip detection (latching or non-latching)

2 Applications• Automotive head unit and external amplifier• eCall (emergency call)• Virtual engine sound system (VESS)

3 DescriptionTAS6421-Q1 device is a mono-channel digital-inputClass-D Burr-Brown™ audio amplifier thatimplements a 2.1 MHz PWM switching frequencyenabling a cost-optimized solution for a very smallPCB size, full operation down to 4.5 V for start/stopevents, and exceptional sound quality with up to 40kHz audio bandwidth. TAS6421-Q1 is footprint andpin-compatible with TAS642x-Q1 family devices toallow for the flexibility to easily support multiplesystem configurations with minimal redesign effort.

The output switching frequency can be set eitherabove the AM band, which eliminates AM-bandinterferences and reduces output filtering and cost, orbelow the AM band to optimize efficiency. The devicehas a built-in load diagnostic function for detectingand diagnosing misconnected outputs as well asdetection of AC-coupled tweeters.

TAS6421-Q1 provides one channel at 27 W into 4 Ωat 10% THD+N, 45 W into 2 Ω at 10% THD+N from a14.4 V supply or 75 W into 4 Ω at 10% THD+N froma 25 V supply.

For pin compatible two- and four-channel devices seethe TAS6422-Q1, TAS6424L-Q1, TAS6424M-Q1 andTAS6424-Q1.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TAS6421-Q1 HSSOP (56) 18.41 mm × 7.49 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Functional Block Diagram

http://www.ti.com/product/tas6421-q1?qgpn=tas6421-q1

http://www.ti.com/product/TAS6421-Q1?dcmp=dsproject&hqs=pf

http://www.ti.com/product/TAS6421-Q1?dcmp=dsproject&hqs=sandbuy&#samplebuy

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http://www.ti.com/product/TAS6421-Q1?dcmp=dsproject&hqs=support&#community

http://www.ti.com/processors/automotive-processors/overview.html

http://www.ti.com/solution/emergency-call-ecall

http://www.ti.com/solution/virtual-engine-sound-system-vess

http://www.ti.com/product/TAS6422-Q1

http://www.ti.com/product/TAS6424L-Q1

http://www.ti.com/product/TAS6424M-Q1

http://www.ti.com/product/TAS6424-Q1

2

TAS6421-Q1SLOSE32A –APRIL 2019–REVISED OCTOBER 2019 www.ti.com

Product Folder Links: TAS6421-Q1

Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Device Options....................................................... 36 Pin Configuration and Functions ......................... 47 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 67.2 ESD Ratings.............................................................. 67.3 Recommended Operating Conditions....................... 77.4 Thermal Information .................................................. 77.5 Electrical Characteristics........................................... 87.6 Typical Characteristics ............................................ 12

8 Parameter Measurement Information ................ 169 Detailed description............................................. 17

9.1 Overview ................................................................. 179.2 Functional Block Diagram ....................................... 179.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 289.5 Programming........................................................... 299.6 Register Maps ......................................................... 32

10 Application and Implementation........................ 4610.1 Application Information.......................................... 4610.2 Typical Applications .............................................. 47

11 Power Supply Recommendations ..................... 5012 Layout................................................................... 50

12.1 Layout Guidelines ................................................. 5012.2 Layout Example .................................................... 5112.3 Thermal Considerations ........................................ 51

13 Device and Documentation Support ................. 5313.1 Documentation Support ........................................ 5313.2 Receiving Notification of Documentation Updates 5313.3 Community Resources.......................................... 5313.4 Trademarks ........................................................... 5313.5 Electrostatic Discharge Caution............................ 5313.6 Glossary ................................................................ 53

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (April 2019) to Revision A Page

• Changed the device status From: Advanced Information To: Production data ..................................................................... 1


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3

TAS6421-Q1www.ti.com SLOSE32A –APRIL 2019–REVISED OCTOBER 2019


Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Device Options

Part Number ChannelCount

Power-SupplyVoltage Range

ChannelCurrent

Limit (Typ)

Output Power per channel / 10% THD4 Ω / BTL

14.4 V4 Ω / BTL

Max Voltage2 Ω / BTL

14.4 V2 Ω / PBTL

Max VoltageTAS6424-Q1 4 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W 150 W at 25 V

TAS6424M-Q1 4 4.5 V to 18 V 6.5 A 27 W 45 W at 18 V 45 W 80 W at 18 VTAS6424L-Q1 4 4.5 V to 18 V 4.8 A 27 W 45 W at 18 V 27 W 80 W at 18 VTAS6422-Q1 2 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W 150 W at 25 VTAS6421-Q1 1 4.5 V to 26.4 V 6.5 A 27 W 75 W at 25 V 45 W N/A


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1GND 56 PVDD

2PVDD 55 PVDD

3VBAT 54 NC

4AREF 53 NC

5VREG 52 NC

6VCOM 51 NC

7AVSS 50 NC

8AVDD 49 NC

9GVDD 48 BST_P

10NC 47 OUT_P

11GND 46 GND

12MCLK 45 OUT_M

13SCLK 44 BST_M

14FSYNC 43 NC

15SDIN1 42 NC

16GND 41 NC

17GND 40 NC

18GND 39 NC

19VDD 38 NC

20SCL 37 NC

21SDA 36 NC

22I2C_ADDR0 35 NC

23I2C_ADDR1 34 NC

24STANDBY 33 NC

25MUTE 32 NC

26FAULT 31 NC

27WARN 30 NC

28GND 29 NC

Not to scale

Thermal

Pad

4




6 Pin Configuration and Functions

DKQ Package56-Pin HSSOP With Exposed Thermal Pad

Top View


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5




(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/DO = digital inputand output, NC = no connection

Pin FunctionsPIN

TYPE (1) DESCRIPTIONNAME NO.AREF 4 PWR VREG and VCOM bypass capacitor returnAVDD 8 PWR Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSSAVSS 7 PWR AVDD bypass capacitor returnBST_M 44 PWR Bootstrap capacitor connection pin for high-side gate driverBST_P 48 PWR Bootstrap capacitor connection pin for high-side gate driverFAULT 26 DO Reports a fault (active low, open drain), 100 kΩ internal pull-up resistorFSYNC 14 DI Audio frame clock input

GND 1, 11, 16, 17,18, 28, 46 GND Ground

GVDD 9 PWR Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GNDI2C_ADDR0 22

DI I2C address pins. Refer to Table 7I2C_ADDR1 23MCLK 12 DI Audio master clock input

MUTE 25 DI Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100 kΩinternal pull-down resistor

NC 10, 29-43,49-54 NC Not connected or pulled to ground

OUT_M 45 NO Negative output for the channelOUT_P 47 PO Positive output for the channel

PVDD 2, 55, 56 PWR PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitorrequired

SCL 20 DI I2C clock inputSCLK 13 DI Audio bit and serial clock inputSDA 21 DI/DO I2C data input and outputSDIN1 15 DI TDM data input and audio I2S data inputSTANDBY 24 DI Enables low power standby state (active Low), 100 kΩ internal pull-down resistorVBAT 3 PWR Battery voltage inputVCOM 6 PWR Bias voltageVDD 19 PWR 3.3 V external supply voltageVREG 5 PWR Voltage regulator bypassWARN 27 DO Clip and overtemperature warning (active low, open drain), 100 kΩ internal pull-up resistor

Thermal Pad — GND Provides both electrical and thermal connection for the device. Heatsink must be connected toGND.


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6




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITPVDD, VBAT DC supply voltage relative to GND -0.3 30 VVMAX Transient supply voltage: PVDD, VBAT t ≤ 400 ms exposure -1 40 VVRAMP Supply-voltage ramp rate: PVDD, VBAT 75 V/msVDD DC supply voltage relative to GND -0.3 3.5 VIMAX Maximum current per pin (PVDD, VBAT, OUT_P, OUT_M, GND) 8 AIMAX_PULSED Pulsed supply current per PVDD pin (one shot) t < 100 ms 12 A

VLOGICInput voltage for logic pins (SCL, SDA, SDIN1, FSYNC, MCLK, BCLK, SCLK,MUTE, STANDBY, I2C_ADDRx) -0.3 VDD + 0.5 V

VGND Maximum voltage between GND pins -0.3 0.3 VTJ Maximum operating junction temperature -55 150 °CTstg Storage temperature -55 150 °C

(1) (1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002 (1)

HBM ESD Classification Level 2 ±3000V

Charged-device model (CDM), per AEC Q100–011CDM ESD Classification Level C4B

All pins ±500

Corner pins (1, 28, 29 and 56) ±750 V


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7




7.3 Recommended Operating ConditionsMIN TYP MAX UNIT

PVDD Output FET Supply Voltage Range Relative to GND 4.5 26.4

VVBAT Battery Supply Voltage Input Relative to GND 4.5 14.4 18

VDD DC Logic supply Relative to GND 3.0 3.3 3.5

TA Ambient temperature –40 125°C

TJ Junction temperature An adequate thermal design isrequired –40 150

RL Minimum speaker load impedance BTL Mode 2 4 Ω

RPU_I2C I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ

CBypass External capacitance on bypass pins Pin 2, 3, 5, 6, 8, 19 1 µF

CGVDD External capacitance on GVDD pin Pin 9 2.2 µF

COUT External capacitance to GND on OUT pins Limit set by DC-diagnostic timing 1 3.3 µF

LO Output filter inductance at 2.1MHz Minimum inductance at ISD currentlevels 1 µH

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

(2) JEDEC Standard 4 Layer PCB.

7.4 Thermal Information

THERMAL METRIC (1)TAS6421-Q1 (2)

DKQ (HSSOP)56 PINS UNIT

RθJA Junction-to-ambient thermal resistance 42.8 °C/WRθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/WRθJB Junction-to-board thermal resistance 21.2 °C/WΨJT Junction-to-top characterization parameter 0.5 °C/WΨJB Junction-to-board characterization parameter 20.2 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance - °C/W


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http://www.ti.com/lit/pdf/SPRA953

8




7.5 Electrical CharacteristicsTest conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings

PARAMETER TEST CONDITIONS MIN TYP MAX UNITOPERATING CURRENTIPVDD_IDLE PVDD idle current Channel playing, no audio input 17 23 mAIVBAT_IDLE VBAT idle current Channel playing, no audio input 28 32 mAIPVDD_STBY PVDD standby current STANDBY Active, VDD = 0 V 0.5 1 µAIVBAT_STBY VBAT standby current STANDBY Active, VDD = 0 V 4 6 µAIVDD VDD supply current Channel playing, –60-dB signal 15 18 mAOUTPUT POWER

PO_BTL Output power per channel, BTL

4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22

W

4 Ω, PVDD = 14.4 V, THD+N = 10%, TC =75°C 25 27

2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 402 Ω, PVDD = 14.4 V, THD+N = 10%, TC =75°C 42 45

4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C 50 554 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C 70 75

EFFP Power efficiency1 channel operating at 25-W output power, 4 Ωload, PVDD = 14.4 V, TC = 25°C, includinginductor losses

86%

AUDIO PERFORMANCE

Vn Output noise voltage

Zero input, A-weighting, gain level 1, PVDD =14.4 V 42

µV

Zero input, A-weighting, gain level 2, PVDD =14.4 V 55

Zero input, A-weighting, gain level 3, PVDD =18 V 67

Zero input, A-weighting, gain level 4, PVDD =25 V 85

GAIN Peak Output Voltage/dBFS

gain level 1, Register 0x01, bit 1-0 = 00 7.5

V/FSgain level 2, Register 0x01, bit 1-0 = 01 15gain level 3, Register 0x01, bit 1-0 = 10 21gain level 4, Register 0x01, bit 1-0 = 11 29

PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, f = 1 kHz 75 dBTHD+N Total harmonic distortion + noise 0.02%LINE OUTPUT PERFORMANCE

Vn_LINEOUT LINE output noise voltage Zero input, A-weighting, channel set to LINEMODE 42 µV

VO_LINEOUT LINE output voltage 0dB input, channel set to LINE MODE 5.5 VRMS

THD+N Line output total harmonic distortion +noise VO = 2 VRMS, channel set to LINE MODE 0.01%

DIGITAL INPUT PINSVIH Input logic level high 70 %VDDVIL Input logic level low 30 %VDDIIH Input logic current, high VI = VDD 15 µAIIL Input logic current, low VI = 0 -15 µAPWM OUTPUT STAGE

RDS(on) FET drain-to-source resistance Not including bond wire and packageresistance 90 mΩ

OVERVOLTAGE (OV) PROTECTIONVPVDD_OV PVDD overvoltage shutdown 27.0 27.8 28.8 V


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9




Electrical Characteristics (continued)Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VPVDD_OV_HYSPVDD overvoltage shutdownhysteresis 0.8 V

VVBAT_OV VBAT overvoltage shutdown 20 21.5 23 VVVBAT_OV_HYS VBAT overvoltage shutdown hysteresis 0.6 VUNDERVOLTAGE (UV) PROTECTIONVBATUV VBAT undervoltage shutdown 4 4.5 V

VBATUV_HYSVBAT undervoltage shutdownhysteresis 0.2 V

PVDDUV PVDD undervoltage shutdown 4 4.5 V

PVDDUV_HYSPVDD undervoltage shutdownhysteresis 0.2 V

BYPASS VOLTAGESVGVDD Gate drive bypass pin voltage 7 VVAVDD Analog bypass pin voltage 6 VVVCOM Common bypass pin voltage 2.5 VVVREG Regulator bypass pin voltage 5.5 VPOWER-ON RESET (POR)VPOR VDD voltage for POR 2.1 2.7 VVPOR_HYS VDD POR recovery hysteresis voltage 0.5 VOVERTEMPERATURE (OT) PROTECTIONOTW(i) Channel overtemperature warning 150 °COTSD(i) Channel overtemperature shutdown 175 °C

OTW Global junction overtemperaturewarning 130 °C

OTSD Global junction overtemperatureshutdown 160 °C

OTHYS Overtemperature hysteresis 15 °CLOAD OVERCURRENT PROTECTION

ILIM Overcurrent cycle-by-cycle limitOC Level 1 4.0 4.8 AOC Level 2 6.0 6.5 A

ISD Overcurrent shutdown

OC Level 1, Any short to supply, ground, orother channels 7 A

OC Level 2, Any short to supply, ground, orother channels 9 A

MUTE MODEGMUTE Output attenuation 100 dBCLICK AND POP

VCP Output click and pop voltage ITU-R 2k filter, High-Z/MUTE to Play, Play toMute/High-Z 7 mV

DC OFFSETVOFFSET Output offset voltage 2 5 mVDC DETECTDCFAULT Output DC fault protection 2 2.5 VDIGITAL OUTPUT PINSVOH Output voltage for logic level high I = ±2 mA 90 %VDDVOL Output voltage for logic level low I = ±2 mA 10 %VDD

tDELAY_CLIPDETSignal delay when output clippingdetected 20 µs


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10





PARAMETER TEST CONDITIONS MIN TYP MAX UNITLOAD DIAGNOSTICS

S2P Resistance to detect a short from OUTpin(s) to PVDD 500 Ω

S2G Resistance to detect a short from OUTpin(s) to ground 200 Ω

SL Shorted load detection tolerance ±0.5 Ω

OL Open load 40 70 Ω

TDC_DIAG DC diagnostic time 100 msLO Line output diagnostic detection 6 kΩTLINE_DIAG Line output diagnostic time Not including the preceeding DC_DIAG time 40 msACIMP AC impedance accuracy Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω 25%ACIMP AC impedance accuracy Offset ±0.5 Ω

TAC_DIAG AC diagnostic time 170 msI2C_ADDR PINS

tI2C_ADDRTime delay needed for I2C addressset-up 300 µs


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11





PARAMETER TEST CONDITIONS MIN TYP MAX UNITI2C CONTROL PORT

tBUSBus free time between a STOP andSTART condition 1.3 µs

th1 Hold time, SCL to SDA 0 nsth2 Hold time, start condition to SCL 0.6 µs

tSTARTI2C startup time after VDD power onreset 12 ms

tRISE Rise time, SCL and SDA 300 nstFALL Fall time, SCL and SDA 300 nstSU1 Setup, SDA to SCL 100 nstSU2 Setup, SCL to start condition 0.6 µstSU3 Setup, SCL to stop condition 0.6 µstW(H) Required pulse duration SCL High 0.6 µstW(L) Required pulse duration SCL Low 1.3 µsSERIAL AUDIO PORTDMCLK, DSCLK Allowable input clock duty cycle 45% 50% 55%fMCLK Supported MCLK frequencies 128, 256, or 512 128 512 xFSfMCLK_Max Maximum frequency 25 MHztSCY SCLK pulse cycle time 40 nstSCL SCLK pulse-with LOW 16 nstSCH SCLK pulse-with HIGH 16 nstRISE/FALL Rise and fall time <5 nstSF SCLK rising edge to FSYNC edge 8 nstFS FSYNC rising edge to SCLK edge 8 nstDS DATA set-up time 8 nstDH DATA hold time 8 ns

ciInput capacitance, pins MCLK, SCLK,FSYNC, SDIN1 10 pf

TLALatency from input to output measuredin FSYNC sample count

FSYNC = 44.1 kHz or 48 kHz 30FSYNC = 96 kHz 12


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Frequency (Hz)

TH

D+

N (

%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

2 : Load4 : Load

Frequency (Hz)

TH

D+

N (

%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

2 : Load4 : Load

Frequency (Hz)

TH

D+

N (

%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

2 : Load4 : Load

Frequency (Hz)

TH

D+

N (

%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

2 : Load4 : Load

Frequency

PS

RR

(d

B)

-100

-80

-60

-40

-20

0

100 1k 10k 20k20

PVDD = 14.4 VPVDD = 24 V

Frequency

PS

RR

(d

B)

-120

-100

-80

-60

-40

-20

0

100 1k 10k 20k20


12




7.6 Typical CharacteristicsTA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2Csettings, see Figure 66 (unless otherwise noted)

PO = 1 W

Figure 1. PVDD PSRR vs Frequency

PO = 1 W

Figure 2. VBAT PSRR vs Frequency

PO = 1 W fSW = 384 kHz

Figure 3. THD+N vs Frequency

PO = 1 W fSW = 2.1 MHz


PO = 1 W 24 V fSW = 384 kHz


PO = 1 W 24 V fSW = 2.1 MHz



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Supply Voltage (V)

Ou

tpu

t P

ow

er

(W)

5 7 9 11 13 15 17 19 21 23 25 260

10

20

30

40

50

60

70

80

90

1002 : Load4 : Load

Supply Voltage (V)

Ou

tpu

t P

ow

er

(W)

5 7 9 11 13 15 17 19 21 23 25 260

10

20

30

40

50

60

70

80

90

1002 : Load4 : Load

Output Power (W)

Tota

l H

arm

onic

Dis

tort

ion +

No

ise (

%)

0.001

0.01

0.1

1

10

10m 100m 1 10 100

4 : Load

Output Power (W)

Tota

l H

arm

onic

Dis

tort

ion +

No

ise (

%)

0.001

0.01

0.1

1

10

10m 100m 1 10 100

4 : Load

Output Power (W)

Tota

l H

arm

onic

Dis

tort

ion +

No

ise (

%)

0.001

0.01

0.1

1

10

10m 100m 1 10 100

2 : Load4 : Load

Output Power (W)

Tota

l H

arm

onic

Dis

tort

ion +

No

ise (

%)

0.001

0.01

0.1

1

10

10m 100m 1 10 100

2 : Load4 : Load

13




Typical Characteristics (continued)TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2Csettings, see Figure 66 (unless otherwise noted)

fSW = 384 kHz

Figure 7. THD+N vs Power

fSW = 2.1 MHz


24 V fSW = 384 kHz


24 V fSW = 2.1 MHz


10% THD fSW = 384 kHz

Figure 11. Output Power vs Supply Voltage

10% THD fSW = 2.1 MHz



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Output Power (W)

Eff

icie

ncy (

%)

0

10

20

30

40

50

60

70

80

90

100

0 10 4020 5030

PVDD = 14.4 V

Output Power (W)

Eff

icie

ncy (

%)

0

10

20

30

40

50

60

70

80

90

100

0 10 4020 5030

PVDD = 14.4 V

Output Power (W)

Eff

icie

ncy (

%)

0

10

20

30

40

50

60

70

80

90

100

0 10 4020 5030 60 70 80


Output Power (W)

Eff

icie

ncy (

%)

0

10

20

30

40

50

60

70

80

90

100

0 10 4020 5030 60 70 80


Supply Voltage (V)

Idle

Chann

el N

ois

e (P

Vrm

s)

0

20

40

60

80

100

120

140

160

205 15 2510

D014

Gain Level 1Gain Level 2Gain Level 3Gain Level 4

Supply Voltage (V)

Idle

Channel N

ois

e (P

Vrm

s)

0

20

40

60

80

100

120

140

160

5 15 25 2610 20

Gain Level 1Gain Level 2Gain Level 3Gain Level 4

14





A-weighted Noise fSW = 384 kHz

Figure 13. Noise vs Supply voltage

A-weighted Noise fSW = 2.1 MHz

Figure 14. Noise vs Supply voltage

4 Ω fSW = 384 kHz

Figure 15. PVDD Efficiency vs Output Power

4 Ω fSW = 2.1 MHz

Figure 16. PVDD Efficiency vs Total Output Power

2 Ω fSW = 384 kHz


2 Ω fSW = 2.1 MHz



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Total Output Power (W)

Pow

er

Dis

sip

ation (

W)

0 10 20 30 40 50 60 70 800

2

4

6

8

10

12

0

PVDD = 14.4 V 2 : LoadPVDD = 14.4 V 4 : LoadPVDD = 24 V 4 : Load

Supply Voltage (V)

PV

DD

Sh

utd

ow

n C

urr

en

t (P

A)

0

1

2

3

4

5

6

5 15 25 267 9 11 13 17 19 21 23Total Output Power (W)

Pow

er

Dis

sip

ation (

W)

0 10 20 30 40 50 60 70 800

2

4

6

8

10

0

PVDD = 14.4 V 2 : LoadPVDD = 14.4 V 4 : LoadPVDD = 24 V 4 : Load

Supply Voltage (V)

Vb

at Id

le C

urr

ent (m

A)

0

5

10

15

20

25

30

185 1510

D020

FPWM = 384 kHzFPWM = 2.1 MHz

Supply Voltage (V)

PV

DD

Id

le C

urr

en

t (m

A)

0

2

4

6

8

10

12

14

16

18

20

7 95 1511 13 17 19 21 2623 25

FPWM = 384 kHzFPWM = 2.1 MHz

15





Figure 19. PVDD Idle Current vs Voltage Figure 20. VBAT Idle Current vs Voltage

Figure 21. PVDD + VBAT Standby Current vs Voltage fSW = 384 kHz

Figure 22. Power Dissipation vs Output Power

fSW = 2.1 MHz

Figure 23. Power Dissipation vs Output Power


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8 Parameter Measurement InformationThe parameters for the TAS6421-Q1 device were measured using the circuit in Figure 66.

For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6421-Q1 EVM is used.


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VDD VCOM VBAT GVDD PVDD

OUT_P

OUT_M

VREG

I2C_ADDR1

I2C_ADDR0

SDA

SCL

I2C Control

SDIN1

SCLK

FSYNC

MCLK

Serial

AudioPort

PLL and Clock

Management

STANDBY

WARN

FAULT

Digital Core

Reference

Regulators

Gate Drive

Regulator

Powerstage

Volume Control -100

to +24 dB,

0.5 dB steps

Gate

Driver

Digital to PWM

Clip

Detection

Closed Loop Class D Amplifier

Overcurrent Limit

Protection

Overcurrent

Overtemperature

Overvoltage and Undervoltage

DC Detection

Short to GND

DC Load Diagnostics

Short to Power

Open Load

Shorted Load

AC Load Diagnostics

MUTE

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9 Detailed description

9.1 OverviewThe TAS6421-Q1 device is a single-channel digital-input Class-D audio amplifier specifically tailored for use inthe automotive industry. The device is designed for vehicle battery operation or boosted voltage systems. Thisefficient Class-D technology allows for reduced power consumption, reduced PCB area and reduced heat. Thedevice realizes an audio sound-system design with smaller size and lower weight than traditional Class-ABsolutions.

The core design blocks are as follows:• Serial audio port• Clock management• High-pass filter and volume control• Pulse width modulator (PWM) with output stage feedback• Gate drive• Power FETs• Diagnostics• Protection• Power supply• I2C serial communication bus

9.2 Functional Block Diagram


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MCLK

SCLK

FSYNC

SDIN1

SDIN2

TAS6424

MCLK

SCLK

FSYNC

SDIN1

TAS6421

MCLK

SCLK

FSYNC

DATA1

DATA2

SOC

DATA3

I2S

MCLK

SCLK

FSYNC

SDIN1

SDIN2

TAS6424

MCLK

SCLK

FSYNC

SDIN1

TAS6421

MCLK

FSYNC

DATA

SOC

TDM8

SCLK

18




9.3 Feature Description

9.3.1 Serial Audio PortThe serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.

Settings for the serial audio port are programmed in the SAP Control (Serial Audio-Port Control) Register(address = 0x03) [default = 0x04] and Miscellaneous Control 3 Register (address = 0x21) [default = 0x00].

Figure 24 shows the digital audio data connections for I2S and TDM8 mode for a five channel system usingTAS6424 four-channel Class-D amplifier and a TAS6421-Q1 single-channel Class-D amplifier.

Figure 24. Digital-Audio Data Connection

9.3.1.1 I2S ModeI2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when thedata is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bitclock, SCLK, runs at 32 × fS or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from thetime the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2s-complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.

The SAP Control Register Bits 3-5 allows to select if I2S Channel 1 or Channel 2 is amplified.

9.3.1.2 Left-Justified TimingLeft-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channeland when the data is for the right channel. The FSYNC pin is high for the left channel and low for the rightchannel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on thedata lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bitclock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right(L/R) frame with zeros.

9.3.1.3 Right-Justified TimingRight-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the leftchannel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for theright channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears onthe data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is alwaysclocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on therising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.


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Feature Description (continued)9.3.1.4 TDM ModeTDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDMclocks are present. The device can be configured through I2C to select which TDM channel slot is amplified. TheTDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.

In TDM mode, SCLK must be 128 x fs or 256 x fs, depending on the TDM slot size. In TDM mode SCLK andMCLK can be connected together. If SCLK and MCLK are connected together or the frequency of SCLK andMCLK is equal, FSYNC should be minimum 2 MCLK pulses long.

In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. Table 1 lists register settings for the TDMchannel selection.

Table 1. Channel SelectionREGISTER SETTING AMPLIFIED CHANNEL

0x03BIT 5

0x03BIT 4

0x03BIT 3

0 0 0 Slot 1 in TDM8/4 or Left Channel in I2S mode0 0 1 Slot 2 in TDM8/4 or Right Channel in I2S mode0 1 0 Slot 3 in TDM8/40 1 1 Slot 4 in TDM8/41 0 0 Slot 5 in TDM81 0 1 Slot 6 in TDM81 1 0 Slot 7 in TDM81 1 1 Slot 8 in TDM8

9.3.1.5 Supported Clock RatesThe device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.

The device supports SCLK rates of 32 × fS or 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDMmode.

The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.

The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is256 × fS.

Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty cycle is not required.

9.3.1.6 Audio-Clock Error HandlingWhen any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts allchannels into the Hi-Z state. When all audio clocks are within the expected range, the device automaticallyreturns to the state it was in. See the Electrical Characteristics table for timing requirements.


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151410151410

232210232210

313010313010

MSB LSB MSB LSB

MSB LSBMSB LSB

MSB MSBLSB LSB

SDIN

Audio data word = 32 bit, SCLK = 64 fS


SDIN

SDIN


SCLK

FSYNCL-channel

R-channel

1/fS

0.5 × DVDD

0.5 × DVDD

0.5 × DVDD

FSYNC

(Input)

SCLK

(Input)

DATA

(Input)

tSCH tSCL

tSFtSCY

tDS tDH

tFS

20




Figure 25. Serial Audio Timing

Figure 26. Left-Justified Audio Data Format


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Audio Data Format: TDM8 mode

23 22 01

1/Fs (256 sbclks)

SDIN (I2S mode) 23 22 01

32 SCLK

8 blocks of 32 SCLK

23 22 01

32 SCLK

23 22

SCLK

FSYNC

151410151410

232210232210

313010313010

MSB LSB MSB LSB

MSB LSBMSB LSB

MSB MSBLSB LSB

SDIN



SDIN

SDIN


SCLK

FSYNCL-channel

R-channel

1/fS

21




Figure 27. I2S Audio Data Format

Figure 28. TDM8 Audio Data Format

9.3.2 DC BlockingDirect-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter toremove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz,15 Hz, 30 Hz andseveral more options up to 463 Hz with bits 0 through 2 in register 0x26. The default value of –3 dB isapproximately 4 Hz for 44.1 kHz or 48 kHz and approximately 8 Hz for 96 kHz sampling rates.


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9.3.3 Volume Control and GainThe output channel has a digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps. Thevolume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1, 2,4, or 8 FSYNC cycles.

The peak output-voltage swing is also configurable in the gain control register through I2C. The four full-scalevoltage settings are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expectedPVDD operation to optimize output noise and dynamic range performance.

9.3.4 High-Frequency Pulse-Width Modulator (PWM)The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is anadvanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching rateis synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48× theinput-sample rate. The option to switch at high frequency allows the use of smaller and lower cost externalfiltering components. Table 2 lists the switch frequency options for bits 4 through 6 in the Miscellaneous Control2 register (address 0x02).

Table 2. Output Switch Frequency OptionINPUT SAMPLE RATE BIT 6:4 SETTINGS

000 001 010 to 100 101 110 11144.1 kHz 352.8 kHz 441 kHz RESERVED 1.68 MHz 1.94 MHz 2.12 MHz48 kHz 384 kHz 480 kHz RESERVED 1.82 MHz 2.11 MHz Not supported96 kHz 384 kHz 480 kHz RESERVED 1.82 MHz 2.11 MHz Not supported

9.3.5 Gate DriveThe gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power-FET stage. The device uses proprietary techniques to optimize EMI and audio performance.

The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected atpin 9.

The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for theproper operation of the high side NMOS transistors. A 1-µF ceramic capacitor of quality X7R or better, rated forat least 16 V, must be connected from each output to the corresponding bootstrap input. The bootstrapcapacitors connected between the BST pins and corresponding output function as a floating power supply for thehigh-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrapcapacitors hold the gate-to-source voltage high keeping the high-side MOSFETs turned on.

9.3.6 Power FETsThe BTL output channel comprises four N-channel 90-mΩ FETs for high efficiency and maximum power transferto the load. These FETs are designed to handle the fast switching frequency and large voltage transients duringload dump.

9.3.7 Load DiagnosticsThe device incorporates both DC-load and AC-load diagnostics, which are used to determine the status of theload. The DC diagnostics are turned on by default, but if a fast startup without diagnostics is required, the DCdiagnostics can be bypassed through I2C. The DC diagnostics run when the output channel is directed to leavethe Hi-Z state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually. DCDiagnostics can be started from any operating condition, but if the channel is in PLAY state, then the time tocomplete the diagnostic is longer because the device must ramp down the audio signal of that channel beforetransitioning to the Hi-Z state. The DC diagnostics are available as soon as the device supplies are within therecommended operating range. The DC diagnostics do not rely on the audio input clocks to be available tofunction. DC Diagnostic results are reported through I2C registers.


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Open Load Open Load Detected

Open Load (OL)

Detection Threshold

Normal or Open Load

May Be Detected

Shorted Load Shorted Load Detected

Shorted Load (SL)

Detection Threshold

Normal or Shorted Load

May Be Detected

Normal Load Play Mode

OL Maximum

OL Minimum

SL Maximum

SL Minimum

23




9.3.7.1 DC Load DiagnosticsThe DC load diagnostics are used to verify the load is connected. The DC diagnostics consists of four tests:short-to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G teststrigger if the impedance to GND or a power rail is below that specified in the Specifications section. Thediagnostic detects a short to vehicle battery, even when the supply is boosted. The SL test has an I2C-configurable threshold depending on the expected load to be connected. The OL test reports if the selectchannel has a load impedance greater than the limits in the Specifications section.

Figure 29. DC Load Diagnostic Reporting Thresholds

9.3.7.2 Line Output DiagnosticsThe device also includes an optional test to detect a line-output load. A line-output load is a high-impedance loadthat is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OLcondition is detected, if the line output detection bit is also set, the channel checks if a line-output load is presentas well. This test is not pop free, so if an external amplifier is connected it should be muted.

9.3.7.3 AC Load DiagnosticsThe AC load diagnostic is used to determine the proper connection of a capacitively-coupled speaker or tweeterwhen used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnosticsrequires an external input signal and reports the approximate load impedance and phase. The selected signalfrequency should create current flow through the desired speaker for proper detection. The AC load-diagnostictest procedure is as follows.

9.3.7.3.1 Impedance Magnitude Measurement

For load-impedance detection, use the following test procedure:1. Set the output channel into the Hi-Z state.2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.3. Apply a full-scale input signal from the DSP for the tested channel with the desired frequency (recommended

10 kHz to 20 kHz).

NOTEThe device ramps the signal up and down automatically to prevent pops and clicks.

4. Set the device into the AC diagnostic mode (set bit 3 in register 0x15 to 1).5. Read back the AC impedance (register 0x17).

When the test is complete, the channel reporting register indicates the status change from the AC diagnosticmode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.


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2D=OA_%*T = 360(2D=OA_%*T:.$-;F 2D=OA_%*T(.&/)

56+_%*T(.&/))

_ 2.371 ( )

( )( )

Impedance CHx mVChannelx Impedance Ohms

Gain I mA

u

24




The hexadecimal register value must be converted to decimal and used to calculate the impedance magnitudeusing Equation 1:

(1)

9.3.7.3.2 Impedance Phase Reference Measurement

The first stage to determine the AC phase is to utilize the built-in loopback mode to determine the referencevalue for the phase measurement. This reference nullifies any phase offset in the device and measure only thephase of the load.

For loopback delay detection, use the following test procedure:1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics (set bit 3 in register 0x15 to 1).3. Read back the 16bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register

0x1C holds the LSB.4. Set bit 3 in register 0x15 to 0.


9.3.7.3.3 Impedance Phase Measurement

After performing the phase reference measurements, measure the phase of the speaker load. This is performedin the same manner as the reference measurements, except the loopback is disabled in register 0x16, bit 7.

For loopback delay detection, use the following test procedure:1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode.2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics by setting bit 3 in register 0x15 to 1.3. Read back the 16-bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register

0x1C holds the LSB.4. Read back the hexadecimal stimulus value, STI. Register 0x1D holds the MSB and register 0x1E holds the

LSB.5. Set bit 3 in register 0x15 to 0.


The AC phase in degrees is calculated using Equation 2:

(2)

Where:• Phase_CHx(LBK) is the reference phase measurement. LBK stands for loopback mode• Phase_CHx(LDM) is the phase measure of the load. LDM stands for load mode• STI_CHx(LDM) is the stimulus value

Table 3. AC Impedance Code to Magnitude

SETTING GAIN AT 19 kHz I(A) MEASUREMENT RANGE (Ω) MAPPING FROM CODE TOMAGNITUDE (Ω/Code)

Gain = 4, I = 10 mA(recommended) 4.28 0.01 12 0.05832

Gain = 4, I = 19 mA 4.28 0.019 6 0.0307

Gain = 1, I = 10 mA(recommended) 1 0.01 48 0.2496

Gain = 1, I = 19 mA 1 0.019 24 0.1314


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9.3.8 Protection and Monitoring

9.3.8.1 Overcurrent Limit (ILIMIT)The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT) isexceeded. Power is limited, but operation continues without disruption and prevents undesired shutdown fortransient music events. ILIMIT is not reported as fault condition to registers or the FAULT pin but as warningcondition to the WARN pin and ILIMIT Status Register (address = 0x25) [default = 0x00]. The two programmablelevels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).

9.3.8.2 Overcurrent Shutdown (ISD)If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs, whichshuts down the channel. The time to shutdown the channel varies depending on the severity of the shortcondition. The channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT pin isasserted. The device remains in this state until the CLEAR FAULT bit is set in Miscellaneous Control 3 Register,0x21 bit 7. After clearing this bit and if the diagnostics are enabled, the device automatically starts diagnostics onthe channel and, if no load failure is found, the device restarts. If a load fault is found the device continues torerun the diagnostics once per second. Because this hiccup mode uses the diagnostics, no high current iscreated. If the diagnostics are disabled, the device sets the state for the channel to Hi-Z and requires the MCU totake the appropriate action, setting the CLEAR FAULT bit after the fault was removed, in order to return to Playstate. The two programmable levels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).

9.3.8.3 DC DetectThis circuit checks the DC offset continuously during normal operation at the output of the amplifier. If the DCoffset exceeds the threshold, the channel is placed in the Hi-Z state, the fault is reported to the I2C register, andthe FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.

9.3.8.4 Clip DetectThe Clip Detect is reported on the WARN pin if 100% duty-cycle PWM is reached for a minimum number ofPWM cycles set by the Clip Window Register (address = 0x23). The default is 20 PWM cycles. The Clip Detect islatched and can be cleared by I2C. Masking the clip reporting to the pin is possible through I2C. If desired, theClip Detect can be configured to be non-latching through I2C. In non-latching mode, Clip Detect is reported whenthe PWM duty cycle reaches 100%, and deasserted once the PWM duty cycle falls below 100%.

9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)Four overtemperature warning levels are available in the device (see the Register Maps section for thresholds).When the junction temperature exceeds the warning level, the WARN pin is asserted, unless the mask bit hasbeen set to disable reporting. The device functions until the OTSD value is reached, at which point the channelsare placed in the Hi-Z state and the FAULT pin is asserted. By default, the device remains shut down after thetemperature drops to normal levels. This configuration can be changed in bit 3 of the Miscellaneous Control 3Register (address = 0x21) [default = 0x00] to auto-recovery: When the junction temperature returns to normallevels, the device automatically recovers and places the channel into the state indicated by the state controlregister. Note that even in auto-recovery configuration the FAULT pin remains asserted until the CLEAR FAULTbit (bit 7) is set in register 0x21.

9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]In addition to the global OTW, the output channel also has an individual overtemperature warning and shutdown.If the channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted, unlessthe mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold thenthe channel goes to the Hi-Z state and either remains there or auto-recovers to the state indicated by the statecontrol register when the temperature drops below the OTW(i) threshold, depending on the setting of bit 3 of theMiscellaneous Control 3 Register (address = 0x21) [default = 0x00].


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9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UVcondition, the FAULT pin is asserted, and the I2C register is updated. A power-on reset (POR) on the VDD pincauses the I2C to goes to the high-impedance (Hi-Z) state, and all registers are reset to default values. At power-on or after a POR event, the POR warning bit and WARN pin are asserted.

9.3.8.8 Overvoltage (OV) and Load DumpThe overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OVthreshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dumpvoltage spikes.

9.3.9 Power SupplyThe device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:

VDD This pin is a 3.3V supply pin that provides power to the low voltage circuitry.

VBAT This pin is a higher voltage supply that can be connected to the vehicle battery or the regulatedvoltage rail in a boosted system within the recommended limits. For best performance, this railshould be 10 V or higher. See the Recommended Operating Conditions table for the maximumsupply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs.

PVDD This pin is a high-voltage supply that can either be connected to the vehicle battery or to anothervoltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can bewithin the recommended operating limits, even if that is below the VBAT supply, to allow fordynamic voltage systems.

Several on-chip regulators are included for generating the voltages necessary for the internal circuitry. Theexternal pins are provided only for bypass capacitors to filter the supply and should not be used to power othercircuits.

The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings forthe device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for asecond ground path through the body diode in the output FETs.

9.3.9.1 Vehicle-Battery Power-Supply SequenceThe device can accept any sequence of the VBAT, PVDD and VDD supply.

9.3.9.1.1 Power-Up Sequence

In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at thesame time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommendedoperating range.

9.3.9.1.2 Power-Down Sequence

To power-down the device, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT orVDD. After 15ms, the power supplies can be removed.

9.3.9.2 Boosted Power-Supply SequenceIn this case, the VBAT and PVDD inputs are not connected to the same supply.

When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.

When powering down, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT or VDD.After 15 ms, the power supplies can be removed.

9.3.10 Hardware Control PinsThe device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.


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27




9.3.10.1 FAULTThe FAULT pin reports faults and is active low under any of the following conditions:• Channel faults (overcurrent or DC detection)• Overtemperature shutdown• Overvoltage or undervoltage conditions on the VBAT or PVDD pins• Clock errors

For all listed faults, the FAULT pin remains asserted after the fault condition is rectified. Deassert the FAULT pinby writing the CLEAR FAULT bit (bit 7) in register 0x21. The only exception is the fault report caused byOvertemperature shutdown, for which the FAULT pin deasserts automatically when the junction temperaturereturns to normal levels and the device automatically recovers.

The register reports for all fault reports remain asserted until they are cleared by writing the CLEAR FAULT bit(bit 7) in register 0x21.

Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask thesetting of the pin and do not affect the register reporting or protection of the device. By default all faults arereported to the pin. See the Register Maps section for a description of the mask settings.

This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.

9.3.10.2 WARNThis active-low output pin reports audio clipping, overtemperature warnings, overcurrent limit warnings and PORevents.

Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks (default value)which results in a 10-µs delay to report the onset of clipping. Changing the number of required consecutive PWMclocks in the Clip Window Register (address = 0x23) impacts the report delay time. The Clip Detect warning bit issticky in latching mode and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21.

An overtemperature warning (OTW) is reported if the general temperature or the channel temperature warningsare set. The warning temperature can be set through bits 5 and 6 in register 0x01.

Register bits are available to mask either clipping, OTW or ILIMIT reporting to the pin. These bits only mask thesetting of the pin and do not affect the register reporting. By default clipping, ILIMIT and OTW are reported.

The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.

This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.

9.3.10.3 MUTEThis active-low input pin is used for hardware control of the mute and unmute function.

This pin has a 100 kΩ internal pull-down resistor.

9.3.10.4 STANDBYWhen this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pincan be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is notalready in the Hi-Z state.

This pin has a 100 kΩ internal pull-down resistor.


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9.4 Device Functional Modes

9.4.1 Operating Modes and FaultsThe operating modes and faults are listed in the following tables.

Global Faults affect the entire device while the effect and management of Channel Faults is limited to the OutputStage. Although the system effects of a Global Fault and a Channel Fault can be identical in a 1-channel devicesuch as TAS6421-Q1, this split and naming convention was selected to remain compatible with the multi-channelTAS642x-Q1 family devices.

Table 4. Operating ModesSTATE NAME OUTPUT FETS OSCILLATOR I2C

STANDBY Hi-Z Stopped ActiveHi-Z Hi-Z Active Active

MUTE Switching at 50% Active ActivePLAY Switching with audio Active Active

Table 5. Global Faults and ActionsFAULT/EVENT

FAULT/EVENTCATEGORY

MONITORINGMODES

REPORTINGMETHOD

ACTIONRESULT

POR

Voltage fault

All I2C + WARN pin StandbyVBAT UV

Hi-Z, mute, normal I2C + FAULT pin Hi-ZPVDD UVVBAT or PVDD OV

OTW Thermal warning Hi-Z, mute, normal I2C + WARN pin NoneOTSD Thermal shutdown Hi-Z, mute, normal I2C + FAULT pin Hi-Z

Table 6. Channel Faults and ActionsFAULT/EVENT

FAULT/EVENTCATEGORY

MONITORINGMODES

REPORTINGMETHOD

ACTIONTYPE

Clipping Warning

Mute and play

I2C + WARN or FAULTpin None

Overcurrent limiting Protection I2C + WARN pin Current limitOvercurrent fault

Output channel fault I2C + FAULT pin Hi-ZDC detect


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SDA

SCL

Start Stop

7-Bit Slave AddressR/

WA A A A8-Bit Register Address (N)

8-Bit Register Data for

Address (N)

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

8-Bit Register Data for

Address (N)

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9.5 Programming

9.5.1 I2C Serial Communication BusThe device communicates with the system processor through the I2C serial communication bus as an I2C slave-only device. The processor can poll the device through I2C to determine the operating status, configure settings,or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.

The device includes two I2C address pins, so up to four devices can be used together in a system with noadditional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in Table 7.

Table 7. I2C AddressesDESCRIPTION I2C ADDR1 I2C ADDR0 I2C Write I2C Read

Device 0 0 0 0xD4 0xD5Device 1 0 1 0xD6 0xD7Device 2 1 0 0xD8 0xD9Device 3 1 1 0xDA 0xDB

9.5.2 I2C Bus ProtocolThe device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol andsupports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. TheTAS6421-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-stateinsertion. The control interface is used to program the registers of the device and to read device status.

The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in asystem. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus isacknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the masterdevice driving a start condition on the bus and ends with the master device driving a stop condition on the bus.The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stopconditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bitslave address and the read/write (R/W) bit to open communication with another device and then wait for anacknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate anacknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device isaddressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signalsvia a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA andSCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start andstop conditions is unlimited. When the last word transfers, the master generates a stop condition to release thebus.

Figure 30. Typical I2C Sequence


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AcknowledgeAcknowledgeAcknowledgeAcknowledgeAcknowledgeStart

Condition

I2C Device Address

and R/W BitSubaddress First Data Byte Other Data Byte Last Data Byte

Stop

Condition

ACKD0D0 ACK D7D0 ACK D7D7ACKA1A7R/W ACKA1A6 A5 A0 A6 A5 A4 A3 A0

Acknowledge AcknowledgeAcknowledgeStart

Condition

I2C Device Address

and R/W BitSubaddress Data Byte

Stop

Condition

ACKA1 A0 ACKA3 A2A4A5A1A3 A2A6 A5 A4 A0 R/W ACK A7 A6 D7 D6 D5 D4 D3 D2 D1 D0

SCL

SDA

tw(H) tw(L)

tsu1 th1

tr tf

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Figure 31. SCL and SDA Timing

Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted usingsingle-byte or multiple-byte data transfers.

9.5.3 Random WriteAs shown in Figure 32, a single-byte data-write transfer begins with the master device transmitting a startcondition followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the datatransfer. For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/Wbit, the device responds with an acknowledge bit. Next, the master transmits the address byte or bytescorresponding to the internal memory address being accessed. After receiving the address byte, the deviceagain responds with an acknowledge bit. Next, the master device transmits the data byte to be written to thememory address being accessed. After receiving the data byte, the device again responds with an acknowledgebit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 32. Random Write Transfer

9.5.4 Sequential WriteA sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes aretransmitted by the master to the device as shown in Figure 33. After receiving each data byte, the deviceresponds with an acknowledge bit and the I2C subaddress is automatically incremented by one.

Figure 33. Sequential Write Transfer

9.5.5 Random ReadAs shown in Figure 34, a single-byte data-read transfer begins with the master device transmitting a startcondition followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed bya read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to beread. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with anacknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device


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Not

AcknowledgeAcknowledgeAcknowledgeAcknowledgeAcknowledge

Repeat Start

ConditionAcknowledge

Start

Condition

I2C Device Address

and R/W BitSubaddress

I2C Device Address

and R/W BitFirst Data Byte Other Data Byte Last Data Byte

Stop

Condition

ACKD0D0 ACK D7D0 ACK D7R/W D7A6 ACKA0A0 ACKA5R/W ACK A7A0A6 A6

Not

AcknowledgeAcknowledgeAcknowledgeAcknowledge

Start

Condition

I2C Device Address

and R/W BitSubaddress

I2C Device Address

and R/W BitData Byte

Stop

Condition

ACKD0ACK D7A1 A0 R/WA5A0A6A7A1 A0 R/WA5A6 ACK

Repeat Start

Condition

A6ACKA5 A4 D6 D6

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transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1,indicating a read transfer. After receiving the address and the R/W bit, the device again responds with anacknowledge bit. Next, the device transmits the data byte from the memory address being read. After receivingthe data byte, the master device transmits a not-acknowledge followed by a stop condition to complete thesingle-byte data-read transfer.

Figure 34. Random Read Transfer

9.5.6 Sequential ReadA sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes aretransmitted by the device to the master device as shown in Figure 35. Except for the last data byte, the masterdevice responds with an acknowledge bit after receiving each data byte and automatically increments the I2Csubaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit followedby a stop condition to complete the transfer.

Figure 35. Sequential Read Transfer


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9.6 Register Maps

Table 8. I2C Address Register DefinitionsAddress Type Register Description Section

0x00 R/W Mode Control Go0x01 R/W Miscellaneous Control 1 Go0x02 R/W Miscellaneous Control 2 Go0x03 R/W SAP Control (Serial Audio-Port Control) Go0x04 R/W Channel State Control Go0x05 R/W Channel 1 Volume Control Go0x06 R RESERVED0x07 R RESERVED0x08 R RESERVED0x09 R/W DC Diagnostic Control 1 Go0x0A R/W DC Diagnostic Control 2 Go0x0B R RESERVED0x0C R DC Load Diagnostic Report 1 Go0x0D R RESERVED0x0E R DC Load Diagnostic Report 3 - Line Output Go0x0F R Channel State Reporting Go0x10 R Channel Faults (Overcurrent, DC Detection) Go0x11 R Global Faults 1 Go0x12 R Global Faults 2 Go0x13 R Warnings Go0x14 R/W Pin Control Go0x15 R/W AC Load Diagnostic Control 1 Go0x16 R/W AC Load Diagnostic Control 2 Go0x17 R AC Load Diagnostic Report Channel 1 Go0x18 R RESERVED0x19 R RESERVED0x1A R RESERVED0x1B R AC Load Diagnostic Phase Report High Go0x1C R AC Load Diagnostic Phase Report Low Go0x1D R AC Load Diagnostic STI Report High Go0x1E R AC Load Diagnostic STI Report Low Go0x1F R RESERVED0x20 R RESERVED0x21 R/W Miscellaneous Control 3 Go0x22 R/W Clip Control Go0x23 R/W Clip Window Go0x24 R Clip Warning Go0x25 R ILIMIT Status Go0x26 R/W Miscellaneous Control 4 Go0x27 R RESERVED0x28 R RESERVED


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9.6.1 Mode Control Register (address = 0x00) [default = 0x00]The Mode Control register is shown in Figure 36 and described in Table 9.

Figure 36. Mode Control Register

7 6 5 4 3 2 1 0RESET RESERVED CH1 LO MODE RESERVEDR/W-0 R/W-0

Table 9. Mode Control Field DescriptionsBit Field Type Reset Description7 RESET R/W 0 0: Normal operation

1: Resets the device. Self-clearing, reads back 0.6-4 RESERVED R/W 000 RESERVED3 CH1 LO MODE R/W 0 0: Channel 1 is in normal/speaker mode

1: Channel 1 is in line output mode2-0 RESERVED R/W 000 RESERVED

9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]The Miscellaneous Control 1 register is shown in Figure 37 and described in Table 10.

Figure 37. Miscellaneous Control 1 Register

7 6 5 4 3 2 1 0HPF BYPASS OTW CONTROL OC CONTROL VOLUME RATE GAIN

R/W-0 R/W-01 R/W-1 R/W-00 R/W-10

Table 10. Misc Control 1 Field DescriptionsBit Field Type Reset Description7 HPF BYPASS R/W 0 0: High pass filter enabled

1: High pass filter disabled6–5 OTW CONTROL R/W 01 00: Global overtemperature warning set to 140°C

01: Global overtemperature warning set to 130C10: Global overtemperature warning set to 120°C11: Global overtemperature warning set to 110°C

4 OC CONTROL R/W 1 0: Overcurrent is level 11: Overcurrent is level 2

3–2 VOLUME RATE R/W 00 00: Volume update rate is 1 step / FSYNC01: Volume update rate is 1 step / 2 FSYNCs10: Volume update rate is 1 step / 4 FSYNCs11: Volume update rate is 1 step / 8 FSYNCs

1–0 GAIN R/W 10 00: Gain level 1 = 7.5 V peak output voltage01: Gain Level 2 = 15 V peak output voltage10: Gain Level 3 = 21 V peak output voltage11: Gain Level 4 = 29 V peak output voltage



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7 6 5 4 3 2 1 0RESERVED PWM FREQUENCY RESERVED SDM_OSR RESERVED

R/W-110 R/W-0

Table 11. Misc Control 2 Field DescriptionsBit Field Type Reset Description7 RESERVED R/W 0 RESERVED

6–4 PWM FREQUENCY R/W 110 000: 8 × fS (352.8 kHz / 384 kHz)001: 10 × fS (441 kHz / 480 kHz)010: RESERVED011: RESERVED100: RESERVED101: 38 × fS (1.68 MHz / 1.82 MHz)110: 44 × fS (1.94 MHz / 2.11 MHz)111: 48 × fS (2.12 MHz / not supported)

3 RESERVED R/W 0 RESERVED2 SDM_OSR R/W 0 0: 64x Oversampling rate

1: 128x Oversampling rate1–0 RESERVED R/W 10 RESERVED

9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]The SAP Control (serial audio-port control) register is shown in Figure 39 and described in Table 12.

Figure 39. SAP Control Register

7 6 5 4 3 2 1 0INPUT SAMPLING RATE TDM SLOT SELECT INPUT FORMAT

R/W-00 R/W-000 R/W-100

Table 12. SAP Control Field DescriptionsBit Field Type Reset Description7–6 INPUT SAMPLING RATE R/W 00 00: 44.1 kHz

01: 48 kHz10: 96 kHz11: RESERVED

5–3 TDM SLOT SELECT R/W 000 000: Select slot 1 in TDM8/4 or channel 1 in I2S mode001: Select slot 2 in TDM8/4 or channel 2 in I2S mode010: Select slot 3 in TDM8/4011: Select slot 4 in TDM8/4100: Select slot 5 in TDM8101: Select slot 6 in TDM8110: Select slot 7 in TDM8111: Select slot 8 in TDM8

2–0 INPUT FORMAT R/W 100 000: 24-bit right justified001: 20-bit right justified010: 18-bit right justified011: 16-bit right justified100: I2S (16-bit or 24-bit)101: Left justified (16-bit or 24-bit)110: DSP mode (16-bit or 24-bit)111: RESERVED


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9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]The Channel State Control register is shown in Figure 40 and described in Table 13.

Figure 40. Channel State Control Register

7 6 5 4 3 2 1 0CH1 STATE CONTROL RESERVED

R/W-01

Table 13. Channel State Control Field DescriptionsBit Field Type Reset Description7–6 CH1 STATE CONTROL R/W 01 00: PLAY

01: Hi-Z10: MUTE11: DC load diagnostics

5–0 RESERVED R/W 010101 RESERVED


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9.6.6 Channel 1 Volume Control Register (address = 0x05) [default = 0xCF]The Channel 1 Volume Control registers is shown in Figure 41 and described in Table 14.

Figure 41. Channel 1 Volume Control Register

7 6 5 4 3 2 1 0CH 1 VOLUMER/W-11001111

Table 14. Ch 1 Volume Control Field DescriptionsBit Field Type Reset Description7–0 CH 1 VOLUME R/W 11001111 8-Bit Volume Control for the output channel, 0.5 dB/step:

0xFF: 24 dB0xCF: 0 dB0x07: –100 dB< 0x07: MUTE

9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]The DC Diagnostic Control 1 register is shown in Figure 42 and described in Table 15.

Figure 42. DC Load Diagnostic Control 1 Register

7 6 5 4 3 2 1 0DC LDGABORT

2x_RAMP 2x_SETTLE RESERVED LDG LOENABLE

LDG BYPASS

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Table 15. DC Load Diagnostics Control 1 Field DescriptionsBit Field Type Reset Description7 DC LDG ABORT R/W 0 0: Default state, clear after abort

1: Aborts the load diagnostics in progress6 2x_RAMP R/W 0 0: Normal ramp time

1: Double ramp time5 2x_SETTLE R/W 0 0: Normal Settle time

1: Double settling time4–2 RESERVED R/W 000 RESERVED1 LDG LO ENABLE R/W 0 0: Line output diagnostics are disabled

1: Line output diagnostics are enabled0 LDG BYPASS R/W 0 0: Automatic diagnostics when leaving Hi-Z and after

channel fault1: Diagnostics are not run automatically

9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]The DC Diagnostic Control 2 register is shown in Figure 43 and described in Table 16.

Figure 43. DC Load Diagnostic Control 2 Register

7 6 5 4 3 2 1 0CH1 DC LDG SL RESERVED

R/W-0001


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Table 16. DC Load Diagnostics Control 2 Field DescriptionsBit Field Type Reset Description7–4 CH1 DC LDG SL R/W 0001 DC load diagnostics shorted-load threshold

0000: 0.5 Ω0001: 1 Ω0010: 1.5 Ω...1001: 5 Ω

3–0 RESERVED R/W 0001 RESERVED

9.6.9 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]DC Load Diagnostic Report 1 register is shown in Figure 44 and described in Table 17.

Figure 44. DC Load Diagnostic Report 1 Register

7 6 5 4 3 2 1 0CH1 S2G CH1 S2P CH1 OL CH1 SL RESERVED

R-0 R-0 R-0 R-0

Table 17. DC Load Diagnostics Report 1 Field DescriptionsBit Field Type Reset Description7 CH1 S2G R 0 0: No short-to-GND detected

1: Short-To-GND Detected6 CH1 S2P R 0 0: No short-to-power detected

1: Short-to-power detected5 CH1 OL R 0 0: No open load detected

1: Open load detected4 CH1 SL R 0 0: No shorted load detected

1: Shorted load detected3–0 RESERVED R 0000 RESERVED


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9.6.10 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]The DC Load Diagnostic Report, Line Output, register is shown in Figure 45 and described in Table 18.

Figure 45. DC Load Diagnostics Report 3 Line Output Register

7 6 5 4 3 2 1 0RESERVED CH1 LO LDG RESERVED

R-0

Table 18. DC Load Diagnostics Report 3 Line Output Field DescriptionsBit Field Type Reset Description7–4 RESERVED R 0000 RESERVED3 CH1 LO LDG R 0 0: No line output detected on channel 1

1: Line output detected on channel 12–0 RESERVED R 000 RESERVED

9.6.11 Channel State Reporting Register (address = 0x0F) [default = 0x40]The Channel State Reporting register is shown in Figure 46 and described in Table 19.

Figure 46. Channel State-Reporting Register

7 6 5 4 3 2 1 0CH1 STATE REPORT RESERVED

R-01

Table 19. State-Reporting Field DescriptionsBit Field Type Reset Description7–6 CH1 STATE REPORT R 01 00: PLAY

01: Hi-Z10: MUTE11: DC load diagnostics

5–0 RESERVED R 000000 RESERVED

9.6.12 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]The Channel Faults (overcurrent, DC detection) register is shown in Figure 47 and described in Table 20.

Figure 47. Channel Faults Register

7 6 5 4 3 2 1 0CH1 OC RESERVED CH1 DC RESERVED

R-0 R-0

Table 20. Channel Faults Field DescriptionsBit Field Type Reset Description7 CH1 OC R 0 0: No overcurrent fault detected

1: Overcurrent fault detected6–4 RESERVED R 000 RESERVED3 CH1 DC R 0 0: No DC fault detected

1: DC fault detected2–0 RESERVED R 000 RESERVED


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9.6.13 Global Faults 1 Register (address = 0x11) [default = 0x00]The Global Faults 1 register is shown in Figure 48 and described in Table 21.

Figure 48. Global Faults 1 Register

7 6 5 4 3 2 1 0RESERVED INVALID

CLOCKPVDD OV VBAT OV PVDD UV VBAT UV

R-0 R-0 R-0 R-0 R-0

Table 21. Global Faults 1 Field DescriptionsBit Field Type Reset Description7–5 RESERVED R 000 RESERVED4 INVALID CLOCK R 0 0: No clock fault detected

1: Clock fault detected3 PVDD OV R 0 0: No PVDD overvoltage fault detected

1: PVDD overvoltage fault detected2 VBAT OV R 0 0: No VBAT overvoltage fault detected

1: VBAT overvoltage fault detected1 PVDD UV R 0 0: No PVDD undervoltage fault detected

1: PVDD undervoltage fault detected0 VBAT UV R 0 0: No VBAT undervoltage fault detected

1: VBAT undervoltage fault detected

9.6.14 Global Faults 2 Register (address = 0x12) [default = 0x00]The Global Faults 2 register is shown in Figure 49 and described in Table 22.

Figure 49. Global Faults 2 Register

7 6 5 4 3 2 1 0RESERVED OTSD CH1 OTSD RESERVED

R-0 R-0

Table 22. Global Faults 2 Field DescriptionsBit Field Type Reset Description7–5 RESERVED R 000 RESERVED4 OTSD R 0 0: No global overtemperature shutdown

1: Global overtemperature shutdown3 CH1 OTSD R 0 0: No overtemperature shutdown on Ch1

1: Overtemperature shutdown on Ch12–0 RESERVED R 000 RESERVED

9.6.15 Warnings Register (address = 0x13) [default = 0x20]The Warnings register is shown in Figure 50 and described in Table 23.

Figure 50. Warnings Register

7 6 5 4 3 2 1 0RESERVED VDD POR OTW OTW CH1 RESERVED

R-1 R-0 R-0


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Table 23. Warnings Field DescriptionsBit Field Type Reset Description7–6 RESERVED R 00 RESERVED5 VDD POR R 1 0: No VDD POR has occurred

1: VDD POR occurred4 OTW R 0 0: No global overtemperature warning

1: Global overtemperature warning3 OTW CH1 R 0 0: No overtemperature warning on channel 1

1: Overtemperature warning on channel 12–0 RESERVED R 000 RESERVED

9.6.16 Pin Control Register (address = 0x14) [default = 0x00]The Pin Control register is shown in Figure 51 and described in Table 24.

Figure 51. Pin Control Register

7 6 5 4 3 2 1 0MASK OC MASK OTSD MASK UV MASK OV MASK DC RESERVED MASK CLIP MASK OTW

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Table 24. Pin Control Field DescriptionsBit Field Type Reset Description7 MASK OC R/W 0 0: Report overcurrent faults on the FAULT pin

1: Do not report overcurrent faults on the FAULT Pin6 MASK OTSD R/W 0 0: Report overtemperature faults on the FAULT pin

1: Do not report overtemperature faults on the FAULT pin5 MASK UV R/W 0 0: Report undervoltage faults on the FAULT pin

1: Do not report undervoltage faults on the FAULT pin4 MASK OV R/W 0 0: Report overvoltage faults on the FAULT pin

1: Do not report overvoltage faults on the FAULT pin3 MASK DC R/W 0 0: Report DC faults on the FAULT pin

1: Do not report DC faults on the FAULT pin2 RESERVED R/W 0 RESERVED1 MASK CLIP R/W 0 0: Report clipping on the configured pin (WARN or FAULT)

1: Do not report clipping on the configured pin (WARN orFAULT)

0 MASK OTW R/W 0 0: Report overtemperature warnings on the WARN pin1: Do not report overtemperature warnings on the WARN pin

9.6.17 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]The AC Load Diagnostic Control 1 register is shown in Figure 52 and described in Table 25.

Figure 52. AC Load Diagnostic Control 1 Register

7 6 5 4 3 2 1 0CH1 GAIN RESERVED CH1 ENABLE RESERVED

R/W-0 R/W-0


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Table 25. AC Load Diagnostic Control 1 Field DescriptionsBit Field Type Reset Description7 CH1: GAIN R/W 0 0: Gain 1

1: Gain 46–4 RESERVED R/W 000 RESERVED3 CH1 ENABLE R/W 0 0: AC diagnostics disabled

1: Enable AC diagnostics2–0 RESERVED R/W 000 RESERVED

9.6.18 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]The AC Load Diagnostic Control 2 register is shown in Figure 53 and described in Table 26.

Figure 53. AC Load Diagnostic Control 2 Register

7 6 5 4 3 2 1 0AC_DIAGS_LO

OPBACKRESERVED AC TIMING AC CURRENT RESERVED

R/W-0 R/W-0 R/W-0 R/W-0

Table 26. AC Load Diagnostic Control 2 Field DescriptionsBit Field Type Reset Description7 AC_DIAGS_LOOPBACK R/W 0 0: Disable AC Diag loopback

1: Enable AC Diag loopback6-5 RESERVED R/W 00 RESERVED4 AC TIMING R/W 0 0: 32 Cycles

1: 64 Cycles3-2 AC CURRENT R/W 00 00: 10mA

01: 19 mA10: RESERVED11: RESERVED

1-0 RESERVED R/W 00 RESERVED

9.6.19 AC Load Diagnostic Impedance Report Ch1 Register (address = 0x17) [default = 0x00]The AC Load Diagnostic Report Ch1 registers is shown in Figure 54 and described in Table 27.

Figure 54. AC Load Diagnostic Impedance Report Ch1 Register

7 6 5 4 3 2 1 0CH1 IMPEDANCE

R-00000000

Table 27. Ch1 AC LDG Impedance Report Field DescriptionsBit Field Type Reset Description7–0 CH1 IMPEDANCE R 00000000 8-bit AC-load diagnostic report for each channel with a step size

of 0.2496 Ω/bit (control by register 0x15 and register 0x16)0x00000000: 0 Ω0x00000001: 0.2496 Ω...0x11111111: 63.65 Ω


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9.6.20 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]The AC Load Diagnostic Phase High value registers is shown in Figure 55 and described in Table 28.

Figure 55. AC Load Diagnostic (LDG) Phase High Report Register

7 6 5 4 3 2 1 0AC Phase High

R-00000000

Table 28. AC LDG Phase High Report Field DescriptionsBit Field Type Reset Description7–0 AC Phase High R 00000000 Bit 15:8

9.6.21 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]The AC Load Diagnostic Phase Low value registers is shown in Figure 56 and described in Table 29.

Figure 56. AC Load Diagnostic (LDG) Phase Low Report Register

7 6 5 4 3 2 1 0AC Phase Low

R-00000000

Table 29. AC LDG Phase Low Report Field DescriptionsBit Field Type Reset Description7–0 AC Phase Low R 00000000 Bit 7:0

9.6.22 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]The AC Load Diagnostic STI High value registers is shown in Figure 57 and described in Table 30.

Figure 57. AC Load Diagnostic (LDG) STI High Report Register

7 6 5 4 3 2 1 0AC STI HighR-00000000

Table 30. AC LDG STI High Report Field DescriptionsBit Field Type Reset Description7–0 AC STI High R 00000000 Bit 15:8


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9.6.23 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]The AC Load Diagnostic STI Low value registers is shown in Figure 58 and described in Table 31.

Figure 58. AC Load Diagnostic (LDG) STI Low Report Register

7 6 5 4 3 2 1 0AC STI LowR-00000000

Table 31. Ch1 AC LDG STI Low Report Field DescriptionsBit Field Type Reset Description7–0 AC STI Low R 00000000 Bit 7:0



7 6 5 4 3 2 1 0CLEAR FAULT TDM SLOT

SIZEMASK ILIMIT

WARNINGRESERVED OTSD AUTO

RECOVERYRESERVED

R/W-0 R/W-0 R/W-0 R/W-0

Table 32. Misc Control 3 Field DescriptionsBit Field Type Reset Description7 CLEAR FAULT R/W 0 0: Normal operation

1: Clear fault6 TDM SLOT SIZE R/W 0 0: TDM slot size is 24-bit or 32-bit

1: TDM slot size is 16-bit5 MASK ILIMIT WARNING R/W 0 0: Report ILIMIT on the WARN pin

1: Do not report ILIMIT on the WARN pin4 RESERVED R/W 0 RESERVED3 OTSD AUTO RECOVERY R/W 0 0: OTSD is latched

1: OTSD is auto-recovery2–0 RESERVED R/W 000 RESERVED

9.6.25 Clip Control Register (address = 0x22) [default = 0x01]The Clip Detect register is shown in Figure 60 and described in Table 33. To ensure the Clip Detect Warning isoperating according to the expectation, the related bit values in the Clip Window Register (address = 0x23)[default = 0x14] and Clip Warning Register must be set accordingly.

Figure 60. Clip Control Register

7 6 5 4 3 2 1 0RESERVED CLIP_PIN CLIP_LATCH CLIPDET_EN

R/W-0 R/W-0 R/W-1

Table 33. Clip Control Field DescriptionsBit Field Type Reset Description7–3 RESERVED R/W 00000 RESERVED2 CLIP_PIN R/W 0 0: CH1 Clip Detect reports to WARN pin

1: CH1 Clip Detect reports to FAULT pin


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Table 33. Clip Control Field Descriptions (continued)Bit Field Type Reset Description1 CLIP_LATCH R/W 0 0: Pin latching

1: Pin non-latching0 CLIPDET_EN R/W 1 0: Clip detect disable

1: Clip Detect Enable

9.6.26 Clip Window Register (address = 0x23) [default = 0x14]The Clip Window register is shown in Figure 61 and described in Table 34. The register value represents theminimum number of 100% duty-cycle PWM cycles in hexadecimal notation before Clip Detect is reported. Aregister value of 0 is not permitted. If Clip Detect is set to non-latching, the register value has no function.

Figure 61. Clip Window Register

7 6 5 4 3 2 1 0CLIP_WINDOW_SEL[7:1]

R/W-00010100

Table 34. Clip Window Field DescriptionsBit Field Type Reset Description7–0 CLIP_WINDOW_SEL[7:1] R/W 00010100 00010100: 20 100% duty-cycle PWM cycles before Clip

Detect is triggered

9.6.27 Clip Warning Register (address = 0x24) [default = 0x00]The Clip Window register is shown in Figure 62 and described in Table 35.

Figure 62. Clip Warning Register

7 6 5 4 3 2 1 0RESERVED CH1_CLIP

R-0

Table 35. Clip Warning Field DescriptionsBit Field Type Reset Description7–1 RESERVED R 0000000 RESERVED0 CH1_CLIP R 0 0: No Clip Detect

1: Clip Detect

9.6.28 ILIMIT Status Register (address = 0x25) [default = 0x00]The ILIMIT Status register is shown in Figure 63 and described in Table 36.

Figure 63. ILIMIT Status Register

7 6 5 4 3 2 1 0RESERVED CH1_ILIMIT_W

ARNR-0

Table 36. ILIMIT Status Field DescriptionsBit Field Type Reset Description7–1 RESERVED R 0000000 RESERVED0 CH1_ILIMIT_WARN R 0 0: No ILIMIT

1: ILIMIT Warning


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45




9.6.29 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]The Miscellaneous Control 4 register is shown in and described in Table 37.


7 6 5 4 3 2 1 0RESERVED BCLK_INV HPF_CORNER[2:0]

R/W-0 R/W-000

Table 37. Misc Control 4 Field DescriptionsBit Field Type Reset Description7–4 RESERVED R/W 0100 RESERVED3 BCLK_INV R/W 0 0: All other MCLK/BCLK frequency / phase use cases

1: Inverted MCLK/BCLK phase relationship when MCLK/BCLKrun at the same frequency

2–0 HPF_CORNER[2:0] R/W 000 000: 3.7 Hz001: 7.4 Hz010: 15 Hz011: 30 Hz100: 59 Hz101: 118 Hz110: 235 Hz111: 463 Hz


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1 F

External AmplifierOutput Filter

1 F

1 F 1 nF

100 k 100 k

600 to

4.7 k 1 F 1 nF

3.3 µH

3.3 µH

46




10 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

10.1 Application InformationThe TAS6421-Q1 is a mono-channel class-D digital-input audio-amplifier design for use in automotive head unitsand external amplifier modules. The TAS6421-Q1 incorporates the necessary functionality to perform indemanding OEM applications.

10.1.1 AM-Radio Band AvoidanceAM-radio frequency interference can be avoided by setting the switching frequency of the device above the AMband. The switching frequency options available are 38 × fS, 44 × fS, and 48 × fS. If the switch frequency cannotbe set above the AM band, then use the two options of 8 × fS and 10 × fS. These options should be changed toavoid AM active channels.

10.1.2 Demodulation Filter DesignThe amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. Thesetransistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that isproportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal.The filter attenuates the high-frequency components of the output signals that are out of the audio band. Thedesign of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, tomeet the system THD+N requirements, the selection of the inductors used in the output filter should be carefullyconsidered.

10.1.3 Line Driver ApplicationsIn many automotive audio applications, the same head unit must drive either a speaker (with several ohms ofimpedance) or an external amplifier input (with several kiloohms of impedance). The design is capable ofsupporting both applications and has special line-drive gain and diagnostics. Coupled with the high switchingfrequency, the device is well suited for this type of application. Set the output channel in line driver mode throughI2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to 4.7 kΩ forthe DC line diagnostic to detect the connected external amplifier. Figure 65 shows the recommended externalamplifier input configuration.

Figure 65. External Amplifier Input Configuration for Line Driver


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VBAT

PVDD

1 F2

1

3

4

5

1 F

6

1 F

7

8

1 F

9

2.2 F

10

11

17

18

19

2 k 20

21

22

23

24

25

26

27

28

Micro

13

14

15

16

12

DSP

VDD

VCOM

AVDD

I2C ADDR0

I2C ADDR1

SDA

SCL

SDIN1

GND

SCLK

FSYNC

MCLK

STANDBY

MUTE

FAULT

WARN

AREF

VREG

GND

AVSS

GVDD

NC

GND

GND

GND

GND

PVDD

56

550.1 F 10 F

PVDDPVDD

PVDD

43

42

NC

NC

30

29

NC

NC

36NC

49NC

NC

NC

NC

54NC

53

52

51

50

NC

BST_M

OUT_P

OUT_M

48BST_P

47

46

45

44

GND

NC

NC

NC

41NC

40

39

38

37

NC

NC

NC

NC

35NC

34

33

32

31

NC

PVDD

1 F 1 nF100 F

PVDD

Input

Chassis GND

2 k

VDD

1 F

1 F 1 nF

1 nF1 F

1 F

3.3 H

3.3 H4

1 uF

47




10.2 Typical Applications

10.2.1 BTL ApplicationFigure 66 shows the schematic of a typical mono-channel solution in a typical use case.

Figure 66. TAS6421-Q1 Typical Mono-Channel BTL Application Schematic


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48




Typical Applications (continued)10.2.1.1 Design RequirementsUse the following requirements for this design:• This example is focused on the smallest solution size for 1× 25 W output power into 4 Ω with a battery supply

of 14.4 V.• The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which

results in a frequency of 2.11 MHz.• The selection of a 2.11 MHz switching frequency enables the use of a small output inductor value of 3.3 µH

which leads to a very small solution size.

10.2.1.1.1 Communication

All communications to the TAS6421-Q1 are through the I2C protocol. A system controller can communicate withthe device through the SDA pins and SCL pins. The TAS6421-Q1 is an I2C slave device and requires a master.The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by thedevice is 400 kHz. If multiple TAS6421-Q1 devices are on the same I2C bus, the I2C address must be differentfor each device. Up to four TAS6421-Q1 devices can be on the same I2C bus.

The I2C bus is shared internally.

NOTEComplete any internal operations, such as load diagnostics, before reading the registersfor the results.

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Hardware Design

Use the following procedure for the hardware design:• Determine the input format. The input format can be either I2S or TDM mode. The mode determines the

correct pin connections and the I2C register settings.• Determine the power output that is required into the load. The power requirement determines the required

power-supply voltage and current. The output reconstruction-filter components that are required are alsodriven by the output power.

• With the requirements, adjust the typical application schematic in Figure 66 for the input connections.

10.2.1.2.2 Digital Input and the Serial Audio Port

The TAS6421-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left Justified,and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The supportedfrequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see SAP Control (Serial Audio-Port Control) Register(address = 0x03) [default = 0x04] for the complete matrix to set up the serial audio port.

NOTEBits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting upall the control registers to the system requirements should be done before the device isplaced in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21to clear any faults. Then read the fault registers to make sure no faults are present. Whenno faults are present, use register 0x04 to place the device properly into play mode.

10.2.1.2.3 Bootstrap Capacitors

The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must besized appropriately for the system specification. A special condition can occur where the bootstrap may sag if thecapacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly lessthan 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF fordriving subwoofers that require frequencies below 30 Hz may be necessary.


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Output Power (W)

Tota

l H

arm

onic

Dis

tort

ion +

No

ise (

%)

0.001

0.01

0.1

1

10

10m 100m 1 10 100

2 : Load4 : Load

Supply Voltage (V)

Ou

tpu

t P

ow

er

(W)

5 7 9 11 13 15 17 19 21 23 25 260

10

20

30

40

50

60

70

80

90

1002 : Load4 : Load

49




Typical Applications (continued)10.2.1.2.4 Output Reconstruction Filter

The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off orfully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of theaudio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitorto ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduceselectromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. Refer to the Class-DLC Filter Design Application Report for a detailed description of proper component description and design of theLC filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency ofthe LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as100 kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency shouldbe less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value isgiven at zero current, but the TAS6421-Q1 device has current. Use the inductance versus current curve for theinductor to make sure the inductance does not drop below 1 µH (for fSW = 2.1 MHz) at the maximum currentprovided by the system design. The DCR of the inductor directly affects the output power of the system design.The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4 Ω system is 40to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ. Further guidance is provided in the Inductor Selection Guide for2.1 MHz Class-D Amplifiers.

10.2.2 Application Curves

fSW = 2.1 MHz


10% THD fSW = 2.1 MHz



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http://www.ti.com/lit/pdf/SLAA701A

http://www.ti.com/lit/pdf/SLAA701A

http://www.ti.com/lit/pdf/SLOA242A

http://www.ti.com/lit/pdf/SLOA242A

50




11 Power Supply RecommendationsThe TAS6421-Q1 requires three power supplies. The PVDD supply is the high-current supply in therecommended supply range. The VBAT supply is a lower current supply that must be in the recommendedsupply range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply rangefor VBAT is maintained. The VDD supply is the 3.3 Vdc logic supply and must be maintained in the tolerance asshown in the Recommended Operating Conditions table.

For best device performance and to avoid unexpected device behavior follow the recommendations in theVehicle-Battery Power-Supply Sequence section.

12 Layout

12.1 Layout GuidelinesThe pinout of the TAS6421-Q1 was selected to provide flowthrough layout with all high-power connections on theright side, and all low-power signals and supply decoupling on the left side.

Figure 69 shows the area for the components in the application example (see the Typical Applications section).

The TAS6421-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize powerloss.

The small value of the output filter provides a small size and, in this case, the low height of the inductor enablesdouble-sided mounting.

The EVM PCB shown in Figure 69 is the basis for the layout guidelines.

12.1.1 Electrical Connection of Thermal pad and Heat SinkFor the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND.The thermal pad must not be connected to any other electrical node.

12.1.2 EMI ConsiderationsAutomotive-level EMI performance depends on both careful integrated circuit design and good system-leveldesign. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of thedesign. The design has minimal parasitic inductances because of the short leads on the package which reducesthe EMI that results from current passing from the die to the system PCB. Each channel also operates at adifferent phase. The design also incorporates circuitry that optimizes output transitions that cause EMI.

For optimizing the EMI a solid ground layer plane is recommended, for a PCB design that fulfills the CISPR25level 5 requirements, see the TAS6421-Q1 EVM layout.

12.1.3 General GuidelinesThe EVM layout is optimized for low noise and EMC performance.

The TAS6421-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider anexternal heat sink.

Refer to Figure 69 for the following guidelines:• A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop

impedance for the high-frequency switching current.• The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the

ground pins.• The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also

the ground return for each channel is the shared. This direct path allows for improved common mode EMIrejection.

• The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for thesmallest loop of large switching currents.

• Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package toground.


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51




Layout Guidelines (continued)• Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power

supply.

12.2 Layout Example

Figure 69. Mono Channel EVM Layout

12.3 Thermal ConsiderationsThe thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The outputpower of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed onit by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6421-Q1and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can becontinually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier designbecause of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,therefore, RθJC is used as the thermal resistance from junction to the exposed metal package. This resistancedominates the thermal management, so other thermal transfers are not considered. The thermal resistance ofRθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprisedof the following components:• RθJC of the TAS6421-Q1• Thermal resistance of the thermal interface material• Thermal resistance of the heat sink


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52




Thermal Considerations (continued)The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for thearea thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, atypical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. TheTAS6421-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance bythe exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of thethermal grease is 0.094°C/W

Table 38 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease examplepreviously described is used for the thermal interface material. Use Equation 3 to design the thermal system.

RθJA = RθJC + thermal interface resistance + heat sink resistance (3)

Table 38. Thermal ModelingDescription Value

Ambient Temperature 25°CAverage Power to load 10W

Power dissipation 2WJunction Temperature 115°CΔT inside package 1.8°C (0.9°C/W × 2W)

ΔT through thermal interface material 0.188°C (0.094°C/W × 2W)Required heat sink thermal resistance 44.0°C/W ([115°C – 25°C – 1.8°C – 0.188°C] / 2W)

System thermal resistance to ambient RθJA 45.1°C/W


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53




13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related DocumentationFor related documentation see the following:• PurePath™ Console 3 Graphical Development Suite• TAS6421-Q1 EVM User's Guide (SLOU415)

13.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

13.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

E2E Audio Amplifier Forum TI's Engineer-to-Engineer (E2E) Community for Audio Amplifiers. Created tofoster collaboration among engineers. Ask questions and receive answers in real-time.

13.4 TrademarksBurr-Brown, PurePath, E2E are trademarks of Texas Instruments.

13.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

13.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.


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http://www.ti.com/tool/purepathconsole

http://www.ti.com/lit/pdf/SLOU415

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TAS6421QDKQRQ1 ACTIVE HSSOP DKQ 56 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TAS6421

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

http://www.ti.com/product/TAS6421-Q1?CMP=conv-poasamples#samplebuy

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TAS6421QDKQRQ1 HSSOP DKQ 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Oct-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TAS6421QDKQRQ1 HSSOP DKQ 56 1000 367.0 367.0 55.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Oct-2019

Pack Materials-Page 2

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PACKAGE OUTLINE

C10.6710.03 TYP

54X 0.635

56X 0.370.17

2X17.15

0.250.13 TYP

0 - 80.080.00

8.6618.611

5.5335.483

2.4752.240

NOTE 6

(2.29)

2.29 0.050.25

GAGE PLANE

1.020.51

A

18.5418.29

NOTE 3

B 7.597.39

NOTE 4

PowerPAD HSSOP - 2.475 mm max heightDKQ0056APLASTIC SMALL OUTLINE

4221870/D 01/2019

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. The exposed thermal pad is designed to be attached to an external heatsink.6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body thickness dimension.

PowerPAD is a trademark of Texas Instruments.

TM

1 56

0.13 C A B

2928

PIN 1 ID AREA

EXPOSEDTHERMAL PAD

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 1.000

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EXAMPLE BOARD LAYOUT

(9.5)

0.05 MAXAROUND

0.05 MINAROUND

56X (1.9)

56X (0.4)

54X (0.635)

(R0.05) TYP


4221870/D 01/2019

SYMM

SYMM

SEE DETAILS

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:6X

1

28 29

56

TM

NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 9. Size of metal pad may vary due to creepage requirement.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILSNOT TO SCALE

EXPOSED METAL

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

56X (1.9)

56X (0.4)

54X (0.635)

(9.5)(R0.05) TYP


4221870/D 01/2019

NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design.

TM

SYMM

SYMM

1

28 29

56

SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCIL

SCALE:6X

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

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