tda8927 power stage 2 x 80 w class-d audio amplifierskory.gylcomp.hu/alkatresz/tda8927th,j.pdfpower...

DATA SHEET

Preliminary specificationSupersedes data of 2001 Dec 11

2002 Oct 22

INTEGRATED CIRCUITS

TDA8927Power stage 2 × 80 W class-Daudio amplifier

2002 Oct 22 2

Philips Semiconductors Preliminary specification

Power stage 2 × 80 W class-D audioamplifier

TDA8927

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 Power stage8.2 Protection8.2.1 Overtemperature8.2.2 Short-circuit across the loudspeaker terminals8.3 BTL operation

9 LIMITING VALUES

10 THERMAL CHARACTERISTICS

11 QUALITY SPECIFICATION

12 DC CHARACTERISTICS

13 AC CHARACTERISTICS

14 SWITCHING CHARACTERISTICS

14.1 Duty factor

15 TEST AND APPLICATION INFORMATION

15.1 BTL application15.2 Package ground connection15.3 Output power15.4 Reference design15.5 Reference design bill of materials15.6 Curves measured in reference design

16 PACKAGE OUTLINES

17 SOLDERING

17.1 Introduction to soldering through-hole mountpackages

17.2 Soldering by dipping or by solder wave17.3 Manual soldering17.4 Suitability of through-hole mount IC packages

for dipping and wave soldering methods

18 DATA SHEET STATUS

19 DEFINITIONS

20 DISCLAIMERS

2002 Oct 22 3



TDA8927

1 FEATURES

• High efficiency (>94%)

• Operating voltage from ±15 to ±30 V

• Very low quiescent current

• High output power

• Short-circuit proof across the load, only in combinationwith controller TDA8929T

• Diagnostic output

• Usable as a stereo Single-Ended (SE) amplifier or as amono amplifier in Bridge-Tied Load (BTL)

• Electrostatic discharge protection (pin to pin)

• Thermally protected, only in combination with controllerTDA8929T.

2 APPLICATIONS

• Television sets

• Home-sound sets

• Multimedia systems

• All mains fed audio systems

• Car audio (boosters).

3 GENERAL DESCRIPTION

The TDA8927 is the switching power stage of a two-chipset for a high efficiency class-D audio power amplifiersystem. The system is split into two chips:

• TDA8927J; digital power stage in a DBS17P package

• TDA8929T; analog controller chip in a SO24 package.

With this chip set a compact 2 × 80 W audio amplifiersystem can be built, operating with high efficiency and verylow dissipation. No heatsink is required, or depending onsupply voltage and load, a very small one. The systemoperates over a wide supply voltage range from±15 up to ±30 V and consumes a very low quiescentcurrent.

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

General; VP = ±25 V

VP supply voltage ±15 ±25 ±30 V

Iq(tot) total quiescent current no load connected − 35 45 mA

η efficiency Po = 30 W − 94 − %

Stereo single-ended configuration

Po output power RL = 4 Ω; THD = 10%; VP = ±25 V 60 65 − W

RL = 4 Ω; THD = 10%; VP = ±27 V 74 80 − W

Mono bridge-tied load configuration

Po output power RL = 4 Ω; THD = 10%; VP = ±17 V 90 110 − W

RL = 8 Ω; THD = 10%; VP = ±25 V 120 150 − W

TYPE NUMBERPACKAGE

NAME DESCRIPTION VERSION

TDA8927J DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1

2002 Oct 22 4



TDA8927

6 BLOCK DIAGRAM

MGW138

handbook, full pagewidth

CONTROLAND

HANDSHAKE

DRIVERHIGH

TDA8927J

TEMPERATURE SENSORAND

CURRENT PROTECTION

DRIVERLOW

temp

current

4

7

VSS1

VSS1 VSS2

VDD2

6

1

2

9

8 10

VDD2 VDD1

13 5

CONTROLAND

HANDSHAKE

DRIVERHIGH

DRIVERLOW

14

11

12

17

16

3

15

EN1

DIAG

REL1

SW1

SW2

REL2

POWERUP

EN2

BOOT1

OUT1

STAB

OUT2

BOOT2

Fig.1 Block diagram.

2002 Oct 22 5



TDA8927

7 PINNING

SYMBOL PIN DESCRIPTION

SW1 1 digital switch input; channel 1

REL1 2 digital control output;channel 1

DIAG 3 digital open-drain output forovertemperature andovercurrent report

EN1 4 digital enable input;channel 1

VDD1 5 positive power supply;channel 1

BOOT1 6 bootstrap capacitor;channel 1

OUT1 7 PWM output; channel 1

VSS1 8 negative power supply;channel 1

STAB 9 decoupling internal stabilizerfor logic supply

VSS2 10 negative power supply;channel 2

OUT2 11 PWM output; channel 2

BOOT2 12 bootstrap capacitor;channel 2

VDD2 13 positive power supply;channel 2

EN2 14 digital enable input;channel 2

POWERUP 15 enable input for switching oninternal reference sources

REL2 16 digital control output;channel 2

SW2 17 digital switch input; channel 2

handbook, halfpage

TDA8927J

MGW142

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

VSS1

VSS2

VDD2

VDD1

EN1

DIAG

REL1

SW1

SW2

REL2

POWERUP

EN2

BOOT1

OUT1

STAB

OUT2

BOOT2

Fig.2 Pin configuration.

2002 Oct 22 6



TDA8927

8 FUNCTIONAL DESCRIPTION

The combination of the TDA8927 and the TDA8929Tproduces a two-channel audio power amplifier systemusing the class-D technology (see Fig.3). In the TDA8929Tcontroller the analog audio input signal is converted into adigital Pulse Width Modulation (PWM) signal.

The power stage TDA8927 is used for driving the low-passfilter and the loudspeaker load. It performs a level shiftfrom the low-power digital PWM signal, at logic levels, to ahigh-power PWM signal that switches between the mainsupply lines. A 2nd-order low-pass filter converts thePWM signal into an analog audio signal across theloudspeaker.

For a description of the controller, see data sheet“TDA8929T, Controller class-D audio amplifier”.

8.1 Power stage

The power stage contains the high-power DMOSswitches, the drivers, timing and handshaking between thepower switches and some control logic. For protection, atemperature sensor and a maximum current detector arebuilt-in on the chip.

For interfacing with the controller chip the followingconnections are used:

• Switch (pins SW1 and SW2): digital inputs; switchingfrom VSS to VSS + 12 V and driving the power DMOSswitches

• Release (pins REL1 and REL2): digital outputs toindicate switching from VSS to VSS + 12 V, followpins SW1 and SW2 with a small delay

• Enable (pins EN1 and EN2): digital inputs; at a level ofVSS the power DMOS switches are open and the PWMoutputs are floating; at a level of VSS + 12 V the powerstage is operational and controlled by the switch pin ifpin POWERUP is at VSS + 12 V

• Power-up (pin POWERUP): must be connected to acontinuous supply voltage of at least VSS + 5 V withrespect to VSS

• Diagnostics (pin DIAG): digital open-drain output; pulledto VSS if the temperature or maximum current isexceeded.

8.2 Protection

Temperature and short-circuit protection sensors areincluded in the TDA8927 power stage. The protectioncircuits are operational only in combination with theTDA8929T. In the event that the maximum current ormaximum temperature is exceeded the diagnostic outputis activated. The controller has to take appropriatemeasures by shutting down the system.

8.2.1 OVERTEMPERATURE

If the junction temperature (Tj) exceeds 150 °C, thenpin DIAG becomes LOW. The diagnostic pin is released ifthe temperature is dropped to approximately 130 °C, sothere is a hysteresis of approximately 20 °C.

8.2.2 SHORT-CIRCUIT ACROSS THE LOUDSPEAKER

TERMINALS

When the loudspeaker terminals are short-circuited thiswill be detected by the current protection. If the outputcurrent exceeds the maximum output current of 7.5 A,then pin DIAG becomes LOW. The controller should shutdown the system to prevent damage. Using the TDA8929Tthe system is shut down within 1 µs, and after 220 ms it willattempt to restart the system again. During this time thedissipation is very low, therefore the average dissipationduring a short-circuit is practically zero.

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2002O

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Philips S

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Prelim

inary specification

Pow

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80W

class-D audio

amplifier

TD

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1

4IN1−PWM1

5IN1+

IN2+

IN2−

mute

mute

SGND

SGND

SGND1

SGND2

3

20

REL123

SW124

EN1

REL1

SW1

EN1

STAB

DIAGCUR

DIAGTMP

SW2

REL2

PWM2

21

22

19

15

13

EN2

SW2

REL2

EN216

14

17

6

11

8

9

7

2

Rfb

Rfb

INPUTSTAGE

INPUTSTAGE

TDA8929T

PWMMODULATOR

PWMMODULATOR

MODE

STABISTAB

POWERUP

OSCILLATOR MANAGER

VSSA VDDA

VSS1 VDD1

12 10

VSSA VDDA

VSS2(sub) VSSDVDD2

VMODE

VSSA

MODE

OSCROSC

18

MGU388

DIAG

CONTROLAND

HANDSHAKE

DRIVERHIGH

TDA8927J


CURRENT PROTECTION

DRIVERLOW

2

7

+25 V

−25 V

VSS1

VSS1

VSSA

VSS2

VSSD

VDDD

VDD2

VDDA

6

1

4

9

8 10

VDD2 VDD1

13 5

CONTROLAND

HANDSHAKE

DRIVERHIGH

DRIVERLOW

14

11

12

17

16

3

15

BOOT1

OUT1

OUT2

BOOT2

SGND(0 V)

Vi(1)

Vi(2)

Fig.3 Typical application schematic of the class-D system using TDA8929T and the TDA8927J.

2002 Oct 22 8



TDA8927

8.3 BTL operation

BTL operation can be achieved by driving the audio inputchannels of the controller in the opposite phase and byconnecting the loudspeaker with a BTL output filterbetween the two PWM output pins of the power stage(see Fig.4).

In this way the system operates as a mono BTL amplifierand with the same loudspeaker impedance a four timeshigher output power can be obtained.

For more information see Chapter 15.

MGU386


CONTROLAND

HANDSHAKE

DRIVERHIGH

TDA8927J


CURRENT PROTECTION

DRIVERLOW

temp

current

4

7

VSS1

VSS1 VSS2

VDD2

6

1

2

9

8 10

VDD2 VDD1

13 5

CONTROLAND

HANDSHAKE

DRIVERHIGH

DRIVERLOW

14

11

12

17

16

3

15

EN1

DIAG

REL1

SW1

SW2

REL2

POWERUP

EN2

BOOT1

OUT1

STAB

OUT2

BOOT2

SGND(0 V)

Fig.4 Mono BTL application.

2002 Oct 22 9



TDA8927

9 LIMITING VALUESIn accordance with the Absolute Maximum Rate System (IEC 60134).

Notes

1. Human Body Model (HBM); Rs = 1500 Ω; C = 100 pF.

2. Machine Model (MM); Rs = 10 Ω; C = 200 pF; L = 0.75 µH.

10 THERMAL CHARACTERISTICS

11 QUALITY SPECIFICATION

In accordance with “SNW-FQ611-part D” if this type is used as an audio amplifier (except for ESD, see also Chapter 9).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VP supply voltage − ±30 V

VP(sc) supply voltage forshort-circuits across the load

− ±30 V

IORM repetitive peak current inoutput pins

− 7.5 A

Tstg storage temperature −55 +150 °CTamb ambient temperature −40 +85 °CTvj virtual junction temperature − 150 °CVes(HBM) electrostatic discharge

voltage (HBM)note 1

all pins with respect to VDD (class 1a) −500 +500 V

all pins with respect to VSS (class 1a) −1500 +1500 V

all pins with respect to each other(class 1a)

−1500 +1500 V

Ves(MM) electrostatic dischargevoltage (MM)

note 2

all pins with respect to VDD (class B) −250 +250 V

all pins with respect to VSS (class B) −250 +250 V

all pins with respect to each other(class B)

−250 +250 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W

Rth(j-c) thermal resistance from junction to case in free air 1.0 K/W

2002 Oct 22 10



TDA8927

12 DC CHARACTERISTICSVP = ±25 V; Tamb = 25 °C; measured in test diagram of Fig.6; unless otherwise specified.

Notes

1. The circuit is DC adjusted at VP = ±15 to ±30 V.

2. Temperature sensor or maximum current sensor activated.


Supply

VP supply voltage note 1 ±15 ±25 ±30 V

Iq(tot) total quiescent current no load connected − 35 45 mA

outputs floating − 5 10 mA

Internal stabilizer logic supply (pin STAB)

VO(STAB) stabilizer output voltage 11 13 15 V

Switch inputs (pins SW1 and SW2)

VIH HIGH-level input voltage referenced to VSS 10 − VSTAB V

VIL LOW-level input voltage referenced to VSS 0 − 2 V

Control outputs (pins REL1 and REL2)

VOH HIGH-level output voltage referenced to VSS 10 − VSTAB V

VOL LOW-level output voltage referenced to VSS 0 − 2 V

Diagnostic output (pin DIAG, open-drain)

VOL LOW-level output voltage IDIAG = 1 mA; note 2 0 − 1.0 V

ILO output leakage current no error condition − − 50 µA

Enable inputs (pins EN1 and EN2)

VIH HIGH-level input voltage referenced to VSS − 9 VSTAB V

VIL LOW-level input voltage referenced to VSS 0 5 − V

VEN(hys) hysteresis voltage − 4 − V

II(EN) input current − − 300 µA

Switching-on input (pin POWERUP)

VPOWERUP operating voltage referenced to VSS 5 − 12 V

II(POWERUP) input current VPOWERUP = 12 V − 100 170 µA

Temperature protection

Tdiag temperature activating diagnostic VDIAG = VDIAG(LOW) 150 − − °CThys hysteresis on temperature

diagnosticVDIAG = VDIAG(LOW) − 20 − °C

2002 Oct 22 11



TDA8927

13 AC CHARACTERISTICS

Notes

1. VP = ±25 V; RL = 4 Ω; fi = 1 kHz; fosc = 310 kHz; Rs = 0.1 Ω (series resistance of filter coil); Tamb = 25 °C; measuredin reference design (SE application) shown in Fig.7; unless otherwise specified.

2. Indirectly measured; based on Rds(on) measurement.

3. Total Harmonic Distortion (THD) is measured in a bandwidth of 22 Hz to 22 kHz. When distortion is measured usinga low-order low-pass filter a significantly higher value will be found, due to the switching frequency outside the audioband.

4. Efficiency for power stage; output power measured across the loudspeaker load.

5. VP = ±25 V; RL = 8 Ω; fi = 1 kHz; fosc = 310 kHz; Rs = 0.1 Ω (series resistance of filter coil); Tamb = 25 °C; measuredin reference design (BTL application) shown in Fig.7; unless otherwise specified.


Single-ended application; note 1

Po output power RL = 4 Ω; VP = ±25 V

THD = 0.5% 50(2) 55 − W

THD = 10% 60(2) 65 − W

RL = 4 Ω; VP = ±27 V

THD = 0.5% 60(2) 65 − W

THD = 10% 74(2) 80 − W

THD total harmonic distortion Po = 1 W; note 3

fi = 1 kHz − 0.01 0.05 %

fi = 10 kHz − 0.1 − %

Gv(cl) closed-loop voltage gain 29 30 31 dB

η efficiency Po = 30 W; fi = 1 kHz; note 4 − 94 − %

Mono BTL application; note 5

Po output power RL = 8 Ω; VP = ±25 V

THD = 0.5% 100(2) 112 − W

THD = 10% 128(2) 140 − W

RL = 4 Ω; VP = ±17 V

THD = 0.5% 80(2) 87 − W

THD = 10% 100(2) 110 − W

THD total harmonic distortion Po = 1 W; note 3

fi = 1 kHz − 0.01 0.05 %

fi = 10 kHz − 0.1 − %

Gv(cl) closed loop voltage gain 35 36 37 dB

η efficiency Po = 30 W; fi = 1 kHz; note 4 − 94 − %

2002 Oct 22 12



TDA8927

14 SWITCHING CHARACTERISTICSVP = ±25 V; Tamb = 25 °C; measured in Fig.6; unless otherwise specified.

Note

1. When used in combination with TDA8929T controller, the effective minimum pulse width during clipping is 0.5tW(min).

14.1 Duty factor

For the practical useable minimum and maximum duty factor (δ) which determines the maximum output power:

× 100% < δ < × 100%

Using the typical values: 3.5% < δ < 96.5%.


PWM outputs (pins OUT1 and OUT2); see Fig.5

tr rise time − 30 − ns

tf fall time − 30 − ns

tblank blanking time − 70 − ns

tPD propagation delay from pin SW1 (SW2) topin OUT1 (OUT2)

− 20 − ns

tW(min) minimum pulse width note 1 − 220 270 ns

Rds(on) on-resistance of the outputtransistors

− 0.2 0.3 Ω

tW(min) fosc×2

------------------------------- 1tW(min) fosc×

2-------------------------------–

2002 Oct 22 13



TDA8927


MGW145

PWMoutput

(V)

VDD

VSS

0 V

tblanktftr

1/fosc

100 ns

VSTAB

VSS

VSW(V)

tPD

VSTAB

VSS

VREL(V)

Fig.5 Timing diagram PWM output, switch and release signals.

2002O

ct2214

Philips S

emiconductors

Prelim

inary specification

Pow

er stage 2×

80W

class-D audio

amplifier

TD

A8927


15T

ES

T A

ND

AP

PLIC

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N IN

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andbook, full pagewidth

12 kΩ15 nF

MGW184

15 nF100nF

CONTROLAND

HANDSHAKE

DRIVERHIGH

TDA8927J


CURRENT PROTECTION

DRIVERLOW

temp

current

4

7

VSS1

VSS1

VREL2VSS2

VDD2

6

1

2

9

8 10

VDD2 VDD1

13 5

CONTROLAND

HANDSHAKE

DRIVERHIGH

DRIVERLOW

14

11

12

17

16

3

15

EN1

DIAG

REL1

SW1

SW2

REL2

POWERUP

EN2

BOOT1

2VDD

OUT1

STAB

OUT2

VOUT2

VOUT1

BOOT212 V

V

V

V

VSW2VREL1

V

VSW1VEN

12 V0

VDIAG

V

VSTAB

V

12 V0

Fig.6 Test diagram.

2002 Oct 22 15



TDA8927

15.1 BTL application

When using the system in a mono BTL application (for more output power), the inputs of both channels of the PWMmodulator must be connected in parallel; the phase of one of the inputs must be inverted. In principle the loudspeakercan be connected between the outputs of the two single-ended demodulation filters.

15.2 Package ground connection

The heatsink of the TDA8927J/ST is connected internally to VSS.

15.3 Output power

The output power in single-ended applications can be estimated using the formula

The maximum current should not exceed 7.5 A.

The output power in BTL applications can be estimated using the formula

The maximum current should not exceed 7.5 A.

Where:

RL = load impedance

Rs = series resistance of filter coil

Po(1%) = output power just at clipping

The output power at THD = 10%: Po(10%) = 1.25 × Po(1%).

15.4 Reference design

The reference design for a two-chip class-D audio amplifier for TDA8927J and TDA8929T is shown in Fig.7. ThePrinted-Circuit Board (PCB) layout is shown in Fig.8. The bill of materials is given in Table 1.

Po(1%)

RL

RL Rds(on) Rs+ +( )------------------------------------------------ VP 1 tW(min) fosc×–( )××2

2 RL×--------------------------------------------------------------------------------------------------------------------------=

IO(max)

VP 1 tW(min) fosc×–( )×[ ]RL Rds(on) Rs+ +

----------------------------------------------------------------=

Po(1%)

RL

RL 2 Rds(on) Rs+( )×+---------------------------------------------------------- 2VP 1 tW(min) fosc×–( )××

2

2 RL×----------------------------------------------------------------------------------------------------------------------------------------=

IO(max)

2VP 1 tW(min) fosc×–( )×[ ]RL 2 Rds(on) Rs+( )×+

---------------------------------------------------------------------=


2002O

ct2216

Philips S

emiconductors

Prelim

inary specification

Pow

er stage 2×

80W

class-D audio

amplifier

TD

A8927

hand

book

, ful

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thMLD633

39 kΩ

R1939 kΩ

R710 kΩ

220 nFC2R20

1 kΩ

R10

Sumida 33 µHCDRH127-330

L4

Sumida 33 µHCDRH127-330

L2

GND

220 nF

C44220 nF

C1

3

6 17PWM2

5

4

8

9

10 12

15

n.c.

1

1 nF

C29

input 2input 1

J5

J6

D1(5.6 V)

D2(7.5 V)

IN1+

IN1−

GND

2

11

SGND1

SGND2

S1

VSSA

VSS1VSS2

VDDA

VDD2VDD1

GND

1

2

1

2

1

2

QGND

QGND

QGND

QGND

OUT1−

OUT1+

OUT1+

OUT2−

OUT2−

OUT2+BOOT2

BOOT1

OUT1

OUT2

VDDDVDD1

VDD2

VSS2

VSS1

VDDD

VSSD

VSSA VSSD

27 kΩ

R17

220 nF

C3

OSC

POWERUP

VSSA

220 nF

C5

MODE

VDDA

R24200 kΩ

VDDD

onmute

off

U2

TDA8929T

CONTROLLERC22

330 pF

C27470 nF

C4220 nF C7

220 nF

C14470 nF

C181 nF

C191 nF

C201 nF

C211 nF

C16470 nF

C6220 nF

C915 nF

C815 nF

C43180 pF

IN2+

IN2−

R6 10 kΩ

C26470 nF

R410 kΩ

1 nF

C28

C24470 nF

R5 10 kΩ

J3J1

QGND QGND

inputs

outputs

power supply

mode select

J4

J2

VSS

C25470 nF

C23330 pF

R115.6 Ω

C10560 pF

VSSD

VDDD VSSD

R125.6 Ω

R135.6 Ω

R145.6 Ω

C11560 pF

C12560 pF

C13560 pF

R229.1 kΩ

VSSD

VSSA

VDDA

VDDD

C311 nF

C301 nF

C33220 nF

C351500 µF(35 V)

R2110 kΩ

C32220 nF

C341500 µF(35 V)

C38220 nF

C39220 nF

C4147 µF(35 V)

C36220 nF

C37220 nF

C4047 µF(35 V)

GND

QGND

QGND

beadL6

L5bead

L7bead

GND

VDD

VSS

+25 V

−25 V

1

2

3

13SW2

14REL2

16EN2

SW2

REL2

EN2

21

PWM1

23SW1

24

15

9

3

U1

TDA8926Jor

TDA8927J

POWER STAGE

17

16

14

4

2

1

8

10

13

5

6

7

11

12

REL1

20

EN1

SW1

REL1

EN1

19STAB

STAB18

VSSD

22DIAGCUR

DIAG

R1624 Ω

R1524 Ω

4 or 8 ΩSE

4 or 8 ΩSE

8 ΩBTL

C17220 nF

C15220 nF

Fig.7 Two-chip class-D audio amplifier application diagram for TDA8927J and TDA8929T.

R21 and R22 are necessary only in BTL applications with asymmetrical supply.

BTL: remove R6, R7, C23, C26 and C27 and close J5 and J6.

C22 and C23 influence the low-pass frequency response and should be tuned with the real load (loudspeaker).

Inputs floating or inputs referenced to QGND (close J1 and J4) or referenced to VSS (close J2 and J3) for an input signal ground reference.


2002O

ct2217

Philips S

emiconductors

Prelim

inary specification

Pow

er stage 2×

80W

class-D audio

amplifier

TD

A8927


MLD634

C24

D1

TDA8926J/27J & TDA8929T

Copper top, top view

Copper bottom, top view

Silk screen top, top view

Silk screen bottom, top view

D2

L7

L5

In1

GN

D

In2

Out1 Out2

state of D artVersion 21 03-2001

U1

C25C34

C35

C40

C26

C27

L6

ONMUTEOFF

C41

C16

C14

S1

R20

R1

R21L2

L4

R22

C38

U2

C39

C36

R24

R5

R4 R6

R7

C2

C31C30C18

C19

C20

C21

C1

C9

C8

J4

J5

J6

J1J3J2

R19

C13

C33

C32

C11

C29C28

R14

R12

C3

C43R10

C12

C17

R16

C15

R15

R13

R11C10

C5

C37

C22C23

C44

VD

D

VS

S

In1

Out1 Out2

GND

In2

QGND

VDD VSS

C7

C4

C6

Fig.8 Printed-circuit board layout for TDA8927J and TDA8929T.

2002 Oct 22 18



TDA8927

15.5 Reference design bill of materials

Table 1 Two-chip class-D audio amplifier PCB (Version 2.1; 03-2001) for TDA8927J and TDA8929T (seeFigs 7 and 8)

COMPONENT DESCRIPTION VALUE COMMENTS

In1 and In2 Cinch input connectors 2 × Farnell: 152-396

Out1, Out2, VDD,GND and VSS

supply/output connectors 2 × Augat 5KEV-02;1 × Augat 5KEV-03

S1 on/mute/off switch PCB switch Knitter ATE 1 E M-O-M

U1 power stage IC TDA8926J/27J DBS17P package

U2 controller IC TDA8929T SO24 package

L2 and L4 demodulation filter coils 33 µH 2 × Sumida CDRH127-330

L5, L6 and L7 power supply ferrite beads 3 × Murata BL01RN1-A62

C1 and C2 supply decoupling capacitors forVDD to VSS of the controller

220 nF/63 V 2 × SMD1206

C3 clock decoupling capacitor 220 nF/63 V SMD1206

C4 12 V decoupling capacitor of thecontroller

220 nF/63 V SMD1206

C5 12 V decoupling capacitor of the powerstage

220 nF/63 V SMD1206

C6 and C7 supply decoupling capacitors forVDD to VSS of the power stage

220 nF/63 V SMD1206

C8 and C9 bootstrap capacitors 15 nF/50 V 2 × SMD0805

C10, C11,C12 and C13

snubber capacitors 560 pF/100 V 4 × SMD0805

C14 and C16 demodulation filter capacitors 470 nF/63 V 2 × MKT

C15 and C17 resonance suppress capacitors 220 nF/63 V 2 × SMD1206

C18, C19,C20 and C21

common mode HF coupling capacitors 1 nF/50 V 4 × SMD0805

C22 and C23 input filter capacitors 330 pF/50 V 2 × SMD1206

C24, C25,C26 and C27

input capacitors 470 nF/63 V 4 × MKT

C28, C29,C30 and C31

common mode HF coupling capacitors 1 nF/50 V 2 × SMD0805

C32 and C33 power supply decoupling capacitors 220 nF/63 V 2 × SMD1206

C34 and C35 power supply electrolytic capacitors 1500 µF/35 V 2 × Rubycon ZL very low ESR (largeswitching currents)

C36, C37,C38 and C39

analog supply decoupling capacitors 220 nF/63 V 4 × SMD1206

C40 and C41 analog supply electrolytic capacitors 47 µF/35 V 2 × Rubycon ZA low ESR

C43 diagnostic capacitor 180 pF/50 V SMD1206

C44 mode capacitor 220 nF/63 V SMD1206

D1 5.6 V Zener diode BZX79C5V6 DO-35

D2 7.5 V Zener diode BZX79C7V5 DO-35

R1 clock adjustment resistor 27 kΩ SMD1206

2002 Oct 22 19



TDA8927

R4, R5,R6 and R7

input resistors 10 kΩ 4 × SMD1206

R10 diagnostic resistor 1 kΩ SMD1206

R11, R12,R13 and R14

snubber resistors 5.6 Ω; >0.25 W 4 × SMD1206

R15 and R16 resonance suppression resistors 24 Ω 2 × SMD1206

R19 mode select resistor 39 kΩ SMD1206

R20 mute select resistor 39 kΩ SMD1206

R21 resistor needed when using anasymmetrical supply

10 kΩ SMD1206

R22 resistor needed when using anasymmetrical supply

9.1 kΩ SMD1206

R24 bias resistor for powering-up the powerstage

200 kΩ SMD1206

COMPONENT DESCRIPTION VALUE COMMENTS

2002 Oct 22 20



TDA8927

15.6 Curves measured in reference design

handbook, halfpage102

10

1

10−1

10−3

10−2

MLD627

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)

Fig.9 Total harmonic distortion plus noise as afunction of output power.

2 × 8 Ω SE; VP = ±25 V.

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD628

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)

Fig.10 Total harmonic distortion plus noise as afunction of input frequency.

2 × 8 Ω SE; VP = ±25 V.

(1) Po = 10 W.

(2) Po = 1 W.


10

1

10−1

10−3

10−2

MLD629

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)


2 × 4 Ω SE; VP = ±25 V.

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD630

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)

Fig.12 Total harmonic distortion plus as a functionof input frequency.

2 × 4 Ω SE; VP = ±25 V.

(1) Po = 10 W.

(2) Po = 1 W.

2002 Oct 22 21



TDA8927


10

1

10−1

10−3

10−2

MLD631

10−2 10−1 1Po (W)

THD+N(%)

10 102 103

(1)

(2)

(3)


1 × 8 Ω BTL; VP = ±25 V.

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

MLD632

10 102 103 104 105

102

10

1

10−1

10−3

10−2

fi (Hz)

THD+N(%)

(1)

(2)

Fig.14 Total harmonic distortion plus noise as afunction of input frequency.

1 × 8 Ω BTL; VP = ±25 V.

(1) Po = 10 W.

(2) Po = 1 W.

handbook, halfpage

0

25

5

10

15

20

MLD609

10−2 10−1 1

(2)

Po (W)

P(W)

10 102 103

(1)

(3)

Fig.15 Power dissipation as a function of outputpower.

VP = ±25 V; fi = 1 kHz.

(1) 2 × 4 Ω SE.

(2) 1 × 8 Ω BTL.

(3) 2 × 8 Ω SE.

handbook, halfpage

0

(3) (1)

(2)

150

100

0

20

40

60

80

30

η(%)

Po (W)60 90 120

MLD610

Fig.16 Efficiency as a function of output power.

VP = ±25 V; fi = 1 kHz.

(1) 2 × 4 Ω SE.

(2) 1 × 8 Ω BTL.

(3) 2 × 8 Ω SE.

2002 Oct 22 22



TDA8927

handbook, halfpage

10

(3)

(4)

(1)

(2)

35

200

0

40

80

120

160

15

Po(W)

VP (V)20 25 30

MGU893

Fig.17 Output power as a function of supplyvoltage.

THD + N = 0.5%; fi = 1 kHz.

(1) 1 × 4 Ω BTL.

(2) 1 × 8 Ω BTL.

(3) 2 × 4 Ω SE.

(4) 2 × 8 Ω SE.

handbook, halfpage

10

(3)

(4)

(1)

(2)

35

200

0

40

80

120

160

15

Po(W)

VP (V)20 25 30

MGU894

Fig.18 Output power as a function of supplyvoltage.

THD + N = 10%; fi = 1 kHz.

(1) 1 × 4 Ω BTL.

(2) 1 × 8 Ω BTL.

(3) 2 × 4 Ω SE.

(4) 2 × 8 Ω SE.

handbook, halfpage

−100

0

−80

−60

−40

−20

MLD613

10210fi (Hz)

αcs(dB)

103 104 105

(1)

(2)

Fig.19 Channel separation as a function of inputfrequency.

2 × 8 Ω SE; VP = ±25 V.

(1) Po = 10 W.

(2) Po = 1 W.

handbook, halfpage

−100

0

−80

−60

−40

−20

MLD614

10210fi (Hz)

αcs(dB)

103 104 105

(1)

(2)

Fig.20 Channel separation as a function of inputfrequency.

2 × 4 Ω SE; VP = ±25 V.

(1) Po = 10 W.

(2) Po = 1 W.

2002 Oct 22 23



TDA8927

handbook, halfpage

20

45

25

30

35

40

MLD615

10210fi (Hz)

G(dB)

103 104 105

(1)

(2)

(3)

Fig.21 Gain as a function of input frequency.

VP = ±25 V; Vi = 100 mV; Rs = 10 kΩ/Ci = 330 pF.

(1) 1 × 8 Ω BTL.

(2) 2 × 8 Ω SE.

(3) 2 × 4 Ω SE.

handbook, halfpage

20

45

25

30

35

40

MLD616

10210fi (Hz)

G(dB)

103 104 105

(1)

(2)

(3)

Fig.22 Gain as a function of input frequency.

VP = ±25 V; Vi = 100 mV; Rs = 0 Ω.

(1) 1 × 8 Ω BTL.

(2) 2 × 8 Ω SE.

(3) 2 × 4 Ω SE.

handbook, halfpage

−100

0

−80

−60

−40

−20

MLD617

10210fi (Hz)

SVRR(dB)

103 104 105

(1)

(2)

(3)

Fig.23 Supply voltage ripple rejection as a functionof input frequency.

VP = ±25 V; Vripple(p-p) = 2 V.

(1) Both supply lines in antiphase.

(2) Both supply lines in phase.

(3) One supply line rippled.

handbook, halfpage

0 5

0

−100

−80

−60

−40

−20

1

(1)

(3)

SVRR(dB)

Vripple(p-p) (V)2 3 4

MLD618

(2)

Fig.24 Supply voltage ripple rejection as a functionof ripple voltage (peak-to-peak value).

VP = ±25 V.

(1) fripple = 1 kHz.

(2) fripple = 100 Hz.

(3) fripple = 10 Hz.

2002 Oct 22 24



TDA8927

handbook, halfpage

0 10 20 30VP (V)

Iq(mA)

37.5

100

0

20

40

60

80

MLD619

Fig.25 Quiescent current as a function of supplyvoltage.

RL = open-circuit.

handbook, halfpage

0 10 20 30VP (V)

fclk(kHz)

40

380

340

348

356

364

372

MLD620

Fig.26 Clock frequency as a function of supplyvoltage.

RL = open-circuit.

handbook, halfpage

0

5

1

2

3

4

MLD621

10−110−2Po (W)

Vripple(V)

1 10 102

(1)

(2)

Fig.27 Supply voltage ripple as a function of outputpower.

VP = ±25 V; 1500 µF per supply line; fi = 10 Hz.

(1) 1 × 4 Ω SE.

(2) 1 × 8 Ω SE.

handbook, halfpage5

010 104

MLD622

102 103fi (Hz)

SVRR(%)

1

2

3

4

(1)

(2)

Fig.28 Supply voltage ripple rejection as a functionof input frequency.

VP = ±25 V; 1500 µF per supply line.

(1) Po = 30 W into 1 × 4 Ω SE.

(2) Po = 15 W into 1 × 8 Ω SE.

2002 Oct 22 25



TDA8927

handbook, halfpage

600100

(3)

fclk (kHz)

THD+N(%)

200 300 400 500

10

1

10−1

10−2

10−3

MLD623

(1)

(2)

Fig.29 Total harmonic distortion plus noise as afunction of clock frequency.

VP = ±25 V; Po = 1 W in 2 × 8 Ω.

(1) 10 kHz.

(2) 1 kHz.

(3) 100 Hz.

handbook, halfpage

100 600

50

0

10

20

30

40

200

Po(W)

fclk (kHz)300 400 500

MLD624

Fig.30 Output power as a function of clockfrequency.

VP = ±25 V; RL = 2 × 8 Ω; fi = 1 kHz; THD + N = 10%.

handbook, halfpage

100 600

150

0

30

60

90

120

200

Iq(mA)

fclk (kHz)300 400 500

MLD625

Fig.31 Quiescent current as a function of clockfrequency.

VP = ±25 V; RL = open-circuit.

handbook, halfpage

100 600

1000

0

200

400

600

800

200

Vr(PWM)(mV)

fclk (kHz)300 400 500

MLD626

Fig.32 PWM residual voltage as a function of clockfrequency.

VP = ±25 V; RL = 2 × 8 Ω.

2002 Oct 22 26



TDA8927

16 PACKAGE OUTLINES

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT243-1

0 5 10 mm

scale

D

L

E

A

c

A2

L3

Q

w Mbp

1

d

D

Z e

e

x h

1 17

j

Eh

non-concave

97-12-1699-12-17

DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1

view B: mounting base side

m 2e

v M

B

UNIT A e 1A2 bp c D(1) E(1) Z(1)d eDh L L3 m

mm 17.015.5

4.64.4

0.750.60

0.480.38

24.023.6

20.019.6

10 2.54

v

0.812.211.8

1.27

e 2

5.08 2.41.6

Eh

6 2.001.45

2.11.8

3.43.1 4.3

12.411.0

Qj

0.4

w

0.03

x

2002 Oct 22 27



TDA8927

17 SOLDERING

17.1 Introduction to soldering through-hole mountpackages

This text gives a brief insight to wave, dip and manualsoldering. A more in-depth account of soldering ICs can befound in our “Data Handbook IC26; Integrated CircuitPackages” (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting ofthrough-hole mount IC packages on a printed-circuitboard.

17.2 Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is260 °C; solder at this temperature must not be in contactwith the joints for more than 5 seconds.

The total contact time of successive solder waves must notexceed 5 seconds.

The device may be mounted up to the seating plane, butthe temperature of the plastic body must not exceed thespecified maximum storage temperature (Tstg(max)). If theprinted-circuit board has been pre-heated, forced coolingmay be necessary immediately after soldering to keep thetemperature within the permissible limit.

17.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of thepackage, either below the seating plane or not more than2 mm above it. If the temperature of the soldering iron bitis less than 300 °C it may remain in contact for up to10 seconds. If the bit temperature is between300 and 400 °C, contact may be up to 5 seconds.

17.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

PACKAGESOLDERING METHOD

DIPPING WAVE

DBS, DIP, HDIP, SDIP, SIL suitable suitable(1)

2002 Oct 22 28



TDA8927

18 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet waspublished. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVELDATA SHEET

STATUS(1)PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective specification for productdevelopment. Philips Semiconductors reserves the right to change thespecification in any manner without notice.

II Preliminary data Qualification This data sheet contains data from the preliminary specification.Supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to change the specification withoutnotice, in order to improve the design and supply the best possibleproduct.

III Product data Production This data sheet contains data from the product specification. PhilipsSemiconductors reserves the right to make changes at any time in orderto improve the design, manufacturing and supply. Relevant changes willbe communicated via a Customer Product/Process Change Notification(CPCN).

19 DEFINITIONS

Short-form specification The data in a short-formspecification is extracted from a full data sheet with thesame type number and title. For detailed information seethe relevant data sheet or data handbook.

Limiting values definition Limiting values given are inaccordance with the Absolute Maximum Rating System(IEC 60134). Stress above one or more of the limitingvalues may cause permanent damage to the device.These are stress ratings only and operation of the deviceat these or at any other conditions above those given in theCharacteristics sections of the specification is not implied.Exposure to limiting values for extended periods mayaffect device reliability.

Application information Applications that aredescribed herein for any of these products are forillustrative purposes only. Philips Semiconductors makeno representation or warranty that such applications will besuitable for the specified use without further testing ormodification.

20 DISCLAIMERS

Life support applications These products are notdesigned for use in life support appliances, devices, orsystems where malfunction of these products canreasonably be expected to result in personal injury. PhilipsSemiconductors customers using or selling these productsfor use in such applications do so at their own risk andagree to fully indemnify Philips Semiconductors for anydamages resulting from such application.

Right to make changes Philips Semiconductorsreserves the right to make changes in the products -including circuits, standard cells, and/or software -described or contained herein in order to improve designand/or performance. When the product is in full production(status ‘Production’), relevant changes will becommunicated via a Customer Product/Process ChangeNotification (CPCN). Philips Semiconductors assumes noresponsibility or liability for the use of any of theseproducts, conveys no licence or title under any patent,copyright, or mask work right to these products, andmakes no representations or warranties that theseproducts are free from patent, copyright, or mask workright infringement, unless otherwise specified.

2002 Oct 22 29



TDA8927

NOTES

2002 Oct 22 30



TDA8927

NOTES

2002 Oct 22 31



TDA8927

NOTES

© Koninklijke Philips Electronics N.V. 2002 SCA74All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com . Fax: +31 40 27 24825For sales offices addresses send e-mail to: [email protected] .

Printed in The Netherlands 753503/02/pp32 Date of release: 2002 Oct 22 Document order number: 9397 750 09592

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