teaching advanced test issues in digital electronics
DESCRIPTION
Teaching Advanced Test Issues in Digital Electronics. ITHET 6th Annual International Conference Juan Dolio, Dominican Republic, July 9, 2005. E.Orasson , J.Raik , R. Ubar T U Tallinn, E STONIA H.-D.Wuttke TU Ilmenau, GERMANY. Outline. Introduction: Test as Teaching Objective - PowerPoint PPT PresentationTRANSCRIPT
Technical University Tallinn, ESTONIA
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E.Orasson, J.Raik, R. UbarTU Tallinn, ESTONIA
H.-D.WuttkeTU Ilmenau, GERMANY
Teaching Advanced Test Issues in Digital Electronics
ITHET 6th Annual International Conference
Juan Dolio, Dominican Republic, July 9, 2005
Technical University Tallinn, ESTONIA
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Outline
• Introduction: Test as Teaching Objective• Complexity vs. quality• Living pictures for learning logic level test• Low-cost tools for training digital test issues• Laboratory works and research training• Conclusions
Technical University Tallinn, ESTONIA
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Test Issues and Engineering Education
• The importance of test (fault diagnosis) as a teaching objective is underestimated in traditional engineering education
• Test is taught usually as a subtopic in a design course• It is taught as an independent discipline only when it is a hobby horse
of the professor
Why?• Because Test is interpreted as a nonproductive issue (vs. design)
• The number of courses that should be taught at universities doubles in a decade (Tenhunen, EWME, Lausanne, April 2004)
Technical University Tallinn, ESTONIA
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Didactical Issues
• Fault Diagnosis is not only an Electronics Systems related issue
• It has an important didactive role for the engineering education in general:
• It is a method to learn how to ask right questions
• It develops the ability of analysing cause-effect relationships
• It is looking for answers to the questions like what is the reason of what happened
Logic world (digital systems) because of its inherent logical complexity could be the best objective for learning the concepts of diagnostic analysis for any technical systems in general
Technical University Tallinn, ESTONIA
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Introduction: Test Tools
Test
System
Fault dictionary
System model
Test generation
Fault simulation
Test result
Fault diagnosis
Go/No go Located defect
Test experiment
Test tools
(BIST)
Technical University Tallinn, ESTONIA
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Course Map for Teaching Test
Models Theory
Tools
Fault Modelling
Fault Simulation
Test Generation
Fault Diagnosis
DFTBIST
Test DesignD&TField:
Defect Level
High Level
System Modelling
High Level
Logic Level
Boolean Differential Analysis
BDD
DD
Technical University Tallinn, ESTONIA
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The Map of Research Topics
Specification Design System
Model
Faults
Structure, functions
Test Synthesis and AnalysisRe-design
“Defect-Oriented Hierarchical Test”
Diagnosis
Defects
Design for testability
Self-Test
Technical University Tallinn, ESTONIA
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Research Motivation in the Field of Test
The main question:
How to improve test quality at increasing complexities of today's systems?
Solutions:• The complexity problems are handled by moving the abstraction
levels from logic to higher functional or behavioral levels • To handle test quality in deep-submicron technologies, new fault
models and defect-oriented methods should be used
Confusing situation (deadlock):• High-level modelling reduces the accuracy (and quality of test) • Defect orientation increases the complexity
Technical University Tallinn, ESTONIA
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Defects and Complexity
Stuck-at-1Broken (change of the function)BridgingStuck-open New StateStuck-on (change of the function)
Short (change of the function)
Stuck-off (change of the function)
Stuck-at-0
SAF-model is not able to cover all the transistor level defects
How to model transistor defects ?
Technical University Tallinn, ESTONIA
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Component level
dy
Mapping of defects
Hierarchical Approach to Test Problems
x1
x2
x3
x4
x5
System level
Wd
dn dFFddxxFy ),,...,(** 1
Logic levelError
Defect
1*
d
yW d
{Wd} dy Fault model:
Hierarchical diagnostics
y*
Physical level
Technical University Tallinn, ESTONIA
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Teaching Tools
• A set of tools will be presented for exercising Digital Test related problems like – test generation – fault simulation– fault diagnosis– built-in self-test
• The tools and practical training are divided into three classes: – applets for preliminary learning of test topics on logic level– the tools for carrying out test related hands-on experiments
(and research) for more complex circuits designed by students themselves
Technical University Tallinn, ESTONIA
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Methodology of Using Tools
• A set of circuits as diagnostic objectives for the applets are predesigned and can be selected by the student
• The applets can be used – by the teacher during the lecture, – by students for self-learning purposes, independent on the time
and place, and again – by the teacher to give the tasks to students during exams
• The third group of tools for hands-on experiments support reseach related laboratory work.
Technical University Tallinn, ESTONIA
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Living pictures
View panel for displaying information
(data tables, waveforms)
Test vector insertion panel
View panel for design schematics
Technical University Tallinn, ESTONIA
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Fault Simulation
Activated paths for selected test pattern
Fault table
Selected test pattern
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Test Pattern Generation
Design panel:• Small boxes on lines
display internal signals
• The boxes are clickable during manual test vector generation and fault diagnosis
• In the test generation mode, the needed signal values for fault activation or fault propagation can be inserted at connections
Technical University Tallinn, ESTONIA
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Defect-Oriented Test Generation
Procedure:• Define the defect
(bridging fault) • Define the line
affected by defect • Sensitize the defect• Propagate the fault• Justify the values
assigned to the lines
y
x3
x2
x1
I3
I1
I0
&
&
I4
1
I5
1
I6
& I2
&
&
1
1
0
0
1
0 1
0
1
0
Technical University Tallinn, ESTONIA
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USER
DEFSIM U S B
SERVER
INTERNET
DEFSIMDefect Investigation Environment
USER USER
DEFSIMCooperation: Estonia, Germany, Poland
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Laboratory training by tools
• After theoretical investigation of the test topics described in the previous section, a laboratory work follows with more complex designs, where – available design software (schematic editor as minimum), and
– Turbo-Tester diagnostic software are used
• Traditional VLSI test generation and fault simulation software on workstations are both costly and unable to handle large numbers of students simultaneously in educational courses
• Low-cost systems for solving a large class of tasks from the dependability area - test synthesis and analysis, fault diagnosis, testability analysis, built-in self-test are missing
Technical University Tallinn, ESTONIA
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Laboratory training by tools
Diagnostic software Turbo-Tester
Test Generation
BIST Simulation
Methods:DeterministicRandomGenetic
Methods:BILBOCSTPStore/Generate
Design Test
Levels:GateMacro
Fault Simulation
Methods:Single faultParallelDeductive
Fault Table
Fault models:Stuck-at-faultsStuck-opensDelay faults
Test Optimization
Fault Diagnosis
Fault Location
Technical University Tallinn, ESTONIA
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Laboratory training by tools
An advanced training environment TURBO TESTER has been developed at Tallinn Technical University
It is installed on PCs for teaching undergraduate and graduate courses in design for testability and test of digital electronics
TT is an easy-to-learn, easy-to-set-up and low-cost CAD system
It has interfaces to commercially available design tools like: Cadence, Synopsys, Mentor Graphics, Viewlogic, Compass, OrCAD, Dixi-CAD
Technical University Tallinn, ESTONIA
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Research-Oriented Lab Work
• Built-in self-test (BIST)– BIST is the capability of a circuit to test itself
– Students concentrate themselves in a off-line BIST consisting of a test pattern generator, unit under test and a response analyzer
– There are several disadvantages of such a structure: • pseudorandom test sequences are usually very long
• they do not guarantee always a sufficient fault coverage because of the existence of “hard-to-test” faults
Test Pattern Generator
Unit Under Test
Response Analyser
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. . .
.
ROM. . . . . .
SoC
Core
Co
ntro
ller
Laboratory works
• Combining – on-line generated pseudo-
random patterns – with pre-generated and stored
test patterns
• Problems :
– To find the best characteristics for test generator (PRPG)
– To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time
Built-in self-test:
CORE UNDER TEST
Response Analyzer
Test Generator
Technical University Tallinn, ESTONIA
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Research training: Example
Fault Cover %
Creal_min
Cestimated_min
Predicted cost
Real cost
CTOTAL (Total cost of BIST)
Storedtest
lengthMS
Generatedtest
lengthTG
100%
• Graphical solution for finding the optimum of mixing pseudorandom and stored test approaches as the tradeoff between the memory cost and testing time
• Cost of the BIST:
CTOTAL = CTIME + CHW = TG + MS
• where
– CTIME is the cost related to time
– CHW is hardware cost related to BIST architecture,
– TG is the length of the test generated by hardware,
– MS is is the number of patterns to be stored
Technical University Tallinn, ESTONIA
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Conclusions
• A conception is presented for improving the skills of students to be educated for digital test related topics
• It is a combination of learning by
– internet based simple “living pictures”, and
– hands-on training with a set of commercial design tools, and low-cost university tools
• The tools are accessible
– Applets: http://www.pld.ttu.ee/testing/
– Low-cost test tools: http://www.pld.ttu.ee/tt/