team a: vme+1/[4-9] (me+1 far side)

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29 Jan. 2008 G. Rakness (UCLA) 1 Team A: VME+1/[4-9] (ME+1 far side) • Goal: Determine synchronization parameters good enough to take data • See https://cmsdaq.cern.ch/elog/CSC/ 3014 Team A: Nick Kypreos (Florida), Shih-Chuan Kao (UCR)

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Team A: VME+1/[4-9] (ME+1 far side). Goal: Determine synchronization parameters good enough to take data See https://cmsdaq.cern.ch/elog/CSC/3014. Team A: Nick Kypreos (Florida), Shih-Chuan Kao (UCR). Communication phase parameters measured for VME+1/[4-9]. - PowerPoint PPT Presentation

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Page 1: Team A: VME+1/[4-9] (ME+1 far side)

29 Jan. 2008 G. Rakness (UCLA) 1

Team A:VME+1/[4-9] (ME+1 far side)

• Goal: Determine synchronization parameters good enough to take data

• See https://cmsdaq.cern.ch/elog/CSC/3014

Team A: Nick Kypreos (Florida), Shih-Chuan Kao (UCR)

Page 2: Team A: VME+1/[4-9] (ME+1 far side)

29 Jan. 2008 G. Rakness (UCLA) 2

Communication phase parameters measured for VME+1/[4-9]

Values measured for ALCT TMB, CFEB TMB, and RAT TMB crate communication. All OK except:

• VMEp1_5…  • +1/2/14, slot 14 all CFEBs not OK  • +1/1/13, slot 4, ALCT tx/rx not OK

• VMEp1_6…  • +1/1/17, slot 6, CFEB0 not OK (likely cable)  • +1/2/15, slot 8, CFEB4 not OK (likely cable)

• VMEp1_7…  • +1/3/20, slot 20, ALCT tx/rx not OK, all CFEB not OK (suspect fuse)

• VMEp1_8…  • +1/2/21, slot 8, CFEB3 not OK (likely cable)

Need to run with TMB default configuration (empty userPROM) in order to perform CFEB rx delay scans…

Page 3: Team A: VME+1/[4-9] (ME+1 far side)

29 Jan. 2008 G. Rakness (UCLA) 3

Synchronization L1A delay values: Difference between measured values and predicted values...

chamber CFEB TMB   ALCT

-----------   ----    ---- ----+1/2/9      -1      -1    -3+1/2/10      0      -1    -3+1/2/11     +1     -1    -2+1/3/9      +1      -1    -2+1/3/10     +1      -1    -3+1/3/11      0      -1    -2+1/1/9       0      -1    -2

To expedite Local Run… Choose to use predicted values modified by…

• tmb_lct_cable_delay = tmb_lct_cable_delay_predicted

• tmb_l1a_delay = tmb_l1a_delay_predicted 1

• alct_l1a_delay = alct_l1a_delay 2

Page 4: Team A: VME+1/[4-9] (ME+1 far side)

29 Jan. 2008 G. Rakness (UCLA) 4

First look at TMB and DDU counters

• HV on with “radioactive trigger” – 1 layer ALCT*1 layer CLCT

• TMB counters– TMB and ALCT L1A delay parameters OK – Recall: 7bx wide windows…

• DDU counters – CFEB-L1A timing needs adjustment on several

chambers– DAV bits for CFEB and ALCT for many chambers– 52 LIVE INPUT CHANNELS TOTAL found on DDUs 

• 53 expected (+1/3/20 masked out…)

Expect ~morning to address timing issues, ready for Local Run tomorrow afternoon (?)