technical university tallinn, estonia overview: fault simulation overview about methods low (gate)...

Technical University Tallinn, ESTONIA

Overview: Fault Simulation

• Overview about methods • Low (gate) level methods• Parallel fault simulation• Deductive fault simulation

– Gate-level fault lists propagation (library based)– Boolean full differential based (general approach)– SSBDD based (tradeoff possibility)

• Concurrent fault simulation• Critical path tracing• Parallel critical path tracing• Hierarchical fault simulation


Faults in Digital Circuits

F1 F2 F3 F4 F5 F6 F7

T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1

Fault F5 located

Fault table

E1 E2 E3

0 0 10 1 00 1 01 0 11 0 10 0 0

Test experiment

Test generation

Fault simulationFault diagnosis

Fault modeling

Testing

How many rows and

columns should be

in the Fault

Table?


Fault simulation

Goals: • Evaluation (grading) of a test T (fault coverage)• Guiding the test generation process• Constructing fault tables (dictionaries)• Fault diagnosis

Generate initial T

Evaluate T

Sufficientfault coverage?

Modify T Done

YesNo

Select target fault

Generate test for target

Fault simulate

Discard detected faults

Done

No morefaults

Deterministic test generation

Random test generation


Fault simulation

Fault simulation techniques:• serial fault simulation• parallel fault simulation• deductive fault simulation• concurrent fault simulation• critical path analysis• parallel critical path analysis

Common concepts:• fault specification (fault collaps)• fault insertion• fault effect propagation• fault discarding (dropping)

Comparison of methods:

Fault table

Faults Fi

Test patterns Tj

Entry (i,j) = 1(0) if Fi is detectable (not detectable) by Tj


Single and Parallel Fault Simulation

Parallel patterns

Fault-free circuit:

Faulty circuit:

& 1x1

x2 x3

zy

0

1

0

0

0

& 1x1

x2 x3

zy

0

1

1

0

1

Inserted stuck-at-1

fault

Detected error

Fault-free circuit:

Faulty circuit:

& 1x1

x2 x3

zy

001

101

001

010

011

& 1x1

x2 x3

zy

001

101

111

010

111

Inserted stuck-at-1

fault

Detected error

Three test patterns

Single pattern


Critical Path Tracing

&

&

1

1

1

2

3

45 a

c

b1

1

0

00

0

0

11

y

1 2

3 4

5

y

Problems:&

&

11

11/0

y

&

&

10

11

y

1/0

1

1

1/0

1

1

The critical path is not continuous

The critical path breaks on the fan-out

Research in ATI© Raimund Ubar

Algorithm:1. Determine the activated path to find the fault candidates2. Analyze the detectability of the each candidate fault

(each node represents a subset of real faults)

Fault Analysis with SSBDDs

x11y x21

x12 x31 x4

x13x22 x32

0

1

0

1

7

&

&

&

1

&

x1

x2

x3x4

y

x11

x21

x12

x31

x13

x22x32

0

1

0 001

00


8

Properties of SSBDDs

Errordetected

Error signal traced

C...Where to continue tracing?

Property 2:If a test vector X

activates in SSBDD a 0-path (1-path) which travers a subset of nodes M, then only 0-nodes (1-nodes) have to be considered as fault candidates

Speeding-up simulation:M = {1,2,3,4,6,7} M* = {1,6,7} – by Property 2M** = {6,7} – by Property 1

Fault diagnosis and fault simulation can be speed-up by using Property 2

Only 6 and 7 have to be considered

Fault diagnosis / Fault simulation:

1

2 3

4

5

6 8 1

7

0

y

y


Parallel Critical Path Tracing

&

1

x1

y

0110321

xxx

y

1011

1110

10011011

Detected faults vector: - 10 -

T1: No faults detectedT2: x1 1 detectedT3: x1 0 detectedT4: No faults detected

x3

x2

Handling of fanout points: • Fault simulation• Boolean differential calculus

x y

xk

x2

x1

F

))(),...,(( 11 x

xx

x

xxFy

x

y kk


F4

F5

F3

F2

F1X1

y4

y5

X2

X5

z2

z3z1 X3

X4

z21

z22

z13

z31

z32

z11

z12

42

3131

2

212144

2

4 ))(),(,( yz

zz

z

zzxF

z

y


Problem with fan-out points:



Problem with sequentiality:

F1

R6

R1

R2

R7

X1

X2

X3

F2

F3

F4

R8

R4

R5

R3X4

F5

F7

F8

F6R10

X5

R9

Y2

Y1

Z1

Z2



Problem is solved:

F1 ... F8

Z1

MISR

R7,R8

X1 – X5 Y1, Y2

R1 ... R6

Two reasons why a fault can be propagated to the same component during different time frames:

• global feedback,

• fan-outs with re-convergence in different time frames

MISR can be connected to these “problem causing” test points

The fault will be captured at the first occasion. The detection of the fault will be fixed, and we can ignore its impact in the future


Overview: Fault Diagnosis

• Combinational methods of diagnosis– Fault table based methods– Fault Dictionary based methods– Minimization of diagnostic data in fault tables– Methods for improving the diagnostic resolution

• Sequential methods of diagnosis– Edge-Pin testing– Guided Probe fault location

• Fault diagnosis with Boolean Differentials• Physical Defect Diagnosis• Design error diagnosis


Combinational Fault diagnosis

F1 F2 F3 F4 F5 F6 F7

T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1

Fault F5 located

Faults F1 and F4 are not distinguishable

Fault localization by fault tables

No match, diagnosis not possible

E1 E2 E3

0 0 10 1 00 1 01 0 11 0 10 0 0


Combinational Fault Diagnosis

• Fault dictionaries contain the sama data as the fault tables with the difference that the data is reorganised

• The column bit vectors can be represented by ordered decimal codes or by some kind of compressed signature

Fault localization by fault dictionaries

No Bit vectors Decimal numbers Faults1 000001 01 F7

2 000110 06 F5

3 001011 11 F6

4 011000 24 F1, F4

5 100011 35 F3

6 101100 44 F2

Test results:E1 = 06, E1 = 24, E1 = 38

No match


Sequential Fault Diagnosis

Sequential fault diagnosis by Edge-Pin Testing

T1 F1,F4,F5,F6,F7

PT2

PF1,F4

F2, F3 T3P

F3

F

F

F2

F

F5,F6,F7 T3P

F5,F7

F

F6

T4P

F7

F

F5

F1,F2

F3,F4

F5,F6

F7

F1 F2 F3 F4 F5 F6 F7

T1 0 1 1 0 0 0 0T2 1 0 0 1 0 0 0T3 1 1 0 1 0 1 0T4 0 1 0 0 1 0 0T5 0 0 1 0 1 1 0T6 0 0 1 0 0 1 1

Diagnostic tree:

Two faults F1,F4 remain indistinguishable

Not all test patterns used in the fault table are needed

Different faults need for identifying test sequences with different lengths

The shortest test contains two patterns, the longest four patterns


Sequential Fault Diagnosis

Guided-probe testing at the gate level

x8

No faultsP

F

x6

P

F

x4

x5,2

P

F

OR- x8 is faulty

x2

P

F

x3,1 PF

NOR- x5 is faulty

x3

P

F

Line x3,1 is faulty

Line x3 is faultyLine x2 is faulty

Line x2

is faultyF

P

x3,2

P AND- x6 is faultyF x3

P

F

Line x3,2 is faulty

Line x3 is faulty

x2

x3

x4

x3,1

x3,2

x5,1x5,2

x5

x6

x7

x8

1

1

1

Searh tree:

Faulty circuit


Improving Diagnostic Resolution

Method:

• F1 may influence both outputs, F2 may influence only x8

• A test pattern 0010 activates F1 up to the both outputs, and F2 only to x8

• If both outputs will be wrong, F1 is present

• If only x8 will be wrong, F2 is present

Generating tests to distinguish faults

F1: x3,1 0

Faults are influencing on differentoutputs:

x2

x3

x4

x3,1

x3,2

x5

x6

x7

x8

1

1

&

1x1

0

0

1

0

F2: x4 1



Method:

• Both faults influence the same output of the circuit

• One of them should be blocked

Two possibilities:

• A test pattern 0100 activates the fault F2. F1 is not activated: the line x3,2 has the same value as it would have if F1 were present

• A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate


F1: x3,2 0 F2: x5,2 1

How to activate a fault without activating another one?

x5,1x5,2

x2

x3

x4

x3,1x3,2

x5

x6

x7

x8

1

1

&

1x1

0

1

0/1

0



Method:

• Both of the faults may influence only the same output

• Both of the faults are activated to the same OR gate, none of them is blocked

• However, the faults produce different values at the inputs of the gate, they are distinguished

if x8 = 0, F1 is present

otherwise, if x8 = 1 (OK value)

• either F2 is present

• or none of the faults are present


F1: x3,1 1

How to activate a fault without activating another one?

x5,1x5,2

x2

x3

x4

x3,1x3,2

x5

x6

x7

x8

1

1&

1x1

1

0

0

1

F2: x3,2 1


21

Boolean Differentials and Fault Diagnosis

dx - fault variable, dx (0,1)

dx = 1, if the value of x has changed because of a fault

Partial Boolean differential (for fault simulation):

Full Boolean differential (for fault diagnosis):

ii

niinix dxx

FxdxxxFxxxFFd

i

),...,,...,(),...,,...,( 11

)()(

),...,...,(),...,...,( 111

dXXFXFdF

dxxdxxdxxFxxxFdF nniini



&

1

&

x1

x2

x3

&1

1

1

0

1

10

y

)( 321 xxxy

x1 = 0x2 = 1x3 = 1dy = 0

))())((( 332211 dxxdxxdxxydy

Diagnostic experiment:

Test pattern

- Correct reaction

1)(13

12

01 dxdxdx

Adjusting for SAF faults:

0)(1 321 dxdxdxdySubstitution of values:

1)( 321 dxdxdxdy

101 dxPartial diagnosis:

22



&

1

&

x1

x2

x3

&1

1

1

0

1

10

y

)( 321 xxxy

x1 = 0x2 = 1x3 = 1dy = 0

))())((( 332211 dxxdxxdxxydy 1) Correct output signal:

1)(13

12

01 dxdxdx 1

01 dx

2) Erroneous output signal:

1)(1 321 dxdxdxdy

103

02

01 dxdxdx&

1

&

x1

x2

x3

&1 0

1

1

0

0

0

1 y

x1 = 0x2 = 0x3 = 0dy = 1

Two diagnostic experiments:

1))((03

02

01

13

12

01 dxdxdxdxdxdx

Diagnosis from two experiments:

23



= 0Final diagnosis:

113

03

02

01 dxdxdxdx

The line x3 works correctlyThere is a fault:

The fault is missing

12 x11 x

Rule: 010 kk dxdx

1))((03

02

01

13

12

01 dxdxdxdxdxdx

Diagnosis from two experiments:

1)(13

03

02

03

02

12

01 dxdxdxdxdxdxdx

24

Rule: 000kk dxdx

technical university tallinn, estonia overview: fault simulation overview about methods low (gate)...

Documents

fault simulationoverview

fault candidatesanalyze

fault simulation overview

test t fault coverageguiding

activated path

continuousthe critical

test vector x

faulty circuit