technion - israel institute of technology department of electrical engineering
DESCRIPTION
Technion - Israel institute of technology department of Electrical Engineering. 40Gbit Signal Generator for Ethernet. Characterization presentation. Developers : Ben-Elazar Doron and Atila Fuad Mentor : Dr. Bar-On David. Nov 16, 2010. High speed digital systems laboratory. - PowerPoint PPT PresentationTRANSCRIPT
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Technion - Israel institute of technologydepartment of Electrical Engineering
High speed digital systems laboratory
40Gbit Signal Generator for Ethernet
Characterization presentation
Developers : Ben-Elazar Doron and Atila FuadMentor : Dr. Bar-On David
Nov 16, 2010
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40Gbit SG Agenda
Background
Project Objectives
System Block Diagram
FPGA Block Diagram
Technical Specifications
Risks
Gantt Chart
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40Gbit SGBackground
• Debugging a modern communication chip requires the ability to generate high speed L1 & L2 Ethernet signals on all ports of the chip.
• High speed Ethernet signals (41.25 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.
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40Gbit SGProject Objectives
The Target is to generate 40Gbps Ethernet channelSplit into two semesters:
Project A – Winter Sem. 2010/11:• 10Gbps Traffic.• generate hard coded patterns.
Project B – Spring Sem. 2011:• Continuation of Project A.• Generating 40Gbps Traffic.• GUI Software for Frame Stream Definition.
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40Gbit SGSystem Block Diagram
10Gbps Signal Generator
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40Gbit SGSystem Block Diagram
Final 40Gps Signal Generator
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40Gbit SGFPGA Block Diagram
System Controller
FSM
CLOCK
Frame Data Creator
CRC
Command Unit
Header Machine
Destination Address
Source Address
Type/Length
PC
S
PM
A
SER
DES
Frame Delay
OUT
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40Gbit SGTechnical Specifications
• Software Tools:• Quartus Design Tool• Altera USB Programming Tool• The Mega Core Functions (PHY+PCS+PMA)
• Hardware: • Altera Stratix IV with 10Gbps Ser-Des• Board with SFP+ Modules 10Gbps• Link Partner – IXIA• PC• Fiber Optic Cable
• Hardware Programming Language: VERILOG• Output: Valid 802.3 Ethernet Packets Transmitted by 64b/66b
coding protocol
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40Gbit SGRisks
• Board not arriving on time – We ordered the board 2 months ahead.
• Defective modules – Ordering two boards.• Knowledge gap – Mini project with Altera.
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40Gbit SGGantt Chart
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40Gbit SGGantt Chart – In Depth