technische universität münchen we create tools for chips institute for electronic design...

Technische Universität MünchenTechnische Universität München

We create tools for chips

Institute forElectronic Design Automation

U. Schlichtmann

ISPD 2015 - March 31, 2015

Beyond GORDIAN and KRAFTWERK:EDA Research at TUM

Technische Universität München

Overview

The early years

Plantage: Analog Placement

PROTON: ONoC Physical Design

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Topics covered by Prof. Antreich

• Since 1975: CAD for analog circuits• Early 1980s: Physical Design• Mid-1980s: ATPG• Late-1980s: Digital Simulation (Parallelization)• 1990s: Logic and RTL synthesis (FPGAs)• 1990s: Formal Techniques


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Topics covered by Prof. Antreich

• Since 1975: CAD for analog circuits• Early 1980s: Physical Design• Mid-1980s: ATPG• Late-1980s: Digital Simulation (Parallelization)• 1990s: Logic and RTL synthesis (FPGAs)• 1990s: Formal Techniques

Technische Universität MünchenInstitute forElectronic Design Automation

Can you simulate what you want to design?

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Circuit simulation

Simulation:

Performances f

Parameters x

Mathematical View

Physical View

Abstraction from the physical level


Statistical Parameter Distribution

• Normal distribution of with– mean vector– covariance matrix

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Operating Range, Performance Specification

• Operating range– Bounds for environmental

parameters

– Simulator input

• Performance specification– Bounds for performances – Simulator output

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Realistic Worst-Case Analysis

• Linear performance model with gradient for each performance

• Parameter tolerance ellipsoid

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Relate Yield and Tolerance Region: Worst-Case Distance W

W -1 0 1 2 3 4

Y´ 15.9%

50% 84.1% 97.7%

99.9% 99.99%

sigma design

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Example – Yield (Worst-Case) Analysis

NominalvaluePerformance

82.9%Overall yield

1.1(„“)/86.4%

2.6 ≤ 3.5DC power [mW]6.3(„“)/99.9%

67 ≥ 32Slew rate [V/s]1.8(„“)/96.9%

68 ≥ 60Phase margin[º]

7.7(„“)/99.9%

67 ≥ 30Transit frequency [MHz]

2.5(„“)/99.4%

76 ≥ 65Gain[dB]

Worst-casedistance/yield

Specifi-cation

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Worst-case distance

Yieldpartition

50.00%

97.70%

99.99%

Example – Yield (Worst-Case) Analysis

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Example – Optimized Yield

0

1

2

3

4

5

6

7

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Initial Optimized

Gain Transit frequency Phase marginSlew rate DC power

50.00%

97.70%

99.99%

Worst-case distance

Yieldpartition

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Empowering Innovation

© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com

MunEDA Corporate Overview

Vision & Mission: Empowering Innovation

EDA Software Vendor – Design Tool Suite WiCkeDTM for IP Migration, Analysis, Modeling & Sizing of Nanometer IC designs

Founded in 2001 - Headquarters in Munich Germany

Worldwide Sales & Support Offices in USA, Korea, China, Taiwan, Japan, UK, Ireland, Scandinavia, South America

Worldwide Customer Base of Semiconductor IDMs, Fabless Design Houses & Foundries

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Empowering Innovation

© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com

MunEDA Worldwide Customers & Foundry Partners (Selection)

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and more…for WiCkeDTM customer references see http://www.muneda.com/Customers


The Early Years


Overview


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Analog Design Flow

Specification

Topology

Sizing

Placement

Routing

Layout

Sizing rules

Placement rules

Routing rules

Process variationsParasitics etc.

manual

mostlyautomated

mostlymanual


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Modeling: inter-set relations

Placement rules

close proximity

A B

C D

E

symmetry

A B C E

alignment

BA

C

E

minimum distance

A1 B2 A3 B4

B1 A2 B3 A4

commoncentroid

variant constraints

R1

R2

R3

R4

R5

R6

Modeling: linear (in-)equalities


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State-of-the-Art

• Two classes of algorithms:– Absolute coordinates

• [Jepsen/Gellat, ICCD‘83]• [Kohn/Garrod/Rutenbar, IEEE Journal SC‘91]

– Topological relations• Sequence Pair [Murata/Fujiyoshi, TCAD‘96],

[Tam/Young/Chu, ICCAD‘06]• BSG [Nakatake/Fujiyoshi, ICCAD‘96]• B*-Tree [Chang/Chang, DAC‘00], [Balasa, TCAD‘04],

[Lin/Lin, DAC‘07], [Lin, DAC‘08]

• Optimization using Simulated Annealing


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CM

DS

CM

DP

Hierarchically Bounded Enumeration

• Hierarchical structure of analog circuits

• Automatic structure recognition [Gräb, Zizala, Eckmüller, Antreich ICCAD‘01]

[Massier, Gräb, Schlichtmann DATE‘08]

M5 M6 M7

CM

M1 M2

DP

M3 M4

CMM1 M2

M5 M6 M7

M3 M4

M8

CDS

CORE

OPA

M8 C

CM: Current Mirror

DP: Differential Pair

DS: Differential Stage


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Enumeration of placements of fundamental module sets

Hierarchically Bounded Enumeration

M5 M6 M7

CM

M1 M2

DP

M3 M4

CM

DS

CORE

OPA

M8 C

Fundamental

module sets

M5 M6 M7

M5

M6

M7M5

M6M7

…

M3 M4

M3

M4M3

M4

…

M8 C

M8

C

M8

C

…

M1a

M2a

M2b

M1b

…

M2

aM

1a

M1

bM

2b

M5 M6 M7

CM

M1 M2

DP

M3 M4

CM

DS

CORE

OPA

M8 C


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Overview

M5 M6 M7

CM

M1 M2

DP

M3 M4

CM

DS

CORE

OPA

M8 C

M5 M6 M7

M5

M6

M7M5

M6M7

…

M3 M4

M3

M4M3

M4

…

M8 C

M8

C

M8

C

…

M1a

M2a

M2b

M1b

…

M2

aM

1a

M1

bM

2b

• Hierarchical approach• Enhanced shape functions• New algorithm for placement:

B*-Tree CG LP• New addition of shapes

by addition of B*-Trees

CM

DS

CM

DP M1 M2

M5 M6 M7

M3 M4

M8

C

Enhanced Shape Functions

Enhanced Shape Addition


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Results

• OTA with folded cascode

#10

12 shapes in 44 sWSCM: Wide Swing Cascode current MirrorDP: Differential Pair

DP

WSCM #3optimum

area

#8

DP

WSCM


Industrial Example: wls_input_stage

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(a)

(c)

(b) (a)

(b) (c)


The Early Years


Overview


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The Architecture

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TSV

TSV

TSV

TSV

M1

2

3

4

λ1

λ2

λ3

λ4

Array of off-chip CW lasers

Electronic layer

Photonic layer

Off-chip memory

Clusters of processors

M2

M3M

4H4

H3

H2

H11


The Photonic Layer

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M1M1

Photonic layer

M2M2

M3M3

M4M4

H4

H3

H2

H1

M2M2 H3

• A path connects two Hubs or a Hub and a Memory Controller via Photonic Switching Elements (PSEs) and waveguides

Memory Controller PSE PSE Hub

λi λj


Example: Logic Scheme of Optical Layer

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Example: 8x8 λ-Router [Scandurra NoCArc’08]

λ1

I1 O1

O2

Wavelength λ1 is redirectedWavelength λn crosses

λ4

I2


Logic Scheme vs. Physical Design

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H1

H2

H3

H4

M1

M2 M4

M3

Logic Scheme Manually created layout

Creating layout manually is time consuming, error prone and suboptimal

PROTON: The first automatic place & route tool for 3D optical NoCs

[Ramini NOCS’12]


Placement and Routing Problem

• Minimize maximum insertion loss over all paths, e.g. minimize– Waveguide length– Number of crossings between

waveguides– Number of bends

• Constraints:– Place all PSEs and waveguides

inside chip area– No overlap

Netlist, chip area, positions of hubs and memory controllers

Valid and optimal layout

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Placement and Routing Algorithm

RoutingRouting

• Approximate waveguide length of each path by using a quadratic net model

• Approximate number of crossings

• Solve non-linear optimization problem

• Route waveguides by allowing but penalizing crossings

• E.g. Maze Router

PlacementPlacement

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Approximation of Crossings

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Module r

Module s

Module i

Module j

• Approximated number of crossings is calculated with the weights of Simpson’s rule


Solving the Optimization Problem

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• Find positions of all PSEs

• Constraints– Place all PSEs inside chip area– No overlap between optical devices (PSEs, hubs, memory

controllers)

• Nonlinear Optimization Problem solver: IPOPT (Interior point method)


Manual Layout vs. PROTON

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Contributions & Acknowledgements

Anja von Beuningen Helmut Graeb Martin Strasser Michael Eick Frank Johannes

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TUM. Technische Universität München

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technische universität münchen we create tools for chips institute for electronic design...

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