technology roadmap 2006 -...
TRANSCRIPT
© 2006 ASM
Technology Roadmap 2006Technology Driven Market Share Development
Ivo RaaijmakersCTO Front-end Operations and Director of R&D
Semicon, San Francisco, July 12, 2006
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 2
ASMI: Achievements and Activities Today
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 3
Improved Market Share 2001-2005Established Products: VLSI Research
www.vlsiresearch.com, accessed June 2006
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IC Depositionand Related
Tools
TraditionalVerticalFurnace
SiliconEpitaxial Film
Tools
PlatformBased PECVD
Tools
Rel
ativ
e M
arke
t Sha
re (%
)
2001 Share (=100 %)2005 Share (%)
Low-k Related
All PECVD
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 4
Improved Market Share 2004-2005Established Products: Morgan Stanley
Front-End IC Equipment
LPCVDPECVDSiGeSi RTP
FEOL BEOL
Epitaxy CVD
ASM +11.3% +10.1% not listed +1.0% +3.0%C1 -13.8% -8.5% -10.4% -1.9% -18.3%C2 +0.2% +13.5%C3 +2.5% +5.6%
+6.9% +0.9%
After: Semiconductor Capital Equipment Industry ViewMorgan Stanley Research, June 5, 2006
Market Leader
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 5
Early Engagement with Industry Leaders to help enable key Roadmap Transitions
ASMI Front-end Products Jun 06First Year for Production 2003 2004 2005 2006 2007 2008 2009 2010 >2011DRAM Half Pitch (nm) 90 65 45 32 <32Starting Materials Planar MOS on Bulk, Epi on Bulk, (PD) SOI
UTB FD SOIsSOI; FinFET/Trigate
Gatestacks SiON/Poly High-k/Metal or Silicide Gate
High-k Stacked Gate for NVMMobility Scaling PMOS RSD, CESL
NMOS RSDCharge Storage SiON MIS Capacitor
High-k/HAR MIM CapacitorUltra High-k/HAR MIM Cap.
Interconnect Cu/Low-kPorous Low-k
3D Integration
Strain, Low-kNew Materials, Processes
3rd Dimension
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 6
Process Technology and Product Platform Unique Production Solutions
• Presentation today is structured along the process technology dimension
• Process technology and product platform combine into unique solutions for each application and end-user environment
Polygon, Epsilon, Levitor, Eagle, and Dragon are registered ASM owned trademarks. A400, A412, PEALD and ALCVD are our trademarks
ALCVD LPCVD Epitaxy Thermal PECVD (Incl. (PE)ALD) RTCVD Process (Incl. Low-k)
A400/412
Levitor
Epsilon
Polygon
Eagle/Dragon
Prod
uct P
latfo
rm
Process Technology
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 7
ALCVD:Main Applications for Logic and Memory
Released1. DRAM node d/m2. High-k gate d/m3. RF caps d/m4. (H2 barriers)5. …
Developmenta. STI fillb. (Stacked gate)c. Copper barrier and
seedd. …
1
12
3
a
c
ALCVD is a trademark owned by ASM International (application): not indicated in pictures
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)Contains ASM Proprietary Information 8
ALD: HfO2 for MPU’sProduction Released
• HfCl4 + H2O process PDC, typical thickness as used in high performance gatestacks
• With Pulsar® ALD reactor similar results achievable for all chloride/water based thermal ALD processes (e.g. ZrO, TiOand HfZrO, HfSiO, Hf ZrSiO mixed oxides)
For presenta
00
Film
Thi
ckne
ss
0
5
10
15 Uniform
ity 1 sigma (%
)
1000 wafers 2000 wafers
~ one Hf atom
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)Contains ASM Proprietary Information 9
PEALD™: RF/AMS TechnologiesPEALD Ta2O5 Customer Results
• Low temperature process (<300 °C)
• PEALD much better material than MOCVD• Lower porosity and
higher density• ~10x lower leakage
XRR data from E. Deloffre, ST, ECS conference 2005
Ta2O5
TiN
TiN
XRR
MOCVD less than 85% dense!!
At a Capacitance Density of 4.8 fF/um2
1.0E-10
1.0E-09
1.0E-08
MOCVD PEALD
Leak
age
Curr
ent (
A)
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 10
ALCVD™: Batch and Single Wafer (PE)ALD
ASM’s ALCVD Process Technology Platform
Single Wafer(PE)ALD
Batch ALD
Single Wafer (PE)ALD
Research Development Volume ProductionWhen cost is most important(e.g. memory)
When TAT or Time to develop process is most important(e.g. foundry, SoC), or when special process requirements play a role
Chemistry, Fluid Dynamics, Surface Physics,…ALCVD and PEALD are trademarks owned by ASM International
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 11
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0 100 200 300Thickness (A)
Thro
ughp
ut (W
afer
s/hr
)
ALCVD™: Batch ALD of Al2O3 and HfO2
• No liner, boat rotation
• Separate multiholeinjectors
• 150 wafer maximum load size
1540Throughput (wfrs/hr@100 Å)
<1.5<1.0RtR (1σ, %)<1.5<1.0WtW (1σ, %)<3.0<1.5WiW (1σ, %)HfO2Al2O3
Al2O3 (TMA+O3)HfO2 (TEMAH+O3)
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 12
ALCVD™: Batch ALD(*) of TiN
• Higher throughput than single wafer LPCVD process (1.6 x)
• Low deposition temperatures (500 C POR, but < 450 C shown feasible)
• Qualified for DRAM capacitor electrodes
• Flexible load size from 5 to 150 wafers
(*) This process is not a “pure” ALD process, it has a significant CVD component
WtWWiW
<0.4
<0.5<0.5
WiW Uniformity, 1σ (%)
<0.4
<0.5<0.6
243.025
249.915256.15
Thickness [Å]Load
0
1
2
3
4
Rel.Throughput(Batch = 1)
Oxygen Content(AES, at. %)
Chlorine Content(AES, at. %)
N/Ti Atomic Ratio
ASM Batch "ALD" @ 500C Competitor Single Wafer LPCVD @650 C
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 13
LPCVD: Main Applications for Logic and Memory
Released1. Pad oxide/nitride2. Poly gate3. (NVM stacked gate)4. Spacer5. SAC6. DRAM capacitor
(poly, HSG,…) 7. BPSG, TEOS ILD’s8. …
Developmenta. SOI Box TEOSb. Nitride CESLc. …2
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7
ab
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(application): not indicated in pictures
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 14
LPCVD:ASM’s Silcore® Chemistry
• Patented chemistry, first introduced in 2002
• Commercialized with Voltaix as preferred supplier
• Many applications• RF/AMS HBT’s• SiGe poly gates• Stacked gates for NVM• Quantum dot NVM• Strain engineering• …
• Batch and single wafer LPCVD systems
Front-end Operations
Copyright © ASM International n.v., June 06 - 28 - IJRASM
®
New Technology™
Enabling Silcore™ Chemistry and Hardware
100 1000
100
1000
10000
500°C; 760 torr
550°C; 120 torr
650°C; 16 torr
Depo
sitio
n R
ate
[A/m
in]
Silcore massflow [mg/min]
a-Si, up to35000 A/minute
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 15
LPCVD: A412 Silcore® Doped SiliconNVM Floating Gate Application
• Deposition of Si and SiGeat very low temperatures• POR at 450 C• Ultra smooth films: < 2 Å
RMS on 450 Å P doped a-Si (for comparison: P doped SiH4 based: >5 Å)
• High dopant incorporation at low temperatures
• Low temperature a-Si enables additional applications for process steps after NiSi
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PH3 Flow (sccm)
Dep
osito
n R
ate
(A/m
in)
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In-F
ilm P
Con
cent
ratio
n (1
0^20
/cm
3)
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 16
Epitaxy:Main Applications for Logic and Memory
Released1. CMOS base epi2. SRB, sSOI3. RSD PMOS strain4. Elevated S/D5. DRAM plug fill6. (Bipolar)
Developmenta. RSD NMOS strainb. (GeOI)c. …
2143 a
5
(application): not indicated in pictures
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)Contains ASM Proprietary Information 17
Epitaxy: Mobility Scaling and Effects on Strain
• Mobility scaling increases Id,sat while not increasing dynamic power dissipation
• Parameters that affect strain and mobility:1. Recess depth2. Ge concentration for PMOS
(C for NMOS)3. Under etch, over fill, … 10-10
10-9
10-8
10-7
10-6
10-5
10-4
200 300 400 500 600 700
SiGe S/DReferenceI O
FF[A
/µm
] @ V
GS=0
.2V
ION
[µΑ/µm] @ VGS
=-0.8V
25%
1
Intel, IEDM 2003
2
22
,VC
LWI isatd µ=
2VfCP ii =
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 18
SiGe:B SiGe:B SiC:As SiC:As
Epitaxy: Mobility Scaling Paths towards 32 nm for NMOS and PMOS
Biaxial (e.g. sSOI or sSi/SiGe)
Uni-axial (e.g. recessed S/D
and/or CESL)
sSi sSi
PMOS NMOS
Ge: 20 40 % C: 0 1 3 %Increase stress/thickness CESL
Increase strain to eqv. 40% Ge
Hetero Orientation (HOT)
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 19
Epitaxy: Increasing Ge Content for PMOS Strain Enhancements
20% Ge740 °Ctc = 130 nm
30% Ge700 °Ctc = 122 nm
40% Ge650 °Ctc = 64 nm
No defects in epi layer, no relaxation, acceptable deposition rates
34 nm/min
27 nm/min
9 nm/min
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 20
Epitaxy: Si:C Development for NMOS
• Selective SiH4/MMS chemistry: max. substitutional C incorporation decreases with increasing T/growth rate
• Non-selective ASM chemistry: very high substitutional C, almost independent of temperature
• Selective process or selective etch in development
Bubble size corresponds to substitutional C (XRD).1% C is equivalent to strain of about 10% Ge, but of opposite sign
SiH4/MMS data from Loup et al., JVST B21.
IN DEVELOPMENT2.5%
3.0%
2.5%
1.4%
0.5%
0.1
1
10
100
1.1 1.15 1.2 1.25 1.3 1.35
1000/T (1/K)
Gro
wth
Rat
e (n
m/m
in.) ASM Chemistry
SiH4/MMS
500 C600 C 550 C
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 1
(Rapid) Thermal Process: Main Applications for Logic and Memory
Released1. (Wafer mfg anneals)2. (Well formation)3. STI formation4. Gate oxidation5. Sidewall oxidation6. Junction formation7. Silicide formation8. BPSG reflow anneal9. Cu, SOG anneal10. (Final alloy)11. …
Developmenta. (RTO)b. …
3 4 5 6
4
98
7
6
(application): not indicated in pictures
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 2
down time caused byscheduled
retrofit
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Mfg
Ava
il %
RTP: Levitor® High Uptime and Production Worthiness proven
• Random mix of four different processes, average 10,000 waferpasses per week
• (T = 850 - 1060°C, t = 20-30s: BPSG and isd Poly)
Down time causedby scheduled retrofit
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 3
RTP: Levitor® shows more Uniform Transistors with Conductive Heating
Dual-Core Opteron• 90nm technology• 194 mm2, SOI• 205 million transistors
Sheet Resistance (a.u.)
Overlap Capacitance (a.u.)
Sheet Resistance (a.u.)
Overlap Capacitance (a.u.)After Th. Feudel, AMD, presented at Semicon
Europe, Munich, April 2005; www.semi.org (2005).
Levitor = Conductive Heating
Conventional =Radiative Heating
Substantial differences in light absorption (ε) exist within die or wafer!
)(εf=
)(εf≠
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 4
RTP: Problems with Radiant Heating RTA-Driven Intra-Die Variations
I. Ahsan, et. al., IBM, VLSI 2006
Reference:Fastest Location
Slowest Location
Large Speed Variations on a
single Die
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM/IMEC Proprietary Information 5
RTP: Levitor® is the Best Tool for FUSI Dual Work Function Control
NMOS PMOS
Resist
Ni
Ni-rich
NiSi
CMP-based FUSI flow after etch-back
pMOS poly-Sietch-back
Ni deposition
2-step RTP-1 & selective etch
2-step RTP-2
A. Lauwers et al., IEDM 2005T. Hoffmann et al., VLSI Symposium 2006
Temperature budget is critical to control conversion of Ni
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM/IMEC Proprietary Information 6
A. Veloso et al., VLSI 2006
RTP: 45 nm Dual Work Function NiSirequires Near-Perfect Temperature Control
• Conductive heat transport provides control at low temperatures
• Process window narrows for smaller feature sizes
• Levitor: 370 C: +/- 0.5 C, good until at least 32 nm technology
(Protective cap )(Protective cap )
-100 -50 0 50 100
-100
-50
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20
20.1
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20.6
20.7
0.4 degrees
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 7
PECVD: Main Applications for Logic and Memory
Released1. TEOS/SiH4 ILD and
IMD2. Low-k/ULK ILD’s3. Low-k/ULK diel.
barriers4. SiON passivation5. NCP hardmask
Developmenta. Low-k gap fillb. (a-NCP hardmask)c. (ELK ILD)
3
45
21
(application): not indicated in pictures
1
1
5
55
555
a
a
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 8
PECVD: Low-k Dielectric Roadmap for Effective k - values
1.00
1.50
2.00
2.50
3.00
3.50
4.00
1999
2001
2003
2005
2007
2009
2011
2013
2015
2017
2019
2021
Year Production Start
Effe
ctiv
e k-
Valu
e
ITRS 1999ITRS 2001ITRS 2003ITRS 2005Customer HVM Qual'dDev. at CustomerResearch
• Colored data points are customer HVM materials, or planned HVM starts
1.00
1.50
2.00
2.50
3.00
3.50
4.00
1999
2001
2003
2005
2007
2009
2011
2013
2015
2017
2019
2021
Year Production Start
Effe
ctiv
e k-
Valu
e
ITRS 1999ITRS 2001ITRS 2003ITRS 2005ASM HVM Tool Availability
• Open data points are ASM HVM tool readiness
• ITRS is still very optimistic for 2011 and beyond
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 9
PECVD: Aurora® Low-k Market Position in 2005 Top 10 IC Makers
• Aurora is gaining market share in the top 10
0123456789
10
Production Production Qualification Development
90 nm 65 nm 45 nm 32 nm
Technology Node
Posi
tion
in IC
Mak
er T
op 1
0Selected Aurora Evaluating AuroraNo Aurora Engagement Today
Source: ASM
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)Contains ASM Proprietary Information 10
PECVD: Approaches to Lower Integrated Effective k Value
2.96Effective k
3.73.7Hardmask
2.802.75Main Low-k3.73.7Barrier
ProcessedVirgin
Porous Low-k and conventional barrier
Dense Low-k and Lower-k barrier
3.14Effective k
5.05.0Hardmask
2.752.50Main Low-k
5.05.0BarrierProcessedVirgin
25 nm
25 nm
235 nm
70 nm L/S
….likely needs UV Cure,
Pore Sealing and Glue Layer
ASM Low-k Barrier and DPL
the Low Cost Approach
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 11
PECVD: Advanced Patterning with Nano-Carbon Polymer (NCP™) Hard-Mask
Roadmap:• Increasing aspect ratio of mask
needed• Increasing number of
applications• More 3D structures, HAR• Smaller feature sizes
Process Flow• NCP/ARC deposition• Resist coat and develop• Etch NCP hardmask• Etch Oxide• Strip remaining resist
and hardmask
J.M.Park, IEDM 2002
SiO2
NCP (300nm)
193 nm ARC
Resist (200nm)
ResistThickness (nm)
Hard MaskThickness (nm)
500
10001500
2000
Device NodeProduction
Year
LithographyProcessComparison
LithographyTechnology
0.14 0.12 0.09 0.07 0.05 0.03
2001 2003 2005 2007 2009
Single Layer ResistBi Layer Resist
Hard Mask Resist (Carbon Film)
KrF 248nm ArF 193nm F2 or EPL, EUVL
100200
300400
500 2500
ResistThickness (nm)
Hard MaskThickness (nm)
500
10001500
2000
Device NodeProduction
Year
LithographyProcessComparison
LithographyTechnology
0.14 0.12 0.09 0.07 0.05 0.03
2001 2003 2005 2007 2009
Single Layer ResistBi Layer Resist
Hard Mask Resist (Carbon Film)
KrF 248nm ArF 193nm F2 or EPL, EUVL
100200
300400
500 2500
Soft Rigid
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 12
PECVD: Advanced Patterning with Nano-Carbon Polymer (NCP™) Hard Mask
1
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5
Competitor A1ASM NCPexDeposition
Temperature
Hydrogen Content
Elastic Modulus
Etch Selectivity
Absorption@ 633 nm
2005
1
2
34
5
ASM NCPexCompetitor A2
DepositionTemperature
Hydrogen Content
Elastic Modulus
Etch Selectivity
Absorption@ 633 nm
2006
1
2
34
5
Competitor A2ASM a-NCP
DepositionTemperature
Hydrogen Content
Elastic Modulus
Etch Selectivity
Absorption@ 633 nm
2006
• Patented ASM plasma polymerization technology
• Rapid continuous improvement needed to meet tightening criteria and beat competition
N
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 13
Longer Term Trends: the Move to 3Dfor 32 – 22 nm Technology
• Front-end of line• Finfet/Trigate in MPU and memory• Extreme high aspect ratio charge storage nodes
• Back-end of line• Porous low-k or air gaps• Shortening interconnect lines by stacking chips
• Heterogeneous Integration• The 3D integration of die from different supply
chains at wafer or die-level (as opposed to today’s integration at package level) to form a SiP
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 14
Emergence of 3D Floating Body Architectures for 32 nm and below
• Key ASM technologies required for CMOS to go vertical:• ALCVD (stepcoverage!!)• (Selective) epitaxy • Low temperature LPCVD
Planar CMOS(single gate)
FinFET(double gate)
Trigate(triple gate)
Omega gate(quadruple gate)
S D
BOx BOx
G + ++ -
BOx
+ ++
G
G
G G G
BOx
+ ++G
G G
+G G
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 15
Collaborative Research with IMEC: FinFET Structures with ASM Materials
• (PE)ALD high-k and metal gate is a must for 3D devices
• Implementation of strain and elevated source drain contacts with selective epitaxy of Si:Ge, Si:C
Collaert, et al. VLSI 2005; Hofmann, et al. IEDM 2005
Si Fin
GateASM ALD HfO2 gate dielectric
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 16
Interconnect: 3D Stacked IC or several Generations of Porous Low-k?
• Porous low-k or airgaps• 10-15% lower keff/generation
• More copper• Thinner barriers with
specular e- reflection
• Shorter global interconnect by 3D die or wafer stacking
• Replace global interconnect by optical, wireless links
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dV/d
R
Aurora ULK2.6Aurora ULKHM2.7Aurora ELK2.25Aurora ELK2.5
0
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14
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dV/d
R
Aurora ULK2.6Aurora ULKHM2.7Aurora ELK2.25Aurora ELK2.5
10 mm
0.1 mm
20 mm
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006) 17
Heterogeneous Integration of Die from Different Supply Chains
At package level• Inter-die connections go
via wire of flip chip bumps
At die or wafer level• Inter-die connections go
vertical through the Si die
SensorRadioComputerPowerBattery
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM/IMEC Proprietary Information 18
Thin Si (10µ, wafer or die)
Thin Si (10µ, wafer or die)
Thick Si Substrate (Wafer)
Thin Si (10µ, wafer or die)
Thin Si (10µ, wafer or die)
Thick Si Substrate (Wafer)
3D Stacked IC
Collaborative Research with IMEC 3D Through Hole Via Fill and TC Bonding
• Critical technologies• Via etch/laser drill• Barrier (ALCVD) • Via fill (Cu ECMD) • Cu-Cu bonding/alignment Sea of Cu-Cu Studs in Si. Si removed
for demonstration purposes
Through Si via with ASM ECMD Cu
CuCu
SiSi
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 19
Summary and Conclusions (1 of 2)
ASM’s Technology Platforms• ALCVD
• Polygon ALD high-k gate stacks meet 45 nm specs• Polygon PEALD high-k accepted for RF MIM capacitors• A412 batch ALD for memory productivity
• LPCVD • New applications for ASM’s patented Silcore chemistry
• Epitaxy• Mobility scaling for NMOS and PMOS down to 32 nm with
Epsilon selective deposition of Si:Ge(B) and Si:C(P)• (Rapid) Thermal Process
• Levitor is the only answer to FUSI metal gate work fundctioncontrol
• Emissivity independent heating will be essential to enhance yield
Front-End Operations
© 2006 ASM San Fransisco, July 12 (2006)ASM Proprietary Information 20
Summary and Conclusions (2 of 2)
ASM’s Technology Platforms, continued• PECVD
• Demonstrated, realistic low-k solutions with Aurora on the Eagle product platform
• Competitive, patented approach for hardmask
Longer term technology trends, 32 and 22 nm• Going in 3 dimensions in FEOL (FinFET’s) and BEOL (SIC)• Between back-end and front-end: stacking of chips to
integrate heterogeneous devices from different supply chains• New Materials, new processes, new materials, new processes,
new materials, new processes,…. at an unprecedented rate• Participation in collaborative research essential