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DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH FOR L

A Term Paper Report

On

DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH

FOR LOW POWER VLSI

Submitted by

K.Gnana Deepika (10102330)

In the partial fulfillment of requirements in degree of

Master of Technology (M-Tech)In

VLSI

DEPARTMENT OF ECE

K L UNIVERSITY

GREEN FIELDS, VADDESWARAM- 520002

21st Feb 2011

Department of ECE KL

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DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH FOR L

A Term Paper Report

On

DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH

FOR LOW POWER VLSI

By

K.Gnana Deepika 10102330 M.Te

DEPARTMENT OF ECE

K L UNIVERSITY

GREEN FIELDS, VADDESWARAM- 520002

21st Feb 2011

Department of ECE KL

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DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH FOR L

ACKNOWLEDGEMENTS

Apart from my individual effort, the success of any work depends largely on the

encouragement and guidelines of many others. I take this opportunity to express my gratitude to

the people who have been instrumental in the successful completion of this term paper.

I would like to express my heartful thanks and gratitude to our god almighty, for his

blessings, abundant grace and guidance with which I am able to finish this project successfully.

I avail this opportunity to express my whole deep sense of gratitude and thanks to

beloved Dr.Habibulla Khan,M.Tech., Ph.D HOD,Department of Electronics and

Communication Engineering for his consent efforts in providing help and encouragement.

I express my sincere thanks to my Internal Guide Mr. G.Rakesh Chowdary,

Asst.Professor, Department of Electronics and Communication Engineering for his valuable

suggestions, unending support and encouragement.

I express my utmost gratitude to my Term Paper Coordinators Mr.G.Rakesh

Chowdary, Asst.Professor, Mr. Praveen Blessington. Thummalakunta, Associate Lecturer,

Dept. of ECE for their timely advices and guidance in the course of my term paper work.

With great enthusiasm I thank my parents who were always there for me in providing

support through their well wishes and prayers.

Department of ECE KL

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DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH FOR L

K L UNIVERSITY

DEPARTMENT OF ECE

DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH

FOR LOW POWER VLSI

Duration: 6 months, Date of start: 04-01-2011,

Date of submission: 21-02-2011.

Student Name : K.Gnana Deepika,10102330,

M.Tech (VLSI),

Department of ECE.

Internal guide : G.Rakesh Chowdary,

Asst.Professor,

Department of ECE.

Term Paper Coordinators : Mr. G.Rakesh ChowdaryMr. P Blessington,Assistant professor, Assistan

Department of ECE. Depar

Key words: Sleepy Keeper, Dual Threshold voltage, Static Power Consumption

Research Areas: Low Power VLSI

Department of ECE KL

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DESIGN OF 4 BIT FULL ADDER USING SLEEPY KEEPER APPROACH FOR L

Abstract

As the leakage power dissipation has become an overriding concern for VLSI circuits, different

leakage reduction techniques have been proposed. This paper mainly deals with the SLEEPY

KEEPER , a leakage reduction technique which provides a new weapon in a VLSI designers

arsenal.Sleepy keeper uses traditionalsleep transistors plus two additional transistors

driven by a gates already calculated output to save state during sleep mode. Dual Vth

values can be applied to sleepy keeper in orderto dramatically reduce sub threshold leakage

current. A 1-bit Full Adder with the SLEEPY KEEPER approach is designed and simulated in

LT-Spice. Later, the work is carried out for 4-bit Full Adder and the static power consumption

and dynamic power consumption are calculated.

.

Signature of the Faculty

Mr. G.Rakesh Chowdary K.Gnana Deepika

Assistant professor Department of ECE

Date: 21-02-2011

Department of ECE KL