Control Technology International, Inc.

15468 East Hinsdale CircleCentennial, Colorado 80112-4225 USAPhone: (303)-400-0547 Fax: (303)-400-0571 Toll Free: 1-888-CTII-USAWorldWideWeb: www.ctii-usa.com Email: ctii@ctii-usa.com

Memorandum for Record Subject: CTI 1776-TS Time Stamp/Sequence of Events Recorder Module

From: Stan New, Control Technology International, IncReference: IEEE Standard Surge Withstand Capability (SWC) Test ReportReport Date: Friday, June 05, 1998Test Engineers:

Dan Dodson and Stan New

The 1776-TS Time Stamp/Sequence of Events Recorder Module revision D has been designed and tested to the following standard, IEEE Standard Surge Withstand Capability (SWC) Tests for Protective Relays and Relay Systems [ANSI/IEEE C37.90.1-1989]. The module was subjected to both the oscillatory SWC test and the fast transient test as outlined in the IEEE C37.90.1-1989 standard.

Prior to SWC testing, the module was tested for proper operation. (page 12) Following SWC testing, the module was re-tested. (page 13) The test results illustrate the oscillatory SWC test and the fast transient SWC test had no adverse effects on the module. The module operated satisfactorily after the SWC tests were performed. No soft errors in block transfer or discrete reads were encountered during or after application of the test voltage. Time stamped events in 1776-TS memory before application of the test waveforms, remained unaffected after completion of the tests. The CTI 1776-TS Time Stamp/Sequence of Events Recorder Module revision D surpassed the IEEE C37.90.1-1989 standard.

Test Objective

The objective of this test is to determine if the 1776-TS module will operate satisfactorily when exposed to the harsh transients encountered in a substation type environment. Both hard and soft errors will be evaluated during the test.

The Oscillatory and Fast Transient (SWC) Test Specifications

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2.2 Oscillatory (SWC) Test Wave Shape and Characteristics. The oscillatory SWC test wave is an oscillatory wave, frequency range of 1.0 MHz to 1.5 MHz, voltage range of 2.5kV to 3kV crest value of first peak, envelope decaying to 50% of the crest value of first peak in not less than 6 s from the start of the wave. The source impedance shall be from 150 to 200. The test wave is to be applied to a test specimen at a repetition rate of not less that 50 tests per second for a period of not less than 2.0 seconds. (All voltage and time values refer to the open circuit condition of the generator.)

2.3 Fast Transient (SWC) Test Wave Shape and Characteristics. The fast transient SWC test wave is a unidirectional wave. Its rise time, from 10 to 90 % shall be 10 ns maximum. The crest duration above 90% shall be at least 50 ns. The decay time, from crest to 50% of crest value, shall be 150 ns +/- 50 ns. The crest voltage is between 4kV and 5kV, open circuit. The source impedance during the initial rise time is 80 ohms or less. The test wave is applied for not less than 2 seconds at a repetition rate of not less than 50 pulses per second. Pulses of both polarities are to be applied. (All voltage and time values refer to the open circuit condition of the generator.)

Equipment Used In Testing

Velonex 510 Surge Transient Generator; SN 16705; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606, Last Calibration – JAN 98 (Advanced Test Equipment Corporation, San Diego, CA)

Velonex 3113 Fast Transient Generator, SN 16307; Advanced Test Equipment Rentals, 10401 Roselle St., San Diego, CA 92121-1503, 1-800-404-2832, Last Calibration – MAY 98 (Advanced Test Equipment Corporation, San Diego, CA)

TrueTime 800 Series IRIG-B Time Code Generator; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Sorenson Power Supply (0-400 VDC) Model DCR300-1.5B;SN 0702; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Tektronix THS720 Tekscope; SNB011699; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Fluke 79 Series II Multimeter; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Allen Bradley --- PLC 5/20 Processor Module, 1771-A3B 12 Slot Chassis (19 inch rack mount), P4S 120VAC Power Supply; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Control Technology International --- 1776-TS Time Stamp/Sequence of Events Recorder Module revision D, SN A0027; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

Toshiba Tecra 530CDT Laptop Computer; SN 87217760-3; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

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Allen-Bradley PCMK Series A Communications Card; SN SV1AL4Q0; Control Technology Intl., Inc, 6355 Ward Rd., Suite 420, Arvada CO 80004, (303) 425-7606

1776-TS Time Stamp/ Sequence of Events Recorder Module Description

The 1776-TS module will time stamp 16 external event inputs with millisecond accuracy and 16 PLC determined internal events to PLC scan time accuracy, while running on the Allen-Bradley 1771 I/O platform. The 1776-TS module allows events at one PLC, at various PLCs within a facility, at plants across the nation, or in multiple locations around the world, to be time stamped with millisecond resolution.

Data is stored in memory on the TS card until the PLC can retrieve the time stamped events. Analysis of the data can provide information on which event occurred first, second, third, etc.; in a fault, shutdown, or time logging situation.

APPLICATIONSNow the PLC can run data logging and control programs based on a precise time clock. The PLC can now have increased functionality in areas such as power utilities, instrumentation, process control, industrial automation, petrochemical, traffic control, and numerous data logging applications. PLC events at single or multiple locations can be coordinated with millisecond precision.

IRIG-B INTERFACEAn IRIG-B input source is required for the 1776-TS module to provide clocking information. It can be obtained from any commercial GPS satellite receiver or a stand-alone time code generator that provides a modulated or demodulated IRIG-B output.

The IRIG-B signal is connected to the first TS module. If additional modules are required, the first module will relay the signal to other TS modules in the system. Distance between the first and last module in a system can be up to 4,000 feet. Up to 32 modules (512 points) can be daisy chained together.

Multiple facilities can maintain millisecond clock accuracy among them when using the 1776-TS module in conjunction with a GPS satellite receiver.

INPUTS TO THE 1776-TS MODULEThe wiring arm supplied with the TS module provides easy connection for 16 external points. Any input transition, either off to on or on to off, will trigger an event. An event consists of one input that changes state during a one millisecond period. The module can be ordered with input voltage levels of 24, 48, or 125 volts.

The module can record and store over 2000 events before the PLC has to retrieve data from the 1776-TS module. When an event occurs, an image of the inputs is saved along with a change mask, indicating which input(s) have changed. The time of day stamp (month, day, hour, minute, second, and millisecond) is also added to the event record.

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WHAT IS IRIG-B IRIG-B is a serial time code format that was developed by a governmental agency, so that time-of-year could be recorded and transmitted in serial fashion. Initially the code was used for recording time on magnetic tape, oscillographs, strip charts, and for real time transmission. Since its inception, the use of the IRIG-B format has become a de facto standard for many different applications.

WIRING ARMField wiring connections to the 1776-TS module are made to the 18 terminal wiring arm, which is shipped with the module. The wiring arm pivots upward and connects with the module so that you are able to install or remove the module without disconnecting the wires. All 16 inputs are optically isolated. Two separate input commons are provided on each card.

PLC COMMUNICATIONSCommunications between the 1776-TS module and the PLC is via discrete input/output image tables, along with block transfer reads. Status of the 16 inputs can be read at any time by looking at the associated input file of the module. When an events occurs, the TS module will set a bit in the input image file and build a 5 word block that can be read by the PLC. These blocks of data are buffered by the TS module to prevent loss of data during periods of fast input activity.

1776-TS Time Stamp Points to be Tested

Data / Communications Lines (signal circuits)

BNC connector Pin 1 AM IRIG-B input (signal) BNC connector Pin 2 AM IRIG-B input (reference) Jack 1 Pin 1 DC Level Shift IRIG-B input (signal) Jack 1 Pin 4 DC Level Shift IRIG-B input (reference) Jack 1 Pin 2 RS 422/485 IRIG-B input (signal) Jack 1 Pin 3 RS 422/485 IRIG-B input (reference) Jack 2 Pin 2 RS 422/485 IRIG-B output (signal) Jack 2 Pin 3 RS 422/485 IRIG-B output (reference)

Input / Common Lines (voltage circuits)

Input 00 Pin 1 Input 01 Pin 2 Input 02 Pin 3 Input 03 Pin 4 Input 04 Pin 5 Input 05 Pin 6 Input 06 Pin 7 Input 07 Pin 8 Common 00-07 Pin 17

Input 10 Pin 9 Input 11 Pin 10 Input 12 Pin 11 Input 13 Pin 12 Input 14 Pin 13 Input 15 Pin 14 Input 16 Pin 15 Input 17 Pin 16 Common 10-17 Pin 18

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Fast Transient (SWC) Test Generator Specification

(from the Velonex Instruction Manual Model V-3113)(Fast Transient Generator)

Section 1General Description

1.1 Introduction:

The Velonex Model V-3 113 is a fast transient generator used to test the surge withstand capability (SWC) of protective relays and relay systems. It contains a built-in transient coupler/isolation network allowing the generator's output to be fed to the equipment under test (EUT) while isolating the transients from feeding upstream into the power mains.

The Model V-3113 is an easy to operate, cost effective GPIB bus programmable generator.

1.2 Model V-3113 Specifications:

Maximum Peak Voltage (E0): 4 – 5kV Open Circuit

Rise Time (Tr) 10-90%: 10ns

Pulse Width (Tw) at 90%: 50ns

Decay 100-50%: 150ns; 50ns

Rs During Tr: <= 80 ohms

Repetition Frequency: 1-100Hx (1Hz steps)

Output Polarity: Positive or negative front panel selectable.

Output Current S.C.: 50A

Timed Output: 1-99 seconds selectable or continuous output.

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Velonex V-3113 Fast Transient Generator Settings

PRF: 50HzMode: Non-SyncTest Time: 2.0 SecondsHigh Voltage: 5.0kVPolarity Select: Both Positive and Negative

FIG 1 – Scope Output from Velonex V-3113 Fast Transient Generator

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Surge Transient (SWC) Test Generator Specification

(from the Velonex Operating and Service Manual Model 510)(Surge Transient Generator)

MODEL 510 SPECIFICATIONS

Eopen Circuit: Variable by front-panel control from <1.5kv to 2.5kV maximum (crest value of the first half cycle peak).

Oscillatory Frequency: 1.25 MHz nominal.

Envelope Decay to 50 %of Crest Value (OpenCircuit): 6.0S, minimum.

Rate of Rise to CrestVoltage: <100nS (10% to 90%).

Source Impedance: Selectable l00, l50, 30, 60, l200.

Test Burst Rep Rate: Manual one-shot, plus continuously variable from <20 bursts per second to >120 bursts per second, plus 50 or 60 Hz synchronized with power line, plus 100 or 120 Hz synchronized with power line. Phase of burst is adjustable through >320 with respect to power-line frequency by front-panel control.

Test Duration: Continuously adjustable from <2 seconds to >10 seconds by front-panel control.

Output Isolation: Isolated output is provided on the inner conductors of two type UG-931 high-voltage connectors. Output may be directly applied to any power line voltage up to 500V RMS.

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Velonex 510 Surge Transient Generator Settings

Frequency: 60HzPhase: 0Mode: Line FreqSource Impedance: 150Duration: 2 secondsMode: Timed OutputAmplitude: 2.5 kV

FIG 1 – Scope Output from Velonex 510 Surge Transient Generator

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Testing Performed on the 1776-TS Module

The following test points were connected to both the oscillatory and fast transient generators. When testing with the fast transient generator, both positive and negative voltage levels were applied to the 1777-TS module. The input image table from the 1776-TS module was observed during testing.

Allen-Bradley’s AI5 programming software package was used to monitor the image table. The AI5 software was running on a Toshiba 530CDT laptop. It was connected to the PLC processor via the Allen-Bradley data highway with a PCMK card.

The PLC test rack was populated with a 5/20 processor in the left most slot, and configured for ½ slot addressing. A PS4 power supply was installed in slot 0-1 rack 0. The 1776-TS Time Stamp/ Sequence of Events Recorder Module was installed in slot 6-7 rack 0. The TSDEMO1 program (Appendix 1) was loaded into the PLC 5/20 processor.

Known time stamp data was loaded into the 1776-TS module to see if this data would be intact after each series of tests was complete. In all cases, the data remained valid and we were able to retrieve it using the TSDEMO1 program.

In cases where we were testing the signal circuits, we also caused external events to be triggered with application of a 125VDC level to one of the 16 inputs while the test generator was activated. In all cases, the time stamp data was properly stored in the 1776-TS memory. Data was later recalled from the TS module and verified using the TSDEMO1 program.

ANSI/IEEE C37.90.1-1989 Section 4.3.1.1 Common Mode Test. One terminal of the test generator shall be connected to each connection, or logical group of connections. The other terminal of the test generator shall be connected to the surge ground of the system. Common Mode testing was performed as outlined in Table 1-Signal Circuit Testing and Table 2–Voltage Circuit Testing.

Table 1 – Common Mode Test - Signal Circuit

Generator OUTPUT VOLTAGE

1776-TSRS-422/485

1776-TSBNC

CONNECTORHIGH LOW JAK1 JAK2Pin 1 Chassis Ground X NA XPin 2 Chassis Ground X X X

Pin 1 & 2 Chassis Ground NA NA XPin 3 Chassis Ground X X NAPin 4 Chassis Ground X NA NA

Pin 1 & 4 Chassis Ground X NA NAPin 2 & 3 Chassis Ground X X NA

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Table 2 – Common Mode Test - Voltage Circuit

Generator OUTPUT VOLTAGE

HIGH LOW1 Chassis Ground2 Chassis Ground3 Chassis Ground4 Chassis Ground5 Chassis Ground6 Chassis Ground7 Chassis Ground8 Chassis Ground9 Chassis Ground10 Chassis Ground11 Chassis Ground12 Chassis Ground13 Chassis Ground14 Chassis Ground15 Chassis Ground16 Chassis Ground17 Chassis Ground18 Chassis Ground

1-18** Chassis Ground

** Pins 1 through 18-jumped together

ANSI/IEEE C37.90.1-1989 Section 4.3.1.2 Transverse (Differential) Mode Test. The terminals of the test generator shall be connected across the terminals of the signal circuit. Transverse Mode testing was performed as outlined in Table 3-Signal Circuit Testing and Table 4–Voltage Circuit Testing.

Table 3 – Transverse Mode Test - Signal Circuit Tests

Generator OUTPUT VOLTAGE

1776-TSRS-422 1776-TS

COAX INHIGH LOW JAK1 JAK2Pin 1 Pin 2 NA NA XPin 1 Pin 4 X NA NAPin 2 Pin 3 X X NA

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Table 4 – Transverse Mode Test - Voltage Circuit Tests

Generator OUTPUT VOLTAGEHIGH LOWPin 1 Pin 17Pin 2 Pin 17Pin 3 Pin 17Pin 4 Pin 17Pin 5 Pin 17Pin 6 Pin 17Pin 7 Pin 17Pin 8 Pin 17Pin 9 Pin 18Pin 10 Pin 18Pin 11 Pin 18Pin 12 Pin 18Pin 13 Pin 18Pin 14 Pin 18Pin 15 Pin 18Pin 16 Pin 18

Pins 1-8* Pin 17Pins 9-16** Pin 18

* Pins 1 through 8-jumped together** Pins 9 through 16-jumped together

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1776-TS MODULE TEST REPORT

(Prior to ANSI/IEEE C37.90.1-1989 testing)

1776-TS Module Test Report 05/05/98

Catalog #:1776-TS-125VDC Serial #: A0027 Date tested: 5/5/98 Tested By: DJD Build #:

Board rev. D

PROCEDURES: Download 1776C03.C (Z-World) and 1776A01.MSA (Atmel) programs. Check revision in

word N9:1. (N9:1/13=0, N9:1/14=1, N9:1/15=1) Confirm “ACTIVE” light flashing upon RS-422, DC Level Shift, and Amplitude Modulated

input valid. Reference manual for dip-switch settings. While in Amplitude Modulated dip-switch setting, set pot to middle of active range. Return switches to RS-422.

Set SW2 to 10ms. Plug in adjacent card to confirm signal passes through present card Check I:6/10 for watchdog pulse from master clock

CHECK INPUTS: Toggle each input & make sure it appears in data table & LED lights “Rapid fire” all 16 inputs and review N10 buffer for correct info Measure edge level of worst case input for both on to off and off to on transitions. The

maximum on and off state voltage levels must fall within the following limits based upon the input voltage level of the card being tested.

Module Type Maximum Off-State Voltage

Minimum On-State Voltage

1776-TS-24VDC 8 VDC 20 VDC1776-TS-48VDC 16 VDC 40VDC1776-TS-125VDC 40 VDC 100VDC

CHECK OUTPUTS: With simulator card check each output via output data file “Rapid fire all 8 switches on simulator card and review N10 buffer for correct info

FINAL: Add sticker to inside of case with date, tested by, software ver. #

NOTES:

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1776-TS MODULE TEST REPORT

(After ANSI/IEEE C37.90.1-1989 testing)

1776-TS Module Test Report 06/04/98

Catalog #:1776-TS-125VDC Serial #: A0027 Date tested: 6/4/98 Tested By: SN Build #:

Board rev. D

PROCEDURES: Download 1776C03.C (Z-World) and 1776A01.MSA (Atmel) programs. Check revision in

word N9:1. (N9:1/13=0, N9:1/14=1, N9:1/15=1) Confirm “ACTIVE” light flashing upon RS-422, DC Level Shift, and Amplitude Modulated

input valid. Reference manual for dip-switch settings. While in Amplitude Modulated dip-switch setting, set pot to middle of active range. Return switches to RS-422.

Set SW2 to 10ms. Plug in adjacent card to confirm signal passes through present card Check I:6/10 for watchdog pulse from master clock

CHECK INPUTS: Toggle each input & make sure it appears in data table & LED lights “Rapid fire” all 16 inputs and review N10 buffer for correct info Measure edge level of worst case input for both on to off and off to on transitions. The

maximum on and off state voltage levels must fall within the following limits based upon the input voltage level of the card being tested.

Module Type Maximum Off-State Voltage

Minimum On-State Voltage

1776-TS-24VDC 8 VDC 20 VDC1776-TS-48VDC 16 VDC 40VDC1776-TS-125VDC 40 VDC 100VDC

CHECK OUTPUTS: With simulator card check each output via output data file “Rapid fire all 8 switches on simulator card and review N10 buffer for correct info

FINAL: Add sticker to inside of case with date, tested by, software ver. #

NOTES:

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APPENDIX 1 – TSDEMO1

TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00001 07:34 08/28/97 ------------------------------------------------------------------------------- | |Assumes the TS module is in the 4th slot (group 6-7) of the I/O rack if using |1/2 slot addressing, or the 8th slot (group 7) if using 1 slot addressing. Be |sure to check all dip switches on the module and rack. This rung downloads |the year from the PLC to the TS module on power up and once every hour at 30 |minutes past the hour. The IRIG-B protocol doesn't include year data. | | | Subtract 1900 | Real time before loading | clock to the TS | MINUTE Single Shot module | +--CMP-----------+ B3 +--MOV-----------+ 0+-++Compare +-----[ONS]----+----------++Move +------+- | ||Expression: | 0 | ||Source: S:18| | | || S:22 = 30| | || 1997| | | |+----------------+ | ||Dest: N7:0| | | | | || 96| | | |First scan | |+----------------+ | | |of ladder | | | | |or SFC | |Subtract 1900 | | |step | |before loading | | | S:1 | |to the TS | | +----] [-------------------------+ |module | | 15 |+--SUB-----------+ | | ++Sub +------+ | ||A: N7:0| | | || 96| | | ||B: 1900| | | ||Dest: N7:0| | | || 96| | | |+----------------+ | | |Subtract 1900 | | |before loading | | |to the TS | | |module | | |+--BTD----------------+ | | ++Bit Field Distributor+-+ | |Source: N7:0| | | 96| | |Source Bit: 0| | |Dest: O:006| | | 24576| | |Dest Bit: 8| | |Length: 7| | +---------------------+

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00002 07:34 08/28/97 ------------------------------------------------------------------------------- | |This rung moves a 1 into N10:10/0 for viewing from that file. If a 1, there is |data in the TS module that is waiting to be transferred to the PLC. Also in |file N10:11/0 is a data bit to show if data that has been transferred from the |TS module to files N9 and N10. Setting bit N10:12/0 to a 1 will transfer data |from the TS module to the PLC. | |DATA BT BIT |rack 0 group 6 Move a 1 to N10 |there is new :10/0 if there |data in the TS is data in the |module TS module | I:006 N10:10 1+-------] [----------------------------------------------------( )-------- | 12 0 | |This rung is important if you wish to retrieve data from the TS module over the |data highway using Visual Basic, RSView, etc. This rung will make sure bit |N10:12/0 will only get set at one place in the ladder program. This will |prevent unexpected results. Make sure bit I6/12 is on and bit N10:12/0 is off |before setting bit B3/4 on, to retrieve new data from the TS module. | |Use this bit if |you need to set FETCH DATA BIT |bit N10:12.0 move data from |outside the PLC 1776-TS module |program Single Shot to PLC memory | B3 B3 N10:12 2+-------] [-----------[ONS]------------------------------------(L)-------- | 4 5 0 | |This rung enables data transfer from the TS module to the PLC. If setting bit |B3/4 outside the PLC program (with a Visual Basic program, etc.), make sure |the PLC is not in program mode. If in program mode the data read from file |N10:0-9 will not be valid and will remain it is last state. Loss of data from |the TS module can happen if this is not observed. | |DATA BT BIT Data Xfer Bit |rack 0 group 6 FETCH DATA BIT set when data |there is new move data from Block transfer is transferred |data in the TS 1776-TS module read instruct. from TS module |module to PLC memory enabled bit to PLC memory | I:006 N10:12 BT11:0 B3 3+-------] [--------------] [--------------]/[------------------(L)-------- | 12 0 EN 2

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00003 07:34 08/28/97 ------------------------------------------------------------------------------- | |Block transfer the data from the TS module to file N9:0. This file is 5 words |in length. It is the raw data as described in the 1776-TS manual. Before |doing a block transfer, be sure to observe the above restrictions. Once the |data is read by the BTR, it is no longer available in the TS module. | |Data Xfer Bit Read the module |set when data at rack 0 group |is transfered 6 module 0 |from TS module location, put |to PLC memory file in N9:0 | B3 +--BTR--------------------+ 4+-------] [-----------------------------+Block Transfer Read +-(EN)- | 2 |Mod Type: 1771-??| | | Other BLK XFER Module+-(DN) | |Rack: 0| | |Group: 7+-(ER) | |Module: 0| | |Control Block: BT11:0| | |Data File: N9:0| | |Length: 5| | |Continuous: N| | +-------------------------+ | |This rung will monitor when the data is finished being transferred from the TS |module to file N9. | |Data Xfer Bit |set when data The data from |is transfered Block transfer the TS module |from TS module read is now is now in file |to PLC memory complete N9, words 0-4 | B3 BT11:0 B3 5+-------] [--------------] [-----------------------------------(L)-------- | 2 DN 3 | |This rung clears the file N10 words 0 through 9 to zeros before moving new data |from file N9. | |The data from |the TS module Clear the file |is now in file before moving |N9, words 0-4 new data in | B3 +--FAL------------------+ 6+-------] [-------------------------------+File Arithmetic/Logical+-(EN)- | 3 |Control: R6:1| | |Length: 10+-(DN) | |Position 0| | |Mode: ALL+-(ER) | |Dest: #N10:0| | | 0| | |Expression: | | | 0| | +-----------------------+

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00004 07:34 08/28/97 ------------------------------------------------------------------------------- | |The file N9 is now being pulled apart and put into a more readable format. The |next 10 rungs will extract that data and put it into file N10. File N10 word 0 |contains an IRIG-B time clock flag in bit 1 (0=valid,1=invalid),and an internal/ |external flag in bit 0. If this flag is 0 an external event occurred. If it is |a 1, an internal (ie., PLC programmed event) occurred. | |The data from Ref Valid 15 |the TS module Int/Ext 14 |is now in file Month 11-08 |N9, words 0-4 Day 04-00 | B3 +--BTD----------------+ 7+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:0| | | 2835| | |Source Bit: 14| | |Dest: N10:0| | | 0| | |Dest Bit: 0| | |Length: 2| | +---------------------+ | |N10 word 1 contains a change mask which shows all bits which have changed |during the recorded millisecond. A 1 indicates that a bit has changed state. | |The data from |the TS module |is now in file |N9, words 0-4 Change Mask | B3 +--MOV-----------+ 8+-------] [-------------------------------------------+Move +-- | 3 |Source: N9:4| | | 1| | |Dest: N10:1| | | 1| | +----------------+ | |N10 word 2 shows the current status of all the inputs. A 1 shows the input is |on, while a 0 shows the input was off. The current status refers to the |current time stamp associated with this event. | |The data from |the TS module |is now in file |N9, words 0-4 Status off/on | B3 +--MOV-----------+ 9+-------] [-------------------------------------------+Move +-- | 3 |Source: N9:3| | | 0| | |Dest: N10:2| | | 0| | +----------------+

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00005 07:34 08/28/97 ------------------------------------------------------------------------------- | |N10 word 3 shows the current year. This information is obtained from the PLC |clock and downloaded to the TS module. | |The data from |the TS module |is now in file |N9, words 0-4 Year | B3 +--MOV-----------+ 10+-------] [-------------------------------------------+Move +-- | 3 |Source: S:18| | | 1997| | |Dest: N10:3| | | 0| | +----------------+ | |N10 word 4 contains the month from the IRIG-B clock. | |The data from Ref Valid 15 |the TS module Int/Ext 14 |is now in file Month 11-08 |N9, words 0-4 Day 04-00 | B3 +--BTD----------------+ 11+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:0| | | 2835| | |Source Bit: 8| | |Dest: N10:4| | | 0| | |Dest Bit: 0| | |Length: 4| | +---------------------+ | |N10 word 5 contains the day from the IRIG-B clock. | |The data from Ref Valid 15 |the TS module Int/Ext 14 |is now in file Month 11-08 |N9, words 0-4 Day 04-00 | B3 +--BTD----------------+ 12+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:0| | | 2835| | |Source Bit: 0| | |Dest: N10:5| | | 0| | |Dest Bit: 0| | |Length: 5| | +---------------------+

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00006 07:34 08/28/97 ------------------------------------------------------------------------------- | |N10 word 6 contains the hour from the IRIG-B clock. | |The data from |the TS module |is now in file Hour 12-08 |N9, words 0-4 Minute 05-00 | B3 +--BTD----------------+ 13+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:1| | | 3378| | |Source Bit: 8| | |Dest: N10:6| | | 0| | |Dest Bit: 0| | |Length: 5| | +---------------------+ | |N10 word 7 contains the minute from the IRIG-B clock. | |The data from |the TS module |is now in file Hour 12-08 |N9, words 0-4 Minute 05-00 | B3 +--BTD----------------+ 14+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:1| | | 3378| | |Source Bit: 0| | |Dest: N10:7| | | 0| | |Dest Bit: 0| | |Length: 6| | +---------------------+ | |N10 word 8 contains the second from the IRIG-B clock. | |The data from |the TS module |is now in file Seconds 15-10 |N9, words 0-4 MilliSec. 09-00 | B3 +--BTD----------------+ 15+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:2| | | 30383| | |Source Bit: 10| | |Dest: N10:8| | | 0| | |Dest Bit: 0| | |Length: 6| | +---------------------+

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00007 07:34 08/28/97 ------------------------------------------------------------------------------- | |N10 word 9 contains the millisecond from the IRIG-B clock. | |The data from |the TS module |is now in file Seconds 15-10 |N9, words 0-4 MilliSec. 09-00 | B3 +--BTD----------------+ 16+-------] [--------------------------------------+Bit Field Distributor+-- | 3 |Source: N9:2| | | 30383| | |Source Bit: 0| | |Dest: N10:9| | | 0| | |Dest Bit: 0| | |Length: 10| | +---------------------+ | |You can now set the XFER VALID BIT for other parts of the program to read, or |for an external program such as Visual Basic & RS Tools to monitor. The data |in files N9 and N10 need to be acted upon or saved before the next event is |read from the TS module. | | XFER VALID BIT |The data from Check to make data in files |the TS module sure there was N9 and N10 has |is now in file no error on the been transferred |N9, words 0-4 block transfer from TS module | B3 BT11:0 N10:11 17+-------] [--------------]/[-----------------------------------(L)-------- | 3 ER 0 | |Go ahead and reset these 2 bits to prepare for the next data transfer. | | Data Xfer Bit |The data from set when data |the TS module is transferred |is now in file from TS module |N9, words 0-4 to PLC memory | B3 B3 18+-------] [------------------------------------------+-------(U)-------+- | 3 | 2 | | |The data from | | |the TS module | | |is now in file | | |N9, words 0-4 | | | B3 | | +-------(U)-------+ | 3

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TSDEMO1 1776-TS Sample Demo Program Control Technology International, Inc. File #2 Proj:TSDEMO1 Page:00008 07:34 08/28/97 ------------------------------------------------------------------------------- | |When bit N10:12/0 is set (FETCH DATA BIT) data is transfered from the TS module |to files N9 and N10. This bit can be set by other rungs in the program or by |an external program such as Visual Basic. This bit is self clearing. Before |turning this bit on, one should look to see if the DATA BT BIT is set (there is |data in the TS module). Monitor the XFER VALID BIT to see if transfer was good. | | XFER VALID BIT |FETCH DATA BIT data in files |move data from N9 and N10 has |1776-TS module been transfered |to PLC memory from TS module | N10:12 N10:11 19+-------] [------------------------------------------+-------(U)-------+- | 0 | 0 | | |FETCH DATA BIT | | |move data from | | |1776-TS module | | |to PLC memory | | | N10:12 | | +-------(U)-------+ | 0 | |Be sure to remove this rung from any final product. It copies the input bits |from an 8 point simulator module in rack 0, group 2, to the output bits of |the TS module at rack 0, group 7. This is to demonstrate the internal time |stamping ability of the TS module. Note that when this event is time stamped |bit N10:0/0 is set to a one. This is how to tell the event was internal. | | +--MOV-----------+ 20+-----------------------------------------------------+Move +-- | |Source: I:002| | | 255| | |Dest: O:007| | | 0| | +----------------+ | |To test the program go to integer file N10 word 12. Monitor word 10 to see if |the TS module has valid data. If so, then write a 1 to word 12. If word 11 |contains a one, the transfer was successful, and file N10:0-9 has valid data. |Continue to write ones to word 12 to empty the 1776-TS buffer. Check work 0, |make sure bit1=0 after the transfer, else there was an invalid time reference. | 21+------------------------------------------------------------------[END]--

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