TESTING ACTIVITIES IN PARISDAMIC kick off meeting

Paris 11/06/2018

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Romain Gaïor (LPNHE Paris) for the Paris Group Hardware: H. Lebbolo, L. Khalil, M. Dhelot. Firmware: D. Martin Software: P. Bailly, Z. Wang

CCD ACQUISITION

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Clock

Signal

Clock / BiasGeneration

AmplificationCDS

Numeric Conversion(ADC)

DCpower

DAQControl

CCD

Flex cable

ACTIVITIES IN PARIS

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Clock

Signal

Clock / BiasGeneration

AmplificationCDS

Numeric Conversion(ADC)

DCpower

DAQControl

CCD

Flex cable

ASPIC / CROC

18 bits 15 MS/s board

(see Latifa’s talk)

CABAC

ASPIC

4

• ASIC developed for LSST

• Programmable gain 1 to 13

• On chip DSI (Dual Slope Integrator) max RC = 4us

LCA-11656 ASPIC4 Testing Report Page 9 of 27

Hard copies of this document should not be considered the latest revision beyond the date of printing.

Figure 3 Power consumption increase with input for the ASPIC itself and for the whole setup.

11 Programmable gains

The diagram of a single channel of the ASPIC4 is shown below. The first-stage amplifier is on the left, with four switches to set the first-stage gain G. Its output is split between a buffer amplifier and an inverter amplifier. On the right are the integrating amplifiers for the DSI operation. The RC time constant of the amplifiers is set by the four switches selecting the resistors.

11.1 First-stage amplifier

Like in ASPIC3, there is a very good agreement between the gain of the first stage-amplifier obtained for every possible setting on the 4-bit G value, and the expected gain from post-layout simulation. The

0

20

40

60

80

100

120

140

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8

Curren

t(mA)

Amplitudeofinputpulses(V)

ASPICandBEBpowerconsump0on

BEBsupply

ASPICVDD

ASPICSaturaTon

ASPIC: TEST BENCH

5

CCD Frame

AdapterASPIC

ASPIC: SOME RESULTS

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Tests at U of Chicago • Used ASPIC with a Leach

system and a CCD • Minimum noise of 5 e-

Mesure de bruit (2)

Latifa KHALIL

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• Mode Transparent• Entrée liée à la masse• Fréquence de lecture : 100 kHz• Durée de TS = 1.8µs

Fuite en fonction de Gain gain F = 50 khz

F = 10 khz

0000 140.94 71.890001 135.81 69.080010 132.43 67.260011 127.18 64.710100 112.13 56.920101 106.59 54.220110 103.2 52.780111 98.42 49.891000 73.94 37.031001 68.02 34.131010 64.98 32.571011 59.69 30.051100 44.53 22.461101 39.52 19.881110 36.12 18.141111 30.98 15.69AF1 0.022 0.000014

• On a un but de mesurer le bruit à basse fréquence, on sort le Clamp de la séquence .

• On a remarqué qu’il y a une fuite au niveau des capacité dans de l’ASPIC

• Cette fuite diminue avec le gain • Au Mode AF1 :la fuite est nulle

NB : fuite en µv/sec

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Trigger :

Clamp

Conv

T(sec)

T(sec)

time in ms 10

Test in Paris • Amplitude evolution with time • Noise measurements

ADC

0

First image with ASPIC and a DAMIC CCD

From Ryan Thomas

no clamp

ADU

frequency

Time

CABAC

7

FPGA

3CABAC board

Test board

DC input

• ASIC developed for LSST • Programmable output clocks, adjustable slopes • DAMIC CCD require more clocks and Bias —> 3CABAC • Add on board to test the clocks

ASPIC + CABAC: TEST BENCH

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FPGA ADC ASPIC 3CABAC

• Requires a set of adjustment in hardware/firmware/software • First time these solutions work together

ASPIC + CABAC: SOFTWARE

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ASPIC + CABAC: FIRST TEST

10

Vertical Clock

Horizontal Clock

ADC command

• hypothetical 4 lines x 8 column CCD • Set all the required clocks • Will test with a CCD in the next weeks

NEXT STEPS

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• Test of read out and clocking integrated solutions (ASPIC and CABAC) with a CCD

• Design a similar test bench for CROC • Compare it with existing solutions

(test bench equipped with a Leach)

Back up

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DAQ and control

11Daniel Charlet Journées IN2P3 Clermont-Ferrand -05-2018

Carte IDROGEN

ARRIA 10 SX10AX027H4F34

IP bus Ethernet 1G

PCIEx 4x Gen3

IPMB

ATMEGA128

EPCQ

SFP+

Ethernet 40G

RTM

WREthernet 1G

White rabbitEthernet 1G

Serial link 40G

spi

Uart

Uart

PPS / trig.Ext

MAX10

I2C

CypressFX2LP

JTA

G

AS

pro

g

LMK04828

LT10104

CLK.Ext

CLK

54

1606

8

I2CSPI

QSFP+

I2C

I2C

USB

IDROGEN board

JTAG

SI5338

I2C

CLK

4

FM

C+• On board configuration (µC)

• Very low noise synthesizer PLL synthesizer cleaner (LM04828) for WR clkand derived clkl.

• Dedicated PLL for serial links● Integrated USBBlaster II.● FPGA configuration : Active serial,

IP bus.● External connectivity : PPS, Trigger,

Ext CLK.

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CABAC

Cabac #2

+40V/BGND

V123 H123a SWa

VDDa

CKP012 CKS012 RG

LVDS CLOCK Cab1

RGa RGb

CKS0 CKS1

Commentaires : CKP3 cabac1 point test CKP123 cabac2 points tests CKP3 cabac3 point test CKP0123 cabac3 points test CKS2 et RG cabac3 points test

OG SPARE RD GD

OD0

TG H123b SWb

CKP0 CKS 0 1 2 RG

OD1

OPA547 Suiveur +10V & BGND

VDD VU VDD VL

RAIL CABAC1

VDD HU VDD HL

OPA445 * (-1) +10V & -30V

VRa

SPARE RD GD

VDDb

OD0 OG

VRb OGb

VDD_TG_U VDD_TG_L

VDD_SW_U

RAIL CABAC2

OGa

OG

SPARE RD GD

VDD_RG_U VDD_RG_L

VDD_SW_L

VSUBCCD

OD0

PA78 *(5)

RAIL CABAC3

VDD_U VDD_ L 10 ohms au BGND

Cabac #1

+40V/BGND

DS90C031B CMOS TO LVDS

MOSI, NRESET, SCLK, NSS CAB1, RO Cab1

SN74AVC4T245 3.3V TO 2.5V

SN74LVCC3245a 2.5V TO 3.3V

LVDS CLOCK Cab1

LVDS CLOCK Cab1

LVDS CLOCK Cab1

OPA547 Suiveur +10V & BGND

OD1

OPA445 * (-1) +10V & -30V

DS90C031B CMOS TO LVDS

MOSI, NRESET, SCLK, NSS CAB1, RO Cab2

SN74AVC4T245 3.3V TO 2.5V

SN74LVCC3245a 2.5V TO 3.3V

LVDS CLOCK Cab2

LVDS CLOCK Cab2

Cabac #3

+40V/BGND

OPA547 Suiveur +10V & BGND

DS90C031B CMOS TO LVDS

MOSI, NRESET, SCLK, NSS CAB1, RO Cab2

SN74AVC4T245 3.3V TO 2.5V

SN74LVCC3245a 2.5V TO 3.3V

LVDS CLOCK Cab2

LVDS CLOCK Cab2

Con 160p SAMTEC HSMC

Con 50p

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