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Page 1: Testing flash memories - ictest8.com · Flash Memory Functional Test. Testing Flash Memories 19 Flash Memory Functional Test Test Coverage of Zero-One Algorithm fCan’t detect all

Testing Flash Memories 1

Testing Flash Testing Flash MemoriesMemories

By Yi GongBy Yi Gong20042004

All Right ReservedAll Right Reserved

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Testing Flash Memories 2

Copy Right InformationCopy Right Information

This presentation is written by This presentation is written by Mr.GongMr.Gong YiYiYou may copy, distribute and spread it by keepingauthor’s name and copy right information.

2004 All Right ReservedAuthor contact:[email protected]

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Testing Flash Memories 3

CONTENTSCONTENTS

Introduce to Flash MemoryIntroduce to Flash MemoryFaults in MemoriesFaults in MemoriesFlash Memory Functional TestFlash Memory Functional TestFlash Memory Parametric TestFlash Memory Parametric TestFlash Memory Reliability TestFlash Memory Reliability Test

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Testing Flash Memories 4

Introduce to Flash MemoryIntroduce to Flash Memory

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Testing Flash Memories 5

Introduce to Flash MemoryIntroduce to Flash Memory

What is Flash Memory?What is Flash Memory?Flash Memory is an EEPROMFlash Memory is an EEPROM

Electrical Programmable and ErasableElectrical Programmable and Erasable

Flash Memory is an NVMFlash Memory is an NVMNonNon--Volatile MemoryVolatile Memory

Flash Cells can be erased simultaneouslyFlash Cells can be erased simultaneouslyParallel ErasableParallel Erasable

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Testing Flash Memories 6

Introduce to Flash MemoryIntroduce to Flash Memory

Flash Memory is PopularFlash Memory is Popular

2000 Memory Market

78% 12%

10%

DRAM NVM SRAM

2000 NVM Market

55%16%

7%

20%

Flash Memory ROM EPROM Other

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Testing Flash Memories 7

Introduce to Flash MemoryIntroduce to Flash Memory

Flash Memory ApplicationsFlash Memory ApplicationsWireless ApplicationsWireless ApplicationsPersonal Digital EquipmentsPersonal Digital EquipmentsDigital Set Top BoxesDigital Set Top BoxesAutomotive ApplicationsAutomotive ApplicationsTelecom and Networking EquipmentsTelecom and Networking Equipments

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Testing Flash Memories 8

Flash Memory Market Share (2001)Flash Memory Market Share (2001)

Introduce to Flash MemoryIntroduce to Flash Memory

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Testing Flash Memories 9

GateGate

Floating GateFloating Gate

DrainDrain SourceSource

Program: Hot Electron EjectionProgram: Hot Electron Ejection

Erase: FowlerErase: Fowler--NordheimNordheim TunnelingTunneling

Introduce to Flash MemoryIntroduce to Flash Memory

Flash Memory CellFlash Memory Cell

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Testing Flash Memories 10

Introduce to Flash MemoryIntroduce to Flash MemoryFloating GateFloating Gate

The The VtVt of a FGMOS transistor is given by:of a FGMOS transistor is given by:VtVt=K=K--Q/CoxQ/CoxK: constant, depends on transistor propertiesK: constant, depends on transistor propertiesQ: charge in FGQ: charge in FGCox: gate oxide capacitanceCox: gate oxide capacitance

A: No ChargeA: No ChargeB: ChargedB: Charged

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Testing Flash Memories 11

Faults in MemoriesFaults in Memories

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Testing Flash Memories 12

Faults in MemoriesFaults in Memories

Fault ManifestationFault ManifestationPermanent Faults (hard faults)Permanent Faults (hard faults)

Design faultsDesign faultsBroken componentsBroken componentsMask faultsMask faults

NonNon--Permanent FaultsPermanent FaultsTransient faults (caused by environment)Transient faults (caused by environment)

cosmic ray, alpha particles, temperature, pressure, humiditycosmic ray, alpha particles, temperature, pressure, humidity

Intermittent faults (not caused by environment)Intermittent faults (not caused by environment)Loose connection, aging components, noiseLoose connection, aging components, noise

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Testing Flash Memories 13

Faults in MemoriesFaults in Memories

Failure MechanismsFailure MechanismsElectrical Stress (inElectrical Stress (in--circuit) Failurecircuit) Failure

Caused by poor design, ESDCaused by poor design, ESD

Intrinsic Failure MechanismsIntrinsic Failure MechanismsCrystal defects, process defectsCrystal defects, process defects

Extrinsic Failure MechanismsExtrinsic Failure MechanismsMetal deposition, bondingMetal deposition, bonding

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Testing Flash Memories 14

Faults in MemoriesFaults in Memories

Memory Fault ClassificationMemory Fault ClassificationFunctional FaultsFunctional Faults

Stuck at faultsStuck at faultsCoupling faultsCoupling faultsPattern sensitive faultsPattern sensitive faults

Parametric FaultsParametric FaultsLeakage faultsLeakage faultsInsufficient input/output levelInsufficient input/output levelAbnormal power consumptionAbnormal power consumption

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Testing Flash Memories 15

Flash Memory Flash Memory Functional TestFunctional Test

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Flash Memory Functional TestFlash Memory Functional TestReduced Flash Memory Functional ModelReduced Flash Memory Functional Model

Address Latch Column Decoder

Cell ArrayRow Decoder Write Driver

Data RegisterSense Amplifiers

RE/WE/CE/OERE/WE/CE/OE

AddressAddress

Data in/outData in/out

Blue: AddressBlue: Address

Red: DataRed: Data

Black: Control SignalBlack: Control Signal

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Testing Flash Memories 17

Flash Memory Functional TestFlash Memory Functional Test

Functional Test Algorithms for Flash MemoryFunctional Test Algorithms for Flash MemoryZeroZero--OneOneCheckerboardCheckerboardGALPATGALPATWalking 1/0Walking 1/0Sliding DiagonalSliding Diagonal

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Testing Flash Memories 18

ZeroZero--One AlgorithmOne AlgorithmAlso known as Memory Scan (MSCAN)Also known as Memory Scan (MSCAN)

Step 1: Write 0 in all cellsStep 1: Write 0 in all cellsStep 2: Read all cellsStep 2: Read all cellsStep 3: Write 1 in all cellsStep 3: Write 1 in all cellsStep 4: Read all cellsStep 4: Read all cells

Step

1 2 3 4

W0 R0 W1 R1

AllCells

Flash Memory Functional TestFlash Memory Functional Test

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Testing Flash Memories 19

Flash Memory Functional TestFlash Memory Functional Test

Test Coverage of ZeroTest Coverage of Zero--One AlgorithmOne AlgorithmCanCan’’t detect all Address decoder faults.t detect all Address decoder faults.SAF will be detected as long as address decoder SAF will be detected as long as address decoder is correct.is correct.Not all Transient Faults are detected.Not all Transient Faults are detected.

Cell may contain 0s before step 1.Cell may contain 0s before step 1.

Not all coupling Faults are detected.Not all coupling Faults are detected.Cell may contain 0s before step 1.Cell may contain 0s before step 1.

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Testing Flash Memories 20

Flash Memory Functional TestFlash Memory Functional Test

ZeroZero--One Algorithm (contOne Algorithm (cont’’d)d)Test length=4*2Test length=4*2N N (N=Total Address Bits)(N=Total Address Bits)Easy to implementEasy to implementLittle test strengthLittle test strength

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Testing Flash Memories 21

Flash Memory Functional TestFlash Memory Functional Test

Checkerboard AlgorithmCheckerboard AlgorithmCells are divided into two groups, cellCells are divided into two groups, cell--a and cella and cell--b, formb, form--inging a checkerboard pattern.a checkerboard pattern.

Step 1: Write 1 in all cellStep 1: Write 1 in all cell--a and 0 in cella and 0 in cell--bbStep 2: Read all cellsStep 2: Read all cellsStep 3: Write 0 in all cellStep 3: Write 0 in all cell--a and 1 in cella and 1 in cell--bbStep 4: Read all cellsStep 4: Read all cells

a b a b

b a b a

a b a b

b a b a

Step

1 2 3 4

cell-a w1 r1 w0 R0

cell-b w0 r0 w1 r1

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Testing Flash Memories 22

Flash Memory Functional TestFlash Memory Functional Test

Test Coverage of Checkerboard AlgorithmTest Coverage of Checkerboard AlgorithmNot all Address Decoder faults are detectedNot all Address Decoder faults are detectedSAF can be detected as long as the Address DeSAF can be detected as long as the Address De--coder is correct.coder is correct.Not all Transient Faults are detected.Not all Transient Faults are detected.

Initial cell status unknown.Initial cell status unknown.Not all Coupling Faults are detected.Not all Coupling Faults are detected.

Initial cell status unknown.Initial cell status unknown.

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Testing Flash Memories 23

Flash Memory Functional TestFlash Memory Functional Test

Checkerboard Algorithm (ContCheckerboard Algorithm (Cont’’d)d)Detects shorts between adjacent cellsDetects shorts between adjacent cellsWorse case test for leakage between adjacent cellsWorse case test for leakage between adjacent cells

Each cell containing a 1 is surrounded by 0sEach cell containing a 1 is surrounded by 0sTest length=4*2Test length=4*2N N (N=Total Address Bits)(N=Total Address Bits)

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Testing Flash Memories 24

Flash Memory Functional TestFlash Memory Functional Test

GALPAT AlgorithmGALPAT AlgorithmMemory is filled with 0s (or 1s) except for the baseMemory is filled with 0s (or 1s) except for the base--cell,cell,which contains a 1 (or 0). The basewhich contains a 1 (or 0). The base--cell walks through cell walks through the whole array and all cells except the basethe whole array and all cells except the base--cell are read, cell are read, after each other cell also the baseafter each other cell also the base--cell is read.cell is read.

0 0 0

0 1 0

0 0 0

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Testing Flash Memories 25

Flash Memory Functional TestFlash Memory Functional TestGALPAT Algorithm (ContGALPAT Algorithm (Cont’’d)d)

Step 1: for d:=0 to 1 doStep 1: for d:=0 to 1 dobeginbegin

for i:=0 to nfor i:=0 to n--1 do1 doA(iA(i):=d;):=d;

for basefor base--cell:=0 to ncell:=0 to n--1 do1 dobeginbegin

Step 2:Step 2: A(baseA(base--cell):=dcell):=d’’;;GotoGoto READREADA(baseA(base--cell):=d;cell):=d;

end;end;end;end;

Step 3: {READ}Step 3: {READ}beginbeginfor cell:=0 to nfor cell:=0 to n--1 do1 dobeginbegin

if (if (A(cellA(cell)<>d) then output ()<>d) then output (““Error at cellError at cell””, cell);, cell);if (if (A(baseA(base--cell)<>dcell)<>d’’) then output () then output (““Error at cellError at cell””, cell);, cell);

endendendend

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Testing Flash Memories 26

Flash Memory Functional TestFlash Memory Functional Test

Test Coverage of GALPAT AlgorithmTest Coverage of GALPAT AlgorithmAll Address Decoder Faults are detected and located.All Address Decoder Faults are detected and located.All SAF will be located because the baseAll SAF will be located because the base--cell iscell iswritten and read with 0 and 1.written and read with 0 and 1.All Transient Faults are located because the baseAll Transient Faults are located because the base--cell make transitions after which it is read. cell make transitions after which it is read.

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Testing Flash Memories 27

Flash Memory Functional TestFlash Memory Functional Test

GALPAT Algorithm (ContGALPAT Algorithm (Cont’’d)d)Test length=2*(2Test length=2*(2NN+2*n+2*n22) )

N=Total Address BitsN=Total Address Bitsn=Total Cell Numbern=Total Cell Number

Capable of locating all Address Decoder Faults Capable of locating all Address Decoder Faults and Coupling Faults.and Coupling Faults.

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Testing Flash Memories 28

Flash Memory Functional TestFlash Memory Functional Test

Walking 1/0 AlgorithmWalking 1/0 AlgorithmMemory is filled with 0s (or 1s) except for the baseMemory is filled with 0s (or 1s) except for the base--cell,cell,which contains a 1 (or 0). The basewhich contains a 1 (or 0). The base--cell walks through cell walks through the whole array and all cells except the basethe whole array and all cells except the base--cell are read, cell are read, after all other cells also the baseafter all other cells also the base--cell is read.cell is read.

0 0 0

0 1 0

0 0 0

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Testing Flash Memories 29

Flash Memory Functional TestFlash Memory Functional TestWalking 1/0 Algorithm (ContWalking 1/0 Algorithm (Cont’’d)d)

Step 1: for d:=0 to 1 doStep 1: for d:=0 to 1 dobeginbegin

for i:=0 to nfor i:=0 to n--1 do1 doA(iA(i):=d;):=d;

for basefor base--cell:=0 to ncell:=0 to n--1 do1 dobeginbegin

Step 2:Step 2: A(baseA(base--cell):=dcell):=d’’;;GotoGoto READREADA(baseA(base--cell):=d;cell):=d;

end;end;end;end;

Step 3: {READ}Step 3: {READ}beginbeginfor cell:=0 to nfor cell:=0 to n--1 do1 dobeginbegin

if (if (A(cellA(cell)<>d) then output ()<>d) then output (““Error at cellError at cell””, cell);, cell);end;end;if (if (A(baseA(base--cell)<>dcell)<>d’’) then output () then output (““Error at cellError at cell””, cell);, cell);

endend

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Testing Flash Memories 30

Flash Memory Functional TestFlash Memory Functional Test

Test Coverage of Walking 1/0 AlgorithmTest Coverage of Walking 1/0 AlgorithmAll Address Decoder Faults are detected and located.All Address Decoder Faults are detected and located.All SAF will be located because the baseAll SAF will be located because the base--cell iscell iswritten and read with 0 and 1.written and read with 0 and 1.All Transient Faults are located because the baseAll Transient Faults are located because the base--cell make transitions after which it is read. cell make transitions after which it is read.

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Testing Flash Memories 31

Flash Memory Functional TestFlash Memory Functional Test

Walking 1/0 Algorithm (ContWalking 1/0 Algorithm (Cont’’d)d)Test length=2*(2Test length=2*(2NN+2*n+n+2*n+n22) )

N=Total Address BitsN=Total Address Bitsn=Total Cell Numbern=Total Cell Number

Capable of locating all Address Decoder Faults Capable of locating all Address Decoder Faults and Coupling Faults.and Coupling Faults.

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Testing Flash Memories 32

Flash Memory Functional TestFlash Memory Functional Test

Sliding Diagonal AlgorithmSliding Diagonal AlgorithmDesigned as a shorter alternative to GALPAT, it Designed as a shorter alternative to GALPAT, it uses a diagonal of base cells instead of a singleuses a diagonal of base cells instead of a singlebase cell.base cell.Cells on the diagonal are used because each cell Cells on the diagonal are used because each cell has a different row and column address,has a different row and column address,simultaneously checking the row and column simultaneously checking the row and column decoder.decoder.The algorithm writes a diagonal of 1s to a backThe algorithm writes a diagonal of 1s to a back--ground of 0s. All cells are read, after which theground of 0s. All cells are read, after which thediagonal is shifted.diagonal is shifted.

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Sliding Diagonal Algorithm (ContSliding Diagonal Algorithm (Cont’’d)d)Repeat the process until every cells are on the Repeat the process until every cells are on the diagonal.diagonal.The whole sequence is then done again with The whole sequence is then done again with inverted data.inverted data.

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

0 0 1 0

0 0 0 1

1 0 0 0

0 1 0 0

First DiagonalFirst Diagonal Third DiagonalThird Diagonal

Flash Memory Functional TestFlash Memory Functional Test

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Testing Flash Memories 34

Sliding Diagonal Algorithm (ContSliding Diagonal Algorithm (Cont’’d)d)For d:=0 to 1 doFor d:=0 to 1 doBeginBegin

Write d to all nonWrite d to all non--diagonal cells;diagonal cells;Write dWrite d’’ to all diagonal cells;to all diagonal cells;For For diagdiag:=0 to maxcolumn:=0 to maxcolumn--1 do1 doBeginBegin

{READ: read all cells}{READ: read all cells}for i:=0 to maxrowfor i:=0 to maxrow--1 do1 dobeginbegin

A(i,diag+iA(i,diag+i) :=d) :=d’’;;A(i,diag+i+1):=d;A(i,diag+i+1):=d;

end.end.end;end;

end; end;

Flash Memory Functional TestFlash Memory Functional Test

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Testing Flash Memories 35

Flash Memory Functional TestFlash Memory Functional Test

Test Coverage of Sliding Diagonal AlgorithmTest Coverage of Sliding Diagonal AlgorithmNot all Address Decoder Faults will be detectedNot all Address Decoder Faults will be detectedsince faults on cells on the same diagonal maysince faults on cells on the same diagonal maymask each other.mask each other.All SAF and Transient Faults are detected andAll SAF and Transient Faults are detected andlocated, since every cell is written when it belocated, since every cell is written when it be--comes part of the diagonal followed by read action.comes part of the diagonal followed by read action.Both transitions occur with inverted data.Both transitions occur with inverted data.Not all Coupling Faults will be detected, becauseNot all Coupling Faults will be detected, becauseall diagonal cells are written consecutively.all diagonal cells are written consecutively.

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Testing Flash Memories 36

Flash Memory Functional TestFlash Memory Functional Test

Sliding Diagonal Algorithm (ContSliding Diagonal Algorithm (Cont’’d)d)Test length=2*(n+nTest length=2*(n+n1/21/2*(n+2n*(n+2n1/21/2))))

n=Total Cell Numbern=Total Cell Number

Less test coverage compared with GALPATLess test coverage compared with GALPATMore efficientMore efficient

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Testing Flash Memories 37

Flash Memory Flash Memory Parametric TestParametric Test

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Testing Flash Memories 38

Flash Memory Parametric TestFlash Memory Parametric Test

Purpose of Parametric TestPurpose of Parametric TestCharacterization Test:Characterization Test:

To determine the exact value of a DC or AC parameter To determine the exact value of a DC or AC parameter at which a device fails.at which a device fails.

Go/Go/NoGoNoGo Test (Production Test)Test (Production Test)To determine whether a device meets its specifications.To determine whether a device meets its specifications.

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Testing Flash Memories 39

Flash Memory Parametric TestFlash Memory Parametric Test

Classification of Parametric TestClassification of Parametric TestDC Parametric TestDC Parametric Test

Contact testContact testPower consumption testPower consumption testLeakage testLeakage testThreshold testThreshold testOutput drive current testOutput drive current testOutput short current testOutput short current test

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Testing Flash Memories 40

Flash Memory Parametric TestFlash Memory Parametric Test

Classification of Parametric TestClassification of Parametric TestAC Parametric TestAC Parametric Test

Test for rise and fall timesTest for rise and fall timesTest for setup and hold timesTest for setup and hold timesTest for measuring delay timesTest for measuring delay timesTest for access timeTest for access timeSpeed testsSpeed tests

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Testing Flash Memories 41

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Contact TestContact TestTo ensure that the tester is in contact with theTo ensure that the tester is in contact with thedevice, also checks for opens and shorts of thedevice, also checks for opens and shorts of thedevice pins. Done as the first test.device pins. Done as the first test.

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Testing Flash Memories 42

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Contact Test (ContContact Test (Cont’’d)d)Set all pins to 0VSet all pins to 0VForce a forward biasing current Force a forward biasing current IIbb through thethrough thediodes; typical value:100ua<= diodes; typical value:100ua<= IIbb <=250ua.<=250ua.Measure the voltage Measure the voltage VVbbatat the pin:the pin:

VVbb<0.1V<0.1V (short)(short)0.1V<=0.1V<=VVbb<=1.5V<=1.5V(normal)(normal)VVbb>1.5V>1.5V (open)(open)

VccVcc=0V=0V

GndGnd

To internal circuitTo internal circuitDriveDrive

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Testing Flash Memories 43

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Power Consumption TestPower Consumption TestMeasuring the maximum current through the Measuring the maximum current through the device while the power supply voltage device while the power supply voltage VinVin is at its is at its specified value.specified value.

Static Power Consumption TestStatic Power Consumption TestTo determine the worstTo determine the worst--case power consumption while thecase power consumption while theinputs have a steady logical value.inputs have a steady logical value.

Dynamic Power Consumption TestDynamic Power Consumption TestTo measure the worstTo measure the worst--case power consumption while thecase power consumption while thedevice is operational.device is operational.

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Testing Flash Memories 44

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Leakage TestLeakage TestCMOS inputs and CMOS inputs and tristatedtristated outputs should be conoutputs should be con--sideredsidered as open circuits; in reality both appear asas open circuits; in reality both appear asa high impedance. The amount of worsta high impedance. The amount of worst--case case current drawn is called leakage.current drawn is called leakage.

Input LeakageInput LeakageTristateTristate LeakageLeakage

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Testing Flash Memories 45

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Leakage TestLeakage TestInput Leakage Test:Input Leakage Test:

Force input pin a voltage and measure the currentForce input pin a voltage and measure the current

TristateTristate Leakage Test:Leakage Test:Measure the Measure the tristatedtristated output with PMU.output with PMU.

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Testing Flash Memories 46

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Threshold TestThreshold TestDetermine the maximum input voltage at whichDetermine the maximum input voltage at whichthe device will switch from high to low. (Vthe device will switch from high to low. (VILIL))Determine the minimum input voltage at whichDetermine the minimum input voltage at whichthe device will switch from low to high. (Vthe device will switch from low to high. (VIHIH))

0V0V VccVccVVILIL VVIHIH

Switching AreaSwitching AreaLogic 0Logic 0 Logic 1Logic 1

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Testing Flash Memories 47

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Output Drive Current TestOutput Drive Current TestThe purpose is to ensure the device can hold itsThe purpose is to ensure the device can hold itsspecified output voltage level while driving thespecified output voltage level while driving thespecified current.specified current.This test is done by forcing the output voltage This test is done by forcing the output voltage and measure the current.and measure the current.

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Testing Flash Memories 48

Flash Memory Parametric Test (DC)Flash Memory Parametric Test (DC)

Output Short Current TestOutput Short Current TestThe purpose is to verify the drive capability of theThe purpose is to verify the drive capability of theoutput drivers.output drivers.Set output pin to 1, the output voltage of theSet output pin to 1, the output voltage of thePMU is forced to 0V and measure the output PMU is forced to 0V and measure the output current.current.

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Testing Flash Memories 49

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Introduction to AC Parametric TestIntroduction to AC Parametric TestTiming measurement.Timing measurement.The purpose is to ensure the changes in outputThe purpose is to ensure the changes in outputvalues occur at the right time.values occur at the right time.

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Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)Classification of AC Parametric TestClassification of AC Parametric Test

Rise and fall time measurement:Rise and fall time measurement:Check the speed with which an output signal can changeCheck the speed with which an output signal can changestate.state.

Setup and hold time measurement:Setup and hold time measurement:Tests for race conditions between input signals.Tests for race conditions between input signals.

Delay time measurement:Delay time measurement:Tests for the delay time between the input stimulus andTests for the delay time between the input stimulus andoutput response.output response.

Speed measurement:Speed measurement:Measure the time interval between the application ofMeasure the time interval between the application ofinput stimuli and their response. Test the speed of theinput stimuli and their response. Test the speed of thedevicedevice

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Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Test for Rise and Fall TimesTest for Rise and Fall Times

Rise TimeRise Time Fall TimeFall Time

VOHVOH

VOLVOL

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Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Setup and Hold TimesTests for Setup and Hold TimesSetup time:Setup time:

The amount of time the input data is required to be The amount of time the input data is required to be present before the edge of the control input occurs.present before the edge of the control input occurs.

Hold time:Hold time:The amount of time the input data has to remainThe amount of time the input data has to remainvalid after the edge of the control input has occurred.valid after the edge of the control input has occurred.

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Testing Flash Memories 53

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Setup and Hold Times (ContTests for Setup and Hold Times (Cont’’d)d)

Setup TimeSetup Time

Hold TimeHold Time

Input DataInput Data

Control SignalControl Signal

50% Point50% Point 50% Point50% Point

50% Point50% Point

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Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Delay TimesTests for Delay TimesMeasures the length of the time interval betweenMeasures the length of the time interval betweeninput and the output.input and the output.TTPHL:PHL:

Propagation delay from the 50% of the input voltagePropagation delay from the 50% of the input voltageuntil the output low voltage Vuntil the output low voltage VOL.OL.

TTPLH:PLH:

Propagation delay from the 50% of the input voltagePropagation delay from the 50% of the input voltageuntil the output high voltage Vuntil the output high voltage VOH.OH.

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Testing Flash Memories 55

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Delay Times (ContTests for Delay Times (Cont’’d)d)

TTPHLPHL

InputInput

OutputOutput

50% Point50% Point

VVOLOL

InputInput

50% Point50% Point

OutputOutput

VVOHOH

TTPLHPLH

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Testing Flash Memories 56

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Access TimesTests for Access TimesAssume the memory is functionally correct.Assume the memory is functionally correct.TTAA is defined as the longest of the two delay timesis defined as the longest of the two delay timesbetween the 50% point of the voltage on thebetween the 50% point of the voltage on theaddress lines and the H/L points of data outputs.address lines and the H/L points of data outputs.

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Testing Flash Memories 57

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Tests for Access Times (ContTests for Access Times (Cont’’d)d)

TTAA

AddressAddress

DataData

50% Point50% Point

Vol/VohVol/Voh

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Testing Flash Memories 58

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

Speed TestsSpeed TestsAssume the memory is functionally correct.Assume the memory is functionally correct.Measure the read/write time of memory locations.Measure the read/write time of memory locations.

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Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)SchmooSchmoo

A A SchmooSchmoo plot is used to visualize the interplot is used to visualize the inter--dependence of dependence of the two variables.the two variables.Used to identify safety margins, frequently used in Used to identify safety margins, frequently used in parapara--metric tests.metric tests.

5.50V

5.00V

4.50V

4.00V

3.50V

3.00V

210ns 180ns 150ns 120ns 90ns 60ns 30ns 0ns

VccVcc

TTREADREAD

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Typical Read Timing SpecificationTypical Read Timing Specification(AMD Am29F010B)(AMD Am29F010B)

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

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Typical Program Timing SpecificationTypical Program Timing Specification(AMD Am29F010B)(AMD Am29F010B)

Flash Memory Parametric Test (AC)Flash Memory Parametric Test (AC)

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Flash Memory Flash Memory Reliability TestReliability Test

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Flash Memory Reliability TestFlash Memory Reliability TestProduction Test HierarchyProduction Test Hierarchy

Production TestProduction Test

Wafer Level Test Reliability Test Final Test

Wafer Electrical Test Circuit Probe Initial Class test

Temp Acceleration Current/Voltage Accelerate

Quality Assurance

Temp Cycle Burn-in

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Flash Memory Reliability TestFlash Memory Reliability TestProduction Test FlowProduction Test Flow

Wafer TestWafer Test Package TestPackage Test(Final Test)(Final Test)

Quality AssuranceQuality Assurance

Reliability TestReliability Test

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Reliability Test PurposesReliability Test PurposesTo ensure that the circuit will perform its statedTo ensure that the circuit will perform its statedfunctions under given operating conditions for atfunctions under given operating conditions for atleast a specific period of lifetime.least a specific period of lifetime.The screening process selects chips with superior The screening process selects chips with superior reliability and rejects those which potentially will reliability and rejects those which potentially will fail early during operation.fail early during operation.

Flash Memory Reliability TestFlash Memory Reliability Test

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Reliability and Failure RateReliability and Failure RateReliability of a system may be stated in terms of Reliability of a system may be stated in terms of system failure rate or Mean Time Between Failures.system failure rate or Mean Time Between Failures.MTBF (Mean Time Between Failures)MTBF (Mean Time Between Failures)

For a constant failure rateFor a constant failure rateMTBF=1/R (R is the failure rate)MTBF=1/R (R is the failure rate)

FIT (Failure Unit)FIT (Failure Unit)Failure per unit timeFailure per unit time1 FIT=one failure in 101 FIT=one failure in 109 9 device hoursdevice hours

Flash Memory Reliability TestFlash Memory Reliability Test

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Reliability and Failure Rate (ContReliability and Failure Rate (Cont’’d)d)

Flash Memory Reliability TestFlash Memory Reliability Test<

Failu

re R

ate>

<Time>

Infant Mortality Normal Life Wear-Out

1K Hours 10-25 Years

Depends on the maturity of the manufacturingand packaging processes

Burn-In

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Reliability Failure MechanismsReliability Failure MechanismsChip Related FailuresChip Related Failures

Dopant diffusionDopant diffusionIonic movementIonic movementOxide contaminationOxide contaminationDielectric breakdownDielectric breakdownMetal voidingMetal voidingMetal interconnect crackingMetal interconnect cracking

Flash Memory Reliability TestFlash Memory Reliability Test

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Reliability Failure Mechanisms (ContReliability Failure Mechanisms (Cont’’d)d)Assembly Related FailuresAssembly Related Failures

Mounting voidsMounting voidsThermal mismatchingThermal mismatchingMetal stress relaxationMetal stress relaxationOxidationOxidation

Flash Memory Reliability TestFlash Memory Reliability Test

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Reliability Failure Mechanisms (ContReliability Failure Mechanisms (Cont’’d)d)Operation Induced FailuresOperation Induced Failures

ElectromigrationElectromigrationHot carriersHot carriersElectrostatic dischargeElectrostatic discharge

Flash Memory Reliability TestFlash Memory Reliability Test

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Reliability Test ClassificationReliability Test ClassificationPressure Cooker Test (PCT)Pressure Cooker Test (PCT)Temperature Cycle Test (TCT)Temperature Cycle Test (TCT)Thermal Shock Test (TST)Thermal Shock Test (TST)Temperature, Humidity Bias Test (THB)Temperature, Humidity Bias Test (THB)Highly Accelerated Stress Test (HAST)Highly Accelerated Stress Test (HAST)High Temperature Operating Life Test (HTOL)High Temperature Operating Life Test (HTOL)Low Temperature Operating Life Test (LTOL)Low Temperature Operating Life Test (LTOL)High Temperature Storage (HTS)High Temperature Storage (HTS)

Flash Memory Reliability TestFlash Memory Reliability Test

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Pressure Cooker TestPressure Cooker TestTo assess the ability of a product to withstandTo assess the ability of a product to withstandsevere temperature and humidity conditions.severe temperature and humidity conditions.Test Conditions:Test Conditions:

Soaking the samples for 168 hours at 121 deg C,Soaking the samples for 168 hours at 121 deg C,100% RH, and 2 100% RH, and 2 atmatm..

Flash Memory Reliability TestFlash Memory Reliability Test

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Temperature Cycle TestTemperature Cycle TestDetermine the ability of samples resist extremely low andDetermine the ability of samples resist extremely low andhigh temperatures and their ability to withstand cyclicalhigh temperatures and their ability to withstand cyclicalexposures to there conditions.exposures to there conditions.Test Conditions:Test Conditions:

Flash Memory Reliability TestFlash Memory Reliability Test

Mil Std 883, Method 1010 Specs :Mil Std 883, Method 1010 Specs :

-- Must be conducted for a minimum of 10 cyclesMust be conducted for a minimum of 10 cycles-- Condition A: Condition A: --55 (+0/55 (+0/--10) deg C to 85 (+10,10) deg C to 85 (+10,--0) deg C0) deg C-- Condition B: Condition B: --55 (+0/55 (+0/--10) deg C to 125 (+15,10) deg C to 125 (+15,--0) deg C 0) deg C -- Condition C: Condition C: --65 (+0/65 (+0/--10) deg C to 150 (+15,10) deg C to 150 (+15,--0) deg C 0) deg C -- Condition D: Condition D: --65 (+0/65 (+0/--10) deg C to 200 (+15,10) deg C to 200 (+15,--0) deg C 0) deg C -- Condition E: Condition E: --65 (+0/65 (+0/--10) deg C to 300 (+15,10) deg C to 300 (+15,--0) deg C0) deg C-- Condition F: Condition F: --65 (+0/65 (+0/--10) deg C to 175 (+15,10) deg C to 175 (+15,--0) deg C", 0) deg C", -- Total Transfer Time <= 1 minuteTotal Transfer Time <= 1 minute-- Total Dwell Time >= 10 minutes Total Dwell Time >= 10 minutes --Specified Temp reached in <= 15 minutesSpecified Temp reached in <= 15 minutes

JEDEC JESD22JEDEC JESD22--A104A104--A Specs :A Specs :

-- Recommended for lot acceptance screen : 10 cycles Recommended for lot acceptance screen : 10 cycles -- Recommended for qualification : 1000 cycles Recommended for qualification : 1000 cycles -- Condition A: Condition A: --55 (+0/55 (+0/--10) deg C to 85 (+10,10) deg C to 85 (+10,--0) deg C 0) deg C -- Condition B: Condition B: --55 (+0/55 (+0/--10) deg C to 125 (+10,10) deg C to 125 (+10,--0) deg C 0) deg C -- Condition C: Condition C: --65 (+0/65 (+0/--10) deg C to 150 (+10,10) deg C to 150 (+10,--0) deg C 0) deg C -- Condition D: Condition D: --65 (+0/65 (+0/--10) deg C to 200 (+10,10) deg C to 200 (+10,--0) deg C 0) deg C -- Condition F: Condition F: --65 (+0/65 (+0/--10) deg C to 175 (+10,10) deg C to 175 (+10,--0) deg C 0) deg C -- Condition G: Condition G: --40 (+0/40 (+0/--10) deg C to 125 (+10,10) deg C to 125 (+10,--0) deg C 0) deg C -- Condition H: Condition H: --55 (+0/55 (+0/--10) deg C to 150 (+10,10) deg C to 150 (+10,--0) deg C 0) deg C -- Total Transfer Time <= 1 minute Total Transfer Time <= 1 minute -- Total Dwell Time >= 10 minutes Total Dwell Time >= 10 minutes -- Specified Temp reached in <= 15 minutes Specified Temp reached in <= 15 minutes

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Thermal Shock TestThermal Shock TestDetermine the resistance of the part to sudden Determine the resistance of the part to sudden changes in temperature.changes in temperature.

The parts undergo a specified number of cycles, whichThe parts undergo a specified number of cycles, whichstart at ambient temperature.start at ambient temperature.Then expose the parts to an extremely low temperature.Then expose the parts to an extremely low temperature.After a short while, the parts are exposed to an After a short while, the parts are exposed to an extreextre--melymely high temperature.high temperature.

Flash Memory Reliability TestFlash Memory Reliability Test

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Thermal Shock Test (ContThermal Shock Test (Cont’’d)d)Test Conditions:Test Conditions:

Flash Memory Reliability TestFlash Memory Reliability Test

Mil Std 883, Method 1011 Specs :Mil Std 883, Method 1011 Specs :

-- Must be conducted for a minimum of 15 cyclesMust be conducted for a minimum of 15 cycles-- Condition A: 0 (+2/Condition A: 0 (+2/--10) deg C to 100 (+10/10) deg C to 100 (+10/--2) deg C2) deg C-- Condition B: Condition B: --55 (+0/55 (+0/--10) deg C to 125 (+10,10) deg C to 125 (+10,--0) deg C0) deg C-- Condition C: Condition C: --65 (+0,65 (+0,--10) deg C to 150 (+10,10) deg C to 150 (+10,--0) deg C0) deg C-- Total Transfer Time < 10 secondsTotal Transfer Time < 10 seconds-- Total Dwell Time > 2 minutesTotal Dwell Time > 2 minutes-- Specified Temp reached in < 5 minutes Specified Temp reached in < 5 minutes

JEDEC JESD22JEDEC JESD22--A106A106--A Specs :A Specs :

-- Must be conducted for a minimum of 15 cyclesMust be conducted for a minimum of 15 cycles-- Condition A: Condition A: --40 (+0/40 (+0/--30) deg C to 85 (+10/30) deg C to 85 (+10/--0) deg C0) deg C-- Condition B: Condition B: --0 (+2/0 (+2/--10) deg C to 100 (+10,10) deg C to 100 (+10,--2) deg C2) deg C-- Condition C: Condition C: --55 (+0,55 (+0,--10) deg C to 125 (+10,10) deg C to 125 (+10,--0) deg C0) deg C-- Condition D: Condition D: --65 (+0,65 (+0,--10) deg C to 150 (+10,10) deg C to 150 (+10,--0) deg C0) deg C-- Total Transfer Time < 10 secondsTotal Transfer Time < 10 seconds-- Total Dwell Time > 2 minutesTotal Dwell Time > 2 minutes-- Specified Temp reached in < 5 minutesSpecified Temp reached in < 5 minutes

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Temperature, Humidity, Bias TestTemperature, Humidity, Bias TestTo accelerate metal corrosion, particularly that ofTo accelerate metal corrosion, particularly that ofthe metallization on the die surface.the metallization on the die surface.Test Conditions:Test Conditions:

1000 hours at 85 deg C, 85% RH, with bias applied to1000 hours at 85 deg C, 85% RH, with bias applied tothe device.the device.

Flash Memory Reliability TestFlash Memory Reliability Test

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Highly Accelerated Temperature Stress TestHighly Accelerated Temperature Stress TestTo shorten the THB test.To shorten the THB test.Take 96Take 96--100 hours.100 hours.Test Conditions:Test Conditions:

130 deg C and 85% RH with bias for 96130 deg C and 85% RH with bias for 96--100 hours.100 hours.

Flash Memory Reliability TestFlash Memory Reliability Test

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Highly Accelerated Operating Life TestHighly Accelerated Operating Life TestDetermine the reliability of devices under operationDetermine the reliability of devices under operationat high temperature conditions over an extendedat high temperature conditions over an extendedperiod of time.period of time.Concerned with wearConcerned with wear--out failures.out failures.Test Conditions:Test Conditions:

Flash Memory Reliability TestFlash Memory Reliability Test

Mil Std 883Mil Std 883, Method 1005 Specs :, Method 1005 Specs :

-- generally 1000 hours min. at 125 deg C generally 1000 hours min. at 125 deg C -- max. rated max. rated TcTc or Ta < 200 deg C (Class B) or Ta < 200 deg C (Class B) -- max. rated max. rated TcTc or Ta < 175 deg C (Class S) or Ta < 175 deg C (Class S) -- Condition A : steadyCondition A : steady--state, reverse bias state, reverse bias -- Condition B : steadyCondition B : steady--state, forward bias state, forward bias -- Condition C : steadyCondition C : steady--state, power/reverse bias state, power/reverse bias -- Condition D : steadyCondition D : steady--state, parallel excitation state, parallel excitation -- Condition E : steadyCondition E : steady--state, ring oscillator state, ring oscillator -- Condition F : steadyCondition F : steady--state, temp.state, temp.--acceleratedaccelerated

Other HTOL Conditions (depending on use) :Other HTOL Conditions (depending on use) :

-- Ta=125C, 1000H, max Ta=125C, 1000H, max PdisPdis-- Ta=150C, 500H, max Ta=150C, 500H, max PdisPdis-- 125C<125C<TjTj<150C, 1000H, max <150C, 1000H, max PdisPdis-- 150<150<TjTj<175C, 500H, max <175C, 500H, max PdisPdis-- Ta=125C, 1000H, Ta=125C, 1000H, DynDyn, max , max PdisPdis-- Ta=150C, 500 H, Ta=150C, 500 H, DynDyn, max , max PdisPdis-- 125C<125C<TjTj<150C, 1000 H, <150C, 1000 H, DynDyn, max , max PdisPdis-- 150<150<TjTj<175C, 500 H, <175C, 500 H, DynDyn, max , max PdisPdis-- Ta=125C, 120H, max Ta=125C, 120H, max PdisPdis

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Low Temperature Operating Life TestLow Temperature Operating Life TestDetermine the reliability of devices under low temDetermine the reliability of devices under low tem--peratureperature conditions over an extended period of time.conditions over an extended period of time.Check for hot carrier effects, a commonly Check for hot carrier effects, a commonly encounencoun--teredtered failure mechanism accelerated by high voltage failure mechanism accelerated by high voltage and low temperature.and low temperature.Test Conditions:Test Conditions:

Maximum temperature: Maximum temperature: --10 deg C10 deg CElectrical testing must be performed within 96 hoursElectrical testing must be performed within 96 hoursafter the bias to the device has been removed.after the bias to the device has been removed.

Flash Memory Reliability TestFlash Memory Reliability Test

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High Temperature Storage TestHigh Temperature Storage TestDetermine the effect on devices of longDetermine the effect on devices of long--term storage term storage at elevated temperatures without any electricalat elevated temperatures without any electricalstresses applied.stresses applied.The purpose is to assess the longThe purpose is to assess the long--term reliability of term reliability of devices under high temperature conditions.devices under high temperature conditions.

Flash Memory Reliability TestFlash Memory Reliability Test

Summary of industrySummary of industry--standard HTS conditions: standard HTS conditions: 1000 hours at 150 deg C.1000 hours at 150 deg C.Mil Std 883, Method 1008, Stabilization Bake Specs :Mil Std 883, Method 1008, Stabilization Bake Specs :

-- storage at a high temperature for a specified durationstorage at a high temperature for a specified duration-- Test Condition A : 75 deg C / 24 hours minimumTest Condition A : 75 deg C / 24 hours minimum-- Test Condition B : 125 deg C / 24 hours minimumTest Condition B : 125 deg C / 24 hours minimum-- Test Condition C : 150 deg C / 24 hours minimumTest Condition C : 150 deg C / 24 hours minimum-- Test Condition D : 200 deg C / 24 hours minimumTest Condition D : 200 deg C / 24 hours minimum-- Test Condition E : 250 deg C / 24 hours minimumTest Condition E : 250 deg C / 24 hours minimum-- Test Condition F : 300 deg C / 24 hours minimumTest Condition F : 300 deg C / 24 hours minimum-- Test Condition G : 350 deg C / 24 hours minimumTest Condition G : 350 deg C / 24 hours minimum-- Test Condition H : 400 deg C / 24 hours minimum Test Condition H : 400 deg C / 24 hours minimum

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Thank You!Thank You!