testing in ics

7/29/2019 Testing in ICs

1/201

ELEN654

ATM

ECEN654YieldandTestin

g

Version0.99

993(BetaLecture)


2/201

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ATM

First..Tes

tingBasics

VLSIre

alizationprocess

Verifica

tionandtest

Idealandrealtests

Costso

ftesting

Roleso

ftesting

AmodernVLSIdevice-

system-on-a-chip

Lecture

outline

PartI:Introductiontote

sting

PartII:Testmethods

PartIII:Designfortestability


3/201

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ATM

VLSIR

ealization

Process

Determinerequirements




Writespecifica

tions

Writespecifica

tions

Writespecifica

tions

Writespecifica

tions

DesignsynthesisandVerification




Fabrication

Fabrication

Fabrication

Fabrication

Manufacturingtest

Manufacturingtest

Manufacturingtest

Manufacturingtest

Chipstocu

stomer

Chipstocu

stomer

Chipstocu

stomer

Chipstocu

stomer

Customersneed

Customersneed

Customersneed

Customersneed

Te

stdevelopm

ent

Te

stdevelopm

ent

Te

stdevelopm

ent

Te

stdevelopm

ent


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Definitio

ns

Designsyn

thesis:GivenanI/Ofunction,deve

lopaprocedureto

manufactureadeviceusing

knownmaterialsandprocesses.

Verification

:Predictiveanaly

sistoensurethatthesynthesizeddesign,

whenmanufactured,willperformthegivenI/O

function.

Test:Amanufacturingstept

hatensuresthatthephysicaldevic

e,

manufacturedfromthesynth

esizeddesign,hasnomanufacturing

defect.


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ATM

Verificationvs.Te

st

Verifiescorrectnessofdesign.

Performedb

ysimulation,

hardwareem

ulation,orformal

methods.

Performedo

ncepriorto

manufacturing.

Responsible

forqualityof

design.

Verifiesco

rrectnessofmanufactured

hardware.

Two-partp

rocess:

1.Test

generation:softwareprocess

execute

donceduringdesign

2.Test

application:electricaltestsapplied

tohardware

Testapplic

ationperformedon

every

manufactu

reddevice.

Responsib

leforqualityofdevices.


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ProblemsofIdealTests

Idealte

stsdetectalldefectsproducedinthemanufacturing

process.

Idealte

stspassallfunctionallygooddevic

es.

Veryla

rgenumbersand

varietiesofpossibledefectsneedtobe

tested.

Difficulttogeneratetests

forsomerealde

fects.Defect-orie

nted

testing

isanopenproble

m.


7/201

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ATM

RealTests

Based

onanalyzablefau

ltmodels,whichmaynotmaponr

eal

defects

.

Incomp

letecoverageofmodeledfaultsdu

etohighcomplexity.

Somegoodchipsarerejected.Thefraction(orpercentage

)of

suchchipsiscalledtheyieldloss.

Somebadchipspasstests.Thefraction(orpercentage)ofbad

chipsa

mongallpassing

chipsiscalledthedefectlevel.


8/201

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ATM

TestingasFilter

Process

Fabric

ated

Fabric

ated

Fabric

ated

Fabric

ated

chips

chips

chips

chips

Goodc

hips

Goodc

hips

Goodc

hips

Goodc

hips

Defectivechips

Defectivechips

Defectivechips

Defectivechips

Prob(good

Prob(good

Prob(good

Prob(good)=y

)=y

)=y

)=y

Prob(bad

Prob(bad

Prob(bad

Prob(bad)=1

)=1

)=1

)=1----yyyy

Prob(pass

Prob(pass

Prob(pass

Prob(passtest)

=high

test)

=high

test)

=high

test)

=high

Prob(fail

Prob(fail

Prob(fail

Prob(failtest)

=high

test)

=high

test)

=high

test)

=high

Prob(f

ail

Prob(f

ail

Prob(f

ail

Prob(f

ail

test)

=low

test)

=low

test)

=low

test)

=low

Pro

b(p

ass

Pro

b(p

ass

Pro

b(p

ass

Pro

b(p

ass

test

)=

low

test

)=

low

test

)=

low

test

)=

low

Mo

stly

Mo

stly

Mo

stly

Mo

stly

good

good

good

good

ch

ips

ch

ips

ch

ips

ch

ips

Mostly

Mostly

Mostly

Mostly

b

ad

b

ad

b

ad

b

ad

chips

chips

chips

chips


9/201


10/201

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DesignforTestab

ility(DFT

)

DFTreferstohardwaredesignstylesoradde

d


d


d


d

hardware

thatreduce

stestgenerationcomp

lexity.

hardware

thatreduce

stestgenerationcomp

lexity.

hardware

thatreduce

stestgenerationcomp

lexity.

hardware

thatreduce

stestgenerationcomp

lexity.

Motivation:Testgene

rationcomplexityincre

ases

Motivation:Testgene


ases

Motivation:Testgene


ases

Motivation:Testgene


ases

exponentiallywiththesizeofthe

circuit.


circuit.


circuit.


circuit.

Logic

Logic

Logic

Logic

blockA

blockA

blockA

blockA

Lo

gic

Logic

Lo

gic

Logic

blockB

blockB

blockB

blockB

PIPIPIPI

POPOPOPO

Test

Test

Test

Test

input

input

input

input

Test

Test

Test

Test

output

output

output

output

Int.Int.Int.Int.busbusbusbus

Example:

TesthardwareappliesteststoblocksA

Example:


Example:


Example:


andBand

tointernal

bus;avoids

testgenera

tion

andBand

tointernal

bus;avoids

testgenera

tion

andBand

tointernal

bus;avoids

testgenera

tion

andBand

tointernal

bus;avoids

testgenera

tion

forcombinedAandB

blocks.

forcombinedAandB

blocks.

forcombinedAandB

blocks.

forcombinedAandB

blocks.


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Costof

ManufacturingTestingin

2000AD

0.5-1.0

GHz,analoginstruments,1,024dig

italpins:ATEpurchase

price

=$1.2M+1,024x$3,0

00=$4.272M

Runnin

gcost(five-yearlineardepreciation)

=Depreciation+Maintenance+Operation

=$0.854M+$0.085M+$0.5M

=$1.439M/year

Testco

st(24hourATEoperation)

=$1.439M/(365x24x

3,600)

=4.5cents/second


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RolesofTesting

Detection:Determination

whetherornotthedeviceundertest

(DUT)hassomefault.

Diagno

sis:Identification

ofaspecificfault

thatispresenton

DUT.

Device

characterization:

Determinationan

dcorrectionofer

rorsin

design

and/ortestprocedure.

Failure

modeanalysis(FMA):Determinationofmanufacturing

processerrorsthatmay

havecauseddefe

ctsontheDUT.


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AMod

ernVLSI

Device

System

-on-a-chip(SOC)

DSPDSPDSPDSPcorcorcorcoreeee

RAM

RAMRAM

RAMROM

ROM

ROM

ROM

Inter

Inter

Inter

Inter----

facefacefacefacelogic

logic

logic

logic

Mixed

Mixed

Mixed

Mixed----

signal

signal

signal

signal

Codec

Codec

Codec

Codec

Data

Data

Data

Data

terminal

terminal

terminal

terminal

Transmission

Transmission

Transmission

Transmission

medium

medium

medium

medium


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Stuffwe

willcover

Basicco

nceptsanddefinitions

Testpro

cessandATE

Testeconomicsandprod

uctquality

Faultmodeling


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Morethi

ngs

Logicandfaultsimulation

Testabilitymeasures

Combin

ationalcircuitATPG

Sequen

tialcircuitATPG

Memory

test

Analogtest

Delayte

standIDDQtest

Scande

sign

BIST

Bounda

ryscanandanalo

gtestbus

System

testandcore-baseddesign


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VLSITestingPr

ocessand

Equipme

nt

Motivation

TypesofTesting

TestSpecificationsandPlan

TestProgram

ming

TestDataAnalysis

AutomaticTe

stEquipment

ParametricTesting

Summary


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Motivati

on

NeedtounderstandsomeAutomaticTestEquipment(AT

E)

technolog

y

Influen

ceswhattestsare

possible

Seriousanalogmeasurementlimitationsathighdigitalfrequ

encyor

intheanalogdomain

Needtounderstandcapa

bilitiesfordigital

logic,memory,an

danalog

testin

System-on-a-Chip

(SOC)technology

Needtou

nderstandparam

etrictesting

Usedtotakesetup,hold

timemeasuremen

ts

Useto

computeVIL,VIH,VOL,VOH,tr,tf,td,IOL,IOH,IIL,IIH


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Typesof

Testing

Verificationtesting,characterizationtesting,ordesign

debug

Verifiescorrectnesso

fdesignandofte

stprocedureusually

requirescorrectionto

design

Manufacturingtesting

Fac

torytestingofallmanufacturedchip

sforparametricf

aults

and

forrandomdefec

ts

Acceptancetesting(incominginspection)

Use

r(customer)tests

purchasedpartstoensurequality


19/201


20/201

ELEN654

ATM

AutomaticTestEq

uipmentCompone

nts

Consis

tsof:

Pow

erfulcomputer

Pow

erfulDigitalSignalProcessor(DSP

)foranalogtesting

Tes

tProgram(written

inhigh-levellang

uage)runningon

the

com

puter

Pro

beHead(actually

touchesthebareorpackagedchipto

performfaultdetectio

nexperiments)

ProbeCardorMembr

aneProbe(containselectronicsto

measuresignalsonc

hippinorpad)


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DiagnosticsandReasoning

Ferociouslyexpensive

Mayco

mprise:

Sca

nningElectronMi

croscopetests

Brig

ht-Litedetectionofdefects

Electronbeamtesting

Artificialintelligence(expertsystem)methods

Rep

eatedfunctionalt

ests


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Characte

rizationT

est

Worst-casetest

Choo

setestthatpasses/failschips

Selec

tstatisticallysign

ificantsampleofc

hips

Repeattestforeveryco

mbinationof2+e

nvironmentalvariables

Plotr

esultsinSchmoo

plot

Diagn

oseandcorrectd

esignerrors

Continuethroughoutpro

ductionlifeofc

hipstoimprove

designa

ndprocesstoin

creaseyield


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Schmo

oPlot


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Manufac

turingTest

Determineswhetherma

nufacturedchip

meetsspecs

Mustco

verhigh%ofm

odeledfaults

Mustminimizetesttime

(tocontrolcost)

Nofaultdiagnosis

Testseverydeviceonc

hip

Testatspeedofapplica

tionorspeedgu

aranteedbysup

plier


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Burn-inorStressT

est

Process

:

Subjectchipstohightemperature&over-voltagesupply,w

hile

runningproductiontes

ts

Catches

:

Infan

tmortalitycases

thesearedamagedchipsthatwillfailin

thefirst2daysofoperationcausesbad

devicestoactuallyfail

beforechipsareshippedtocustomers

Freakfailuresdeviceshavingsamefailuremechanismsa

s

reliab

ledevices


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Typesof

ManufacturingTests

Wafersortorprobetes

tdonebefore

waferisscribed

and

cutintochips

Includestestsitecharacterizationspe

cifictestdevices

are

che

ckedwithspecific

patternstomeasure:

Gatethreshold

Polysiliconfieldthreshold

Polysheetresista

nce,etc.

Packageddevicetests


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Sub-type

sofTests

Parametricmeasures

electricalprope

rtiesofpin

electro

nicsdelay,voltages,currents,

etc.fastandc

heap

Functionalusedtocoververyhigh%

ofmodeledfaults

testev

erytransistoran

dwireindigital

circuitslonga

nd

expensivemaintopic

oftutorial


29/201

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TwoDifferentMeaningsofFunctiona

l

Test

ATEan

dManufacturingWorldanyve

ctorsappliedto

coverhigh%offaultsduringmanufacturingtest

Autom

aticTest-Pattern

GenerationWorldtestingwith

verificationvectors,wh

ichdeterminew

hetherhardware

matchesitsspecificationtypicallyha

velowfaultcoverage

(1sockets

Addm

oreinstruments

toATEtohandlemultipledevices

simultaneously

Usuallytest2or4DUT

Satatime,usuallytest32or64

memorychipsatatime

Limits:#instrumentsa

vailableinATE,

typeofhandling

equipm

entavailablefo

rpackage


45/201

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Electrica

lParametricTestin

g

TypicalTestProgr

am

1.

Prob

etest(wafersor

t)catchesgrossdefects

2.

Cont

actelectricaltes

t

3.

Func

tional&layout-r

elatedtest

4.

DCp

arametrictest

5.

ACp

arametrictest

Unacceptablevoltage/current/delayatpin

Unacceptabledevic

eoperationlimits


46/201

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DCPara

metricTe

sts

ContactTest

1.

Seta

llinputsto0V

2.

ForcecurrentIfbout

ofpin(expectIfb

tobe100to250A)

3.

Meas

urepinvoltageVpin.CalculatepinresistanceR

Contactshort(R=0

)

Noproblem

Pi

nopencircuited(Rhuge),IfbandVpinlarge


47/201

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PowerC

onsumptionTest

1.

Settemperaturetow

orstcase,open

circuitDUToutputs

2.

Mea

suremaximumd

evicecurrentdrawnfromsupplyICC

atspecifiedvoltage

ICC>70mA(fails)

4

0mA40A(ok)

S

hortcurrent

40

A(fails)


49/201

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OutputD

riveCurrentTest

1.

Ap

plyvectorforcingpinto0

2.

SimultaneouslyforceVOLvoltageandmeasureIOL

3.

Re

peatStep2forlogic1

IOL

1

>

1

>

1

Annualcosts

Annualcosts

Annualcosts

Annualcosts


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Econo

micsofDesignforTestability

(DFT)

Consid

erlife-cyclecos

t;DFTonchipm

ayimpactthec

osts

atboardandsystemle

vels.

Weigh

costsagainstbenefits

Costexamples:reducedyieldduetoare

aoverhead,yieldlo

ssdue

tonon-functionaltests

Benefitexamples:R

educedATEcostdu

etoself-test,inexpensive

alternativestoburn-intest


69/201

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Benefits

andCost

sofDFT

Des

ign

Des

ign

Des

ign

Des

ign

and

test

and

test

and

test

and

test

+

/

+/

+

/

+/----

+

/

+/

+

/

+/----

+

/

+/

+

/

+/----

Fabri

Fabri

Fabri

Fabri----

cation

cation

cation

cation

++++ ++++ ++++

Ma

nuf

Ma

nuf

Ma

nuf

Ma

nuf....

Test

Test

Test

Test ---- ---- ----

Level

Level

Level

Level

Chips

Chips

Chips

Chips

Boards

Boards

Boards

Boards

System

System

System

System

Maintenance

Maintenance

Maintenance

Maintenance

test

test

test

test ----

Diagnosis

Diagnosis

Diagnosis

Diagnosis

andrepair

andrepair

andrepair

andrepair

---- ----

Service

Service

Service

Service

inte

rruption

inte

rruption

inte

rruption

inte

rruption

----

+

Costincreas

e

+

Costincreas

e

+

Costincreas

e

+

Costincreas

e

----

Costsaving

Costsaving

Costsaving

Costsaving

+/+/+/+/----Costincreas

emaybalanceco

streduction

Costincreas

emaybalanceco

streduction

Costincreas

emaybalanceco

streduction

Costincreas

emaybalanceco

streduction


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Summar

y

Econo

micsteachesus

howtomaketh

erighttrade-offs.

Itcombinescommons

ense,experienc

eandmathemat

ical

metho

ds.

Theov

erallbenefit/cos

tratiofordesign,testand

manuf

acturingshould

bemaximized;o

neshouldselec

tthe

moste

conomicdesign

overthecheapestdesign.

ADFT

ortestmethodshouldbeselect

edtoimproveth

e

productqualitywithm

inimalincreaseincostduetoarea

overhe

adandyieldlos

s.


71/201

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YieldAnalysis&ProductQuality

Yieldandmanufacturingcost

Clustereddefectyieldformula

Yieldimprovement

Defectlevel

Testdataanalys

is

Example:SEMA

TECHchip

Summary


72/201

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VLSIChipYield

Amanufa

cturingdefectisafinitechipareawithelectrically

malfunctioningcircuitrycau

sedbyerrorsinthefabricationpro

cess.

Achipwithnomanufacturingdefectiscalledagoodchip.

Fraction(orpercentage)ofgoodchipsproducedinamanufacturing

processiscalledtheyield.

Yieldisdenoted

bysymbolY.

Costofa

chip:

Costoffabricatingandte

stingawafer

Co

stoffabricatingandte

stingawafer

Costoffabricatingandte

stingawafer

Co

stoffabricatingandte

stingawafer

----------------------------------------------------------------

---------------------------------------------------------------

-

----------------------------------------------------------------

---------------------------------------------------------------

-----------------

YieldxNumberofchipsite

sonthewa

fer


sonthewa

fer


sonthewa

fer


sonthewa

fer


73/201

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ClusteredVLSIDefects

Wafer

Wafer

Wafer

Wafer

Defects

Defects

Defects

Defects

Fa

ultychips

Fa

ultychips

Fa

ultychips

Fa

ultychips

Goodchips

Goodchips

Goodchips

Goodchips

Uncluste

red

Uncluste

red

Uncluste

red

Uncluste

reddefects

defects

defects

defects

Waferyield

=12/22=0.55

Waferyield

=12/22=0.55

Waferyield

=12/22=0.55

Waferyield

=12/22=0.55

Clus

tereddefects

(VLSI)

Clus

tereddefects

(VLSI)

Clus

tereddefects

(VLSI)

Clus

tereddefects

(VLSI)

Wafe

ryield=17/22=0.77

Wafe

ryield=17/22=0.77

Wafe

ryield=17/22=0.77

Wafe

ryield=17/22=0.77


74/201

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YieldParameters

Defectdensity(d)=Averagenumberofde

fectsperunitofc

hiparea

Chipare

a(A)

Clusterin

gparameter()

Negative

binomialdistribu

tionofdefects,

p(x)=Prob(numberof

defectso

nachip=x)

((((++++xxxx)

(

)

(

)

(

)

(AdAdAdAd////))))xxxx

====-------------

-------------

-------------

-------------....----------------------

----------------------

----------------------

----------------------

xxxx!!!!(((()

(1+

)

(1+

)

(1+

)

(1+AdAdAdAd////))))++++

xxxx

where

where

where

where

istheg

ammafunction

istheg

ammafunction

istheg

ammafunction

istheg

ammafunction

=0=0=0=0,,,,pppp((((xxxx))))isade

ltafunction

(max.clustering)

isade

ltafunction

(max.clustering)

isade

ltafunction

(max.clustering)

isade

ltafunction

(max.clustering)

====

,,,,pppp((((xxxx))))isPo

issondistr.

(noclustering)

isPo

issondistr.

(noclustering)

isPo

issondistr.

(noclustering)

isPo

issondistr.

(noclustering)


75/201

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YieldEquation

YYYY====Prob

Prob

Prob

Prob(zerode

fectonachip)=

(zerode

fectonachip)=

(zerode

fectonachip)=

(zerode

fectonachip)=pppp(0)(0)(0)(0)

YYYY=(1

+

=(1

+

=(1

+

=(1

+AdAdAdAd////

))))

Exa

mple:

Exa

mple:

Exa

mple:

Exa

mple:AdAdAdAd=

1.0,

=

1.0,

=

1.0,

=

1.0,

=0.5,=0.5,=0.5,=0.5,

YYYY=0.58

=0.58

=0.58

=0.58

Uncl

ustered

Unclustered

Uncl

ustered

Unclustereddefects:

defects:

defects:

defects:

====

,Y,Y,Y,Y=e=e=e=e----AdAdAdAd

Ex

ample:

Ex

ample:

Ex

ample:

Ex

ample:AdAdAdAd=

1.0,

=

1.0,

=

1.0,

=

1.0,

=

,

=

,

=

,

=

,YYYY=0.37

=0.37

=0.37

=0.37

too

pessimistic

too

pessimistic

too

pessimistic

too

pessimistic

!!!!


76/201

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DefectLe

velorRejectRatio

Defectlevel(DL)istheratiooffaultychip

samongthechip

s

thatpasstests.

DLism

easuredasparts

permillion(ppm).

DLisa

measureofthee

ffectivenessoftests.

DLisa

quantitativemeasureofthemanufacturedproduct

quality.ForcommercialV

LSIchipsaDLgreaterthan500ppm

iscons

ideredunaccepta

ble.


77/201

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DeterminationofDL

Fromfieldreturndata:C

hipsfailinginthe

fieldarereturned

to

themanufacturer.Then

umberofreturnedchipsnormalize

dto

onemillionchipsshippedistheDL.

Fromtestdata:Faultcoverageoftestsan

dchipfalloutrate

are

analyzed.Amodifiedyieldmodelisfitted

tothefalloutdata

to

estimatetheDL.


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79/201

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DefectLevel

YYYY((((TTTT))))----YYYY(1)(1)(1)(1)

DLDLDLDL((((TTTT)=)=)=)=

--------------------

--------------------

--------------------

--------------------

Y(Y(Y(Y(TTTT))))

((((++++TAfTAfTAfTAf

))))

=

1

=

1

=

1

=

1------------------------

--------------------

--------------------

--------------------

((((++++AfAfAfAf

))))

Where

Where

Where

WhereTTTTisthe

faultcover

ageoftests

,

isthe

faultcover

ageoftests

,

isthe

faultcover

ageoftests

,

isthe

faultcover

ageoftests

,

AfAfAfAfistheaveragenumberoffaultsonthe

istheaveragenumberoffaultsonthe



chipofarea

chipofarea

chipofarea

chipofareaAAAA,,,,isthefaultclustering

isthefaultclustering



parameter.

parameter.

parameter.

parameter.AfAfAfAf

andandandandaredeterminedby

aredeterminedby

aredeterminedby

aredeterminedby

testdataanalysis.

testdataanalysis.

testdataanalysis.

testdataanalysis.


80/201

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Example:SEMAT

ECHChip

BusinterfacecontrollerASICfabricatedandtestedatIBM,

Burling

ton,Vermont

116,000equivalent(2-inputNAND)gates

304-pin

package,249I/O

Clock:40MHz,someparts50MHz

0.45C

MOS,3.3V,9.4m

mx8.8mmarea

Fullscan,99.79%faultc

overage

Advant

est3381ATE,18

,466chipstested

at2.5MHztestclock

DataobtainedcourtesyofPhilNigh(IBM)


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83/201


84/201

ELEN654

ATM

ComputedDL

Stuck

Stuck

Stuck

Stuck----atfaultcoverag

e(%)

atfaultcoverag

e(%)

atfaultcoverag

e(%)

atfaultcoverag

e(%)

Defectlevelin Defectlevelin Defectlevelin Defectlevelinppmppmppmppm

237,700

237,700

237,700

237,700ppmppmppmppm((((YYYY=76.23%)

=76.23%)

=76.23%)

=76.23%)


85/201

ELEN654

ATM

Summar

y

VLSIyielddependsontwop

rocessparameters,defectdensity

(d)and

clusteringp

arameter()

Yielddrops

aschipareaincr

eases;lowyieldmeanshighcost

Faultcover

agemeasuresthetestquality

Defectleve

l(DL)orrejectratioisameasureo

fchipquality

DLcanbedeterminedbyan

analysisoftestd

ata

Forhighqu

ality:DL

testing in ics

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