texas instruments ti solutions for environmental extremes · enhanced product portfolio enhanced...
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Texas Instruments
TI Solutions for Environmental Extremes
Sree Addepalli Marketing Lead // Space & Enhanced Products
Hot links:
Enhanced Product Portfolio
Enhanced products: Orderables
Enhanced products: Quality matrix
Commercial Q100 EP QMLQ QMLV
Packaging Plastic Plastic Plastic Ceramic Ceramic
Single Controlled Baseline No No Yes Yes Yes
Bond Wires Au/Cu Au/Cu Au Al Al
Is Pure Sn used? Yes Yes No No No
Guaranteed Rad
Performance No No No No Yes
Typical Temperature Range -40ºC - 85ºC -40ºC - 125ºC -55ºC - 125ºC (majority) -55ºC - 125ºC -55ºC - 125ºC
Extra Qualification and
Process Monitors No Yes Yes Yes Yes
Life Test Per Wafer Lot No No No No Yes
Specification Management No No VID SMD SMD
Comments Low cost and high volume.
Tailored for commercial and
applications
High reliability for automotive
applications. No single baseline
control. Flow uses matte Sn and Cu
bond wires.
Similar flow compared to Q100.
Controlled baseline ensures more
homogenous performance across
lots.
Ceramic military grade parts
released to a MIL spec. Good for
temperature extremes and long
term dormant storage
Radiation assured space grade
parts release to a MIL spec. Meant
for long lifetime, high reliability
missions
TI’s full range of solutions TI is growing and investing in all of these product areas
*Space EP currently in definition
Quality / Reliability / Cost
What defines an Enhanced Product?
• Single Controlled Baseline flow
• Gold (Au) bond wires
• Vendor Item drawing
• Roughened leadframe and best available material set
• 250 Hour HAST
• Tin content < 97%
• Reliability Reports on ti.com
3
Failure mechanisms and Enhanced Product (EP) mitigation
Failure mechanism EP flow mitigation tactic
Obsolescence – requires redesign
Designed for long lifetime applications (15+ years) +
obsolescence mitigation potential (sequestered die bank,
resurrections)
Copper Bond wire – high stress can cause bond
weakness/failure
Au bond wire only as part of EP definition
Variability + traceability failure – specs can vary
part to part
Controlled Baseline and material set (single fab/A/T) +
Reliability reports + VIDs
Tin Whiskers – during high stress usage No pure or matte tin used >97%
Delamination – can occur during stress testing Rugged leadframe, improved die attach, better mold
compounds (more expensive but more rugged options)
EP qualification matrix Enhanced Products New Device Qualification Matrix (Note that qualification by similarity (“qualification family”) per JEDEC JESD47 is allowed)
Description Condition Sample Size Used/Rejects Lots Required Test Method
Electromigration Maximum Recommended Operating Conditions N/A N/A Per TI Design Rules
Wire Bond Life Maximum Recommended Operating Conditions N/A N/A Per TI Design Rules
Electrical Characterization TI Data Sheet 15 3 N/A
Electrostatic Discharge Sensitivity HBM
3 units/voltage N/A EIA/JESD22-A114
CDM EIA/JESD22-C101
Latch-up Per Technology 5/0 3 EIA/JESD78
Physical Dimensions TI Data Sheet 5/0 1 EIA/JESD22- B100
Thermal Impedance Theta-JA on board Per Pin-Package N/A EIA/JESD51
Bias Life Test 125°C / 1000 hours or equivalent 45/0 3 JESD22-A108*
Biased Humidity 85°C / 85% / 1000 hours
77/0 3
JESD22-A101*
or or
Biased HAST 130°C / 85% / 96 hours JESD22-A110*
Extended Biased Humidity 85°C / 85% / 2600 hours (for reference) JESD22-A101*
or or 77/0 1
Extended Biased HAST 130°C / 85% / 250 hours (for reference) JESD22-A110*
Unbiased HAST 130°C / 85% / 96 hours 77/0 3 JESD22-A.118*
Temperature Cycle -65°C to +150°C non-biased for 500 cycles 77/0 3 JESD22-A104*
Solder Heat 260°C for 10 seconds 22/0 1 JESD22-B106
Resistance to Solvents Ink symbol only 12/0 1 JESD22-B107
Solderability Condition A (steam age for 8 hours) 22/0 1 ANSI/J-STD-002-92
Flammability Method A / Method B 5/0 1 UL-1964
Bond Shear Per wire size 5 units x 30/0 bonds 3 JESD22-B116
Bond Pull Strength Per wire size 5 units x 30/0 bonds 3 ASTM F-459
Die Shear Per die size 5/0 3 TM 2019
High Temp Storage 150 °C / 1,000 hours 15/0 3 JESD22-A103-A*
Moisture Sensitivity Surface Mount Only 12 1 J-STD-020-A*
*Precondition performed per JEDEC Std. 22, Method A112/A113
* Lines in green are either not done in Q100 or have less coverage in Q100
Enhanced Products (More than 750 EP Products)
6
DSP Microcontroller
32 EP Products
Logic 180+ EP Products
Clocks & Timing
6 EP Products
Interface 25+ EP Products
DAC 12 EP Products
ADC 17 EP Products
Amp 50+ EP Products
Amp
Sensing/AFE 5 EP Products
Switching Regulators 53 EP Products
LDOs 80 EP Products
DDR Solutions 2 EP Products
Isolation 4 EP Products
References 6 EP Products
Power Management
Complete System
End Equipment Block Diagrams
Avionics Defense Industrial Transportation Medical Phased Array Radar IMU Actuator Motor Control ECU
Supervisors & Sequencing 12 EP Products
Power
Concept
Data Converter Amplifiers Interface/Clocking Embedded
Processing
Recently
Released
In Development
TMS570LS3137-EP
16- and 32-bit Hercules RISC Flash
Microcontroller
AM3358-EP
Sitara™ Processor
TMS320F28377D-EP Delfino Dual-Core MCU
BGA and PTP
OPA2277-EP
High Precision
Operational Amplifier
OPA4277-EP
High Precision
Operational Amplifier
All roadmaps are subject to change based on market direction, resource limitations, etc.
*HIREL generally indicates part will be the same as an EP product without extended HAST or a V62 number
SN55HVD75-EP
3.3V, 20Mbps RS-485 with ESD Protection
TPS7A4001-EP
100V, 50mA, Single Output Low-Dropout
Linear Regulator
OPA2211-EP
Low Noise, Low Power, Precision Operational
Amplifier
OPA2171-EP
36V, Low Power, RRO, Operational Amplifier
Enhanced Products (EP) roadmap
2
01
6
20
17
2
01
8
AM5718-HIREL (760 FCBGA)
ARM® Cortex®-A15 Sitara Processor
MSP430FR5989-EP (64 VQFN)
16 MHz ULP Microcontroller with 128
KB FRAM
MSP430FR5739-EP Mixed Signal
Microcontroller with FRAM
DRV8842-EP 5A Brushed DC or Half-Bipolar Stepper Motor
Driver (PWM Ctrl)
ADS6444-EP Quad Channel, 14 Bit, 125/105/80/65 Msps Adc With Serial Lvds
Outputs
SN74LVTH16373-EP 3.3-V ABT 16-Bit
Transparent D-Type Latches With 3-State
Outputs
LMK04828-EP Ultra Low Jitter
Synthesizer and Jitter Cleaner
SN65LBC17xA-EP Quadruple RS-485 Differential Line
Receivers
ISO5852S-EP (16 SOIC) Reinforced Isolated IGBT
Gate Driver
TPS5426x-EP (10 VSON) 3.5V to 60V, 2.5A SWIFT
Converter
REF3425-EP 2.5V Low-Drift Low-
Power Small-Footprint Series Voltage Reference
ADS1278-EP Octal, 144kHz, 24 Bit Delta
Sigma, Simultaneous Sampling
TPS7A4701-EP (20 VQFN) 36-V, 1-A, 4.17-μVRMS,
RF LDO Voltage Regulator
TPS79901-EP (6 WSON) 200mA, Ultra-Low Noise, High PSRR Low Dropout
Linear Regulator
UCD90xx0-EP Power Supply Sequencer
and Monitor/Manager
TMS570LC4357-EP (337 NFBGA) Hercules MCU
TMS320F28035-EP Piccolo MCU
CDCM6208V1F-EP 2:8 Ultra Low Power, Low
Jitter Clock Generator, Pin Mode Variant F
OPA2356-EP 2.5V, 200MHz GBW, CMOS Dual Op Amp
DAC34H84-EP Quad-Channel, 16-Bit,
1.25-GSPS, 1x-16x Interpolating DAC
TLV3012-EP Nanopower, 1.8V, SOT23
Push-Pull Comparator with Voltage Reference
TPS549D22-EP 1.5V to 16V , 40A SWIFT
Step-Down Converter
TPS54318-EP 2.95V to 6V Input, 3A
Synchronous Step-Down SWIFT™ Converter
SN65HVD01-EP 3.3 V RS-485 with 1.65 V I/O Supply and Selectable
Data Rate
Motor Control
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Microcontroller (MCU)
SP
I, I2C
, U
AR
T,
CA
N,
US
B
200 MHz
32-bit
C28x CPU
1024 KB
Flash
TMS320F28377D-EP Dual-Core Delfino Microcontroller
designed for advanced closed-loop
control applications
Available today!
New!
200 MHz
32-bit
C28x CPU
200 MHz
CLA
200 MHz
CLA
Motor Controller with
integrated Current
Sense Amplifier
CAN Transceiver
RS422/485 Transceiver
RS 232 Driver/Receiver
DC/DC LDO
TPS54350-EP 4.5-V To 20-V Input 3-A Output
Synchronous Pwm Switcher
W/Integrated Fet
TPS7A7200-EP 2A, Single Output, Very Low Input,
Configurable Fixed (0.9 to 5.0V) Low-
Dropout Linear Regulator
Power FETs/
Darlingtons
Motor
Voltage/Shunt
Feedback ADC
THS1408-EP 2A, Single Output, Very Low Input,
Configurable Fixed (0.9 to 5.0V) Low-
Dropout Linear Regulator UC2625-EP
Brushless DC motor controller
integrates most of the functions
required for high-performance
brushless dc motor control into one
package
SN65HVD1050-EP
SN65HVD09-EP
MAX3232-EP
Isolated IGBT
Gate Driver
OPA2277-EP 10µV, 0.1µV/˚C, High-Precision, Low-
Power Operational Amplifier
Available today!
ISO5852S-EP High-CMTI 2.5-A/5-A Isolated IGBT,
MOSFET Gate Driver With Split
Outputs and Protection Features
Available today!
Current
Feedback
High Speed Signal Chain for Communication
Clocking
CLK
FPGA
SYSREF
LO
RF IF
ADC
CLK
ADC
TMP422-EP
Dig
ital In
terf
ace
LO
RF
FPGA
DDR DDR
Complex Mixer DDR Term
Memory Power
Signal Chain Power
Low Noise LDOs
FPGA/Processor Power
High Power Density DC/DC
Converter
DAC
DAC
TMP422-EP
ADS5463-EP 12-Bit, 500-MSPS Analog-to-Digital Converter
THS4271-EP Low Noise High Slew Rate Unity Gain
Stable Voltage Feedback Amplifier
DAC5687-EP 16-Bit, 500-MSPS
DAC5675-EP 14-Bit 400-Msps
TMP422-EP Dual Remote and Local Temperature
Sensor with N-Factor and Series-R
Correction
High Output Current LDOs
TPS55340-EP Integrated, 5-A 40-V Wide Input Range
Boost/SEPIC/Flyback DC-DC Regulator
TPS79901-EP 2.7- 6.5 VIN, 0.2A LDO
TPS7A4701-EP 36-V, 1-A, 4-μVRMS
TPS74401-EP 0.9 – 5.5 VIN, 3A LDO
New!
TPS51216-EP 2A Complete DDR2, DDR3 and DDR3L
Memory Power Solution
TPS51200-EP 3A Sink/Source DDR Termination
Regulator
THS4503-EP Wideband Low-Distortion Fully
Differential Amplifier
CDCLVP111-EP 1:10 with Selectable Input Clock Driver
LMK04828-EP Ultra Low-Noise JESD204B Compliant Clock
Jitter Cleaner
9
New!
New!
New!
Key Resources:
• EP Orderables List:
http://www.ti.com/pdfs/hirel/mltry/EP_Orderable_Release_List.pdf
• MSL Level Search: http://www.ti.com/packaging/docs/mslsearch.tsp
• Thermal Calculator:
http://www.ti.com/adc/docs/midlevel.tsp?contentId=76735&keyMatch=thermal%20c
alculator&tisearch=Search-EN-Everything
• Product Shelf Life Search: http://www.ti.com/quality/docs/productshelflife.tsp
• DPPM/FIT/MTBF estimator: http://www.ti.com/quality/docs/estimator.tsp
• Various Calculators: http://www.ti.com/lsds/ti/quality/reliability/calculators.page
• Material Content Search: http://www.ti.com/quality/docs/materialcontentsearch.tsp
• Send requests for missing reliability reports to [email protected]
Thanks for watching!
Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers in
TI’s E2E Community. Post in the High Reliability Forum today!
EP reliability reports on TI.com
• Traceability (FAB, assembly, test site)
• Packaging material
• Qualification test results
Material
Set
Material
Set
Material
Set
Material
Set
Wafer
Fab
Wafer
Fab
Wafer
Fab
Wafer
Fab
Commercial Flow
A/T Site A/T Site A/T Site A/T Site
Commercial products can be built in multiple FABs, A/T sites
and may use various material sets for each product build
Material Set
One Wafer
Fab
A/T Site
EP Flow
EP products are built in one FAB, one A/T site,
and use one material set for product build
Different fabs, material sets and AT sites can introduce variability over time.
This can cause changes in system performance for long-running programs.
Baseline Controlled Flow
HT Material Set
One Wafer
Fab/ HT Die
A/T Site
High Temp Plastic Flow
Quality and Temp Driven
HT products are built in one FAB, one AT site
and use one material set optimized for HT
The reliability of Cu bondwire has not been proven in mission critical applications, harsh
environments, or in applications where long term dormant storage (10 to 20 years) is
required. Munitions
Aircraft
Aerospace
Applications with extensive temp cycling
Applications with long term storage requirements
Potential risks identified by the industry include Bond integrity (Cu bonding to aluminum requires much tighter process controls and environments)1
Sporadic DPPM level corrosion due to mold compound interaction2
Bondwire neck breaks during temperature cycling (The coefficient of thermal expansion [CTE] of Cu is higher than
Au, resulting in a higher failure rate in the presence of delamination compared to Au)3
15
Sources: 1 Luke England and Tom Jiang. “Reliability of Cu Wire Bonding to Al Metallization”. Electronic Components and Technology Conference. 2007. 2 Hui Teng, et al. “Effect of Moisture and Temperature on Al-Cu Interfacial Strength”. International Conference on Electronic Packaging Technology & High Density Packaging, 2008. 3 Bart Vandevelde and Geert Willems. “Early fatigue failures in Cooper wire bonds inside packages with low CTE Green Mold Compounds”. 4th ESTC Conference. 2012, Amsterdam, The Netherlands.
Au vs. Cu Bond Wire
Tin Whiskering
• When tin inside a package is subject to large internal or
external stress, it has the tendency to randomly crystallize
and extend like a tendril through a part
• This can cause short circuits if the tendrils reach another
surface.
• To avoid this issue, EP parts do not use pure tin anywhere in
the package or leadframe
• This is a well documented issue by many customers,
including NASA, who had satellites stop functioning due to tin
whiskers
• The NASA website has examples of tin whiskering issues in
many different end equipments, including radios, GPS
modules, circuit breakers, power distribution equipment, etc. 16
FAB / TEST FLOW CHANGES: ASSY FLOW CHANGES:
EP Release Flow Chart – BOM/Flow Changes
17
A. NEW EP PRODUCTS RELEASE IN ROUGHENED
LEADFRAMES (EXCEPTIONS SHOULD BE
IDENTIFIED & RISK APPROVED AT PPR ) .
B. CHANGE LEADFRAMES AS NEEDED TO HAVE
NIPDAU FINISH OR SNPB.
C. BGA PACKAGES NEED TO CHANGE TO SNPB
SOLDER BALLS, FLIP CHIP NEEDS INTERNAL
BUMP CHANGED TO SNPB AS WELL.
D. CHANGE TO GOLD WIRE.
E. USE HIGH RELIABILITY BOM – HIGH TEMP MOLD
AND MOUNT COMPOUND COMPLEMENTING
ROUGHENED LEADFRAMES FOR LESS DELAM.
F. ADD 100% RELFOW AND SAMPLE XRAY IN
ASSEMBLY FLOW TO CATCH GROSS DEFECTS
LIKE WIRE SWEEP & CRACK DIES ETC.
G. ASSEMBLY SITE CHANGES TO COMPLY WITH
CURRENT ROAD MAP STRATEGY. SOMETIMES
NEED EXTRA QUAL.
H. ENSURE SINGLE BOM IN ATSS.
1. PLAN TO RUN ATLEAST 2 TEMPS ( ROOM & HOT).
VERIFY EXISTING TEST HARDWARE & HANDLER
IS CAPABLE TO RUN FOR THESE TEMPS. COLD
TEMP IS NVA FOR MOST A/T.
2. RELEASE SEPARATE TEST PROGRAM FOR
HIREL TO HAVE CONTROL AND AVOID TEST
REMOVAL FOR TIME OPTIMISATION.
3. RELEASE SEPARATE HIREL DIE IN FAB TO
BASE LINE LOCK OR MAINTAIN
MASKS/RETICLE REV AS IS EVEN WHEN
COMMERCIAL CHANGES DIE.
4. TESTER CONVERSIONS TO NON LEGACY
INCASES WHERE ORIGINAL DEVICE IS STILL
RUNNING ON LEGACY TEST PLATFORM AND NO
PLANS TO CONVERT.
5. ALIGN WITH ROAD MAP TEST SITES AND
RELEASE IN NEW SITES AS NEEDED.
REVIEW ASSY &
TEST FLOW.
CHARACTERIZATION STEPS: ADD TESTS IN ATE FOR FOLLOWING:
EP Flow Chart – Validation: ATE / Bench Characterization
18
A. COVERING ROC CORNERS LIKE VOLTAGE &
FREQUENCY CORNERS FOR CHAR / PROD
PROGRAM.
B. MISSING MIN-MAX PARAMETERS (NPT IS
ALLOWED BUT NEEDS STATISTICAL PROOF PER
QSS) AEO DOES TEST TIME REDUCTIONS AND
MOST OF PROGRAMS HAVE OPTIMISED
COVERAGE BASED ON HISTORIC FALL OUT.
C. PLAN FOR TESTS NEEDED TO CREATE GRAPH
TEMP EXTESNIONS.
D. SPEC PARAMETERS WHERE BENCH DATA OR
CHAR DATA IS NOT AVAILABLE.
E. BEST PRACTICES AT TIME OF RELEASE –
EXAMPLE SPC, ROBUSTNESS P2P LEAKAGE
CHECK AT END OF PROGRAM, DIB DIAGNOSTICS
ETC.
F. FIX TEST INSTABILITY OR LOW YIELD ISSUES,
EXAMPLES PROBE TRIM SHIFTS LEADING TO
TARGET CHANGES , FRR FAILS THAT WILL FAIL
CURRENT ERTP SYSTEM FOR RELEASE.
1. PERFORM CHAR ON 30 UNITS POPULATED
FROM 3 LOTS ACROSS TEMPS.
2. CPK CONSIDERATIONS: HIREL HAS BEEN
FOLLOWING LIMIT OF 1.67 FOR CPK. DATA
ANALYSIS TO BE PERFORMED AND ALL
PARAMETERS FAILING THIS SHOULD BE
JUSTIFIED PER QSS.
3. NPT: NON PRODUCTION TESTED
PARAMETERS WILL NEED TO HAVE CPK OF
FROM BENCH / ATE CHAR AND PROPER
EXPLANATION PROVIDED FOR NOT TESTING.
4. NVA: NON VALUE ADDED TEMP INSERTION
REMOVAL NEEDS TO HAVE GUARDBAND STUDY
DONE WITH CHAR DATA. LIMITS AT ROOM TEMP
WILL BE TIGHTENED TO SHOW A GUARDBAND
CPK OF 1 FOR BEST CONFIDENCE ON THIS GB
TECHNIQUE.
5. DO GRADUAL TEMP INCREASE ON A SMALL
SUBSET OF UNITS FOR REGENERATING GRAPHS TO FULL TEMP RANGE.
Regenerate VVCM
per latest Data sheet
For the validation
section only.