text book: silicon vlsi technology fundamentals, …• bunny suits, gloves, air showers, covered...

Manufacturing, Cleaning, Gettering - Chapter 4

Text Book:Silicon VLSI Technology

Fundamentals, Practice and Modelingg

Authors: J. D. Plummer, M. D. Deal, and P. B. Griffina d G

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

© 2000 by Prentice HallUpper Saddle River NJ


Chapter 4• A three tiered approach to control unwanted

impurities in silicon– Clean Rooms

• Minimize particles in the environment– Wafer Cleaningg

• Minimize particles on the wafers– Gettering

• Minimize the effect of particles in the waferMinimize the effect of particles in the wafer


© 2000 by Prentice HallUpper Saddle River NJ2


FRONT END PROCESSES - CLEANING, LITHOGRAPHY, OXIDATIONION IMPLANTATION, DIFFUSION, DEPOSITION AND ETCHING

• Over the next several weeks, we’ll study front end processes individually.• Cleaning belongs to front end processes and is an important part of fabrication

Reference ITRS Roadmap for Front End Processes



• Reference - ITRS Roadmap for Front End Processes (http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_FEP.pdf ).


Defect and Impurities•• Importance of unwanted Importance of unwanted

impurities increases with impurities increases with shrinking geometries of shrinking geometries of devicesdevicesdevices. devices.

•• 75% of the yield loss is 75% of the yield loss is due to defects caused by due to defects caused by particles (1/2 of the min particles (1/2 of the min feature size)feature size)feature size)feature size)

•• Wafer localized light Wafer localized light scatterersscatterers (LLS) is a (LLS) is a starting wafer teststarting wafer test

C l i i dC l i i d•• Crystal originated Crystal originated (45(45--150nm) particles 150nm) particles (COP) ~1,000Å=void (COP) ~1,000Å=void with with SiOSiOxx --> affect gate > affect gate oxide integrity (GOI)oxide integrity (GOI)g y ( )g y ( )

•• --> anneal in H> anneal in H22 --> oxide > oxide decomposes and surface decomposes and surface reconstructs! & oxide reconstructs! & oxide precipitates from deep precipitates from deep



p p pp p pdepth in Si.depth in Si.

Yield > 90% at the end requires > 99% @ each step


Wafer Cleaning• Surface films and doped regions must not be

significantly attacked.• Photoresist strip and particle removal typical• Room air and process equipment delivered particles

Significant elements that cause severe problems in silicon– Significant elements that cause severe problems in silicon include: organics, metals (Fe, Au, Cu, etc.) and alkali ions (Na, K, etc.)

Particles

PhotoresistAu

Cu

Fe

ParticlesNa

SiO2 or other thin films

AuFe

Interconnect Metal

N, P



Silicon Wafer


Example Sensitivity• Example #1: MOS transistor gate threshold shift

2ε qN (2φ ) qQMOS VTH is given by

VTH = VFB + 2φ f +

2εSqN A (2φ f )CO

+qQ M

CO(1)

– QM is the mobile charge density (number of charges per cm2) of Na+ and K + in the gate oxide

If 10 h 0 1 l V hif b d bIf tox = 10 nm, then a 0.1 volt Vth shift can be caused by QM = 6.5 x 1011 cm-2 (< 0.1% monolayer or 10 ppm in the oxide).

– Prevented MOS technologies initially from being important commercially!




Example Sensitivity• Example #2: MOS DRAM

– Storage of charge based on minimal charge leakage in time.• Refresh required to maintain charges after a technology defined period of time. g gy

– Dominated by Shockley, Reed Hall (SRH) recombination (intermediate impurity related energy levels).

• σ is the trap cross sectional area, (10-15cm-2) vth is the minority carrier thermal l it (107 / ) d N i th d it f tvelocity (107 cm/sec), and Nt is the density of traps.

• Deep-level traps (Cu, Fe, Au etc.) Pile up at the surface where the devices are located.

BIT LINE

WORDLINE • Refresh time of several msec

requires a generation lifetime of

1- - - -- --- -- -- STORED

CHARGEON MOS

CAPACITOR

ACCESSMOS

TRANSISTOR

sec 1001R μ≈

⋅⋅=

tth Nvστ (2)

• This requires Nt ≈ 1012 cm-3 or



q t≈ 0.02 ppb (see text).


Example: The Role of Surface Cl i i P iCleaning in Processing

Oxide thickness

[Å]

Residual contaminants, layers affect kinetics of processes.

S f ff tSurface effects are very important (MORE) in scaled down devices




2003 ITRS Front End Processes

Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology N ode (half pi tch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

DRAM Bits/Chip (Sampli ng) 256M 512M 1G 4G 16G 32G 64G 128G 128G

MPU Trans istors/Chip (x106) 550 1100 2200 4400 8800 14,000

Critical D efec t Si ze 125 nm 90 nm 90 nm 90 nm 90 nm 90 nm 65 nm 45 nm 45 nm

Starting Wafe r Particle s (cm-2 ) <0.35 <0.18 <0.09 <0.09 <0.05 <0.05

Starting Wafe r Total Bulk Fe (cm-3 ) 3x1010 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010

Metal Atom s on Wafer Surface

After Clean ing (cm-2 )

5x109 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010 1x1010

Particles on Wafe r Surface After 75 80 86 195 106 168

Clean ing (#/ wa fer)




ITRS 2007 Ed. Front End Processes




Clean Factories – Wafer Fab Facility• The wafer fabrication area “Clean Rooms” must

particle free.– Sources of particles

• Air (normal presence of particles) and Water• Machinery – particularly due to friction, metals• People – 5 to 10 million particles per minute, organic• Supplies – brought in to room for use• Processing

– Rooms and People• Clean room limited access, finger wall machine access• Bunny suits, gloves, air showers, covered faces/facemask• Glove box and robots

– Air handling• Positive air pressure, HEPA filters



p ,

11


Stanford’s CIS Clean Room• The 10,500 square feet clean room is vibration-

isolated from the rest of the building. Support equipment, such as chilled water, vacuum pumps,

i d id t t liair compressors, and acid waste neutralizers, are located in the basement. Corrosive and toxic gases are in a monitored gas area. Liquid gas storage tanks, emergency power generators, and a de-ionized water plant are outdoors.p

• Every 8 seconds, the entire air volume of this room is circulated out to large air ducts, like the meter-wide duct just behind the glass. From there the air flows up to the third floor, down through filters on the

d fl d th b k i t th lsecond floor, and then back into the clean room through the ceiling.

• People inside the room wear bunny suits to minimize the release of human particles into the air. The result is that each cubic foot of air has fewerThe result is that each cubic foot of air has fewer than 100 particles of size 500 nanometers (Class 100), much cleaner than the air in a hospital operating room.

• http://www-cis.stanford.edu/~marigros/CleanRoom.html



• http://snf.stanford.edu/Education/VirtualTour.html

12


Level 1 Contamination Reduction: Clean Factories

• Air quality is measured by the “class” of the facility.

o Less than X total particleso Less than X total particles greater than 0.5 um per cubic foot of air.

Factory environment is cleaned by:Factory environment is cleaned by:• HEPA filters (99.07% eff.)• Air recirculation (laminar >50 cm/sec)• Bunny suits for workers• Filtration of chemicals and gases• Manufacturing protocols



(Photo courtesy of Stanford Nanofabrication Facility.)


Wafer Cleaning• Remove particles, films such as photoresist, and any

other trace contaminants• Distinct processes

– Silicon wafer clean (frontend processes)Post metalization clean (backend processes)– Post metalization clean (backend processes)

• Frontend Wafer Cleaning based on RCA process– RCA was originally the Radio Corporation of America– Werner Kern developed the basic procedure in 1965 while

working for RCA.

• The RCA clean involves the following :The RCA clean involves the following :1. Removal of the organic contaminants (Organic Clean)2. Removal of thin oxide layer (Oxide Strip)3 R l f i i t i ti (I i Cl )



3. Removal of ionic contamination (Ionic Clean)

14


The RCA Clean• The first step (called SC-1, where SC stands for Standard Clean) is

performed with a 1:1:5 solution of NH4OH + H2O2 + H2O at 70º to 80º C for 10 minutes.for 10 minutes.

– This treatment oxidizes organic films and complexes Group IB and IIB metals as well as Au, Ag, Cu, Ni, Zn, Cd, Co, and Cr. The solution dissolves and regrows a thin native oxide layer on the silicon.

Th t t i h t i i i 1 50 l ti f HF + H2O t• The next step is a short immersion in a 1:50 solution of HF + H2O at 25º C

– Remove the thin oxide layer and some fraction of ionic contaminants.• Perform a DI rinsePerform a DI rinse.• The next step (called SC-2) is performed with a 1:1:6 solution of HCl +

H2O2 + H2O at 70º to 80º C for 10 minutes. – This treatment removes alkali ions and cations (AL, Fe, Mg) that form ( g)

NH4OH insoluble hydroxides in solutions like SC-1. In SC-2 they for soluble complexes. This solution also completes the removal of metal contaminants.

• Perform a DI rinse



Perform a DI rinse

15


Level 2 Contamination Reduction: Wafer Cleaning

120 - 150ÞC Strips organicsH2SO4/H2O2 120 150ÞC 10 min

Strips organics especially photoresist

Room T 1 min

Strips chemical oxide

2 4 2 21:1 to 4:1

HF/H2O 1:10 to 1:50

DI H2O Rinse Room T

80 - 90ÞC 10 min

Strips organics, metals and particles

NH4OH/H2O2/H2O 1:1:5 to 0.05:1:5

SC-1

• Organic Clean

• RCA clean is “standard

DI H2O Rinse Room T

80 - 90ÞC Strips alkali ionsHCl/H2O2/H2O

process” used to remove organics, heavy metals and alkali ions.

80 90ÞC 10 min

Strips alkali ions and metals

DI H2O Rinse Room T

1:1:6 SC-2



• Ultrasonic agitation is used to dislodge particles.

DI H2O Rinse Room T


De-Ionized (DI) Water• Clean water for silicon processing

• DI Water conductivity example:

DI water is necessary: H2O↔H++OH- with [H+]=[OH-]=6x10-13cm-3y 2 [ ] [ ]Diffusivity of : H+ ≈9.3x10-5cm2s-1 →µH+=qD/kT=3.59cm2V-1s-1

of : OH-≈5.3x10-5cm2s-1 → µOH-=qD/kT=2.04cm2V-1s-1

cmMOHHq OHH

Ω=+

=−+

−+ 5.18)][]([

1μμ

ρ

Distilled water is typically 10 uS/cm or 0.1 MΩ cm




Gettering• Removing trace elements from active transistor

locations by causing them to combine with defects in the silicon.– Active devices cover a very small portion of the silicon

volume, typically near one surface.yp y– Metals and alkali ions have very high diffusivity.– They tend to be easily captured either in regions with

mechanical defects or in regions which chemically trap them.mechanical defects or in regions which chemically trap them.

• For the alkali ions, gettering generally uses dielectric layers on the topside (PSG or barrier Si3N4 layers).

• For metal ions, gettering generally uses traps on the wafer backside (extrinsic) or in the wafer bulk (intrinsic).



(intrinsic).

18


Level 3 Contamination Reduction: Gettering

N bl

H 1.008

1

3 4Li Be B C N O F

He 4.003

Ne5 6 7 8 9 10

2

Period

1

2

I A

IIAV AIIIA IV A VIA VII A

Noble Gases

Deep Level Impurites in Silicon

Alkali Ions

11 12

19 20

Li 6.941

Be 9.012

Na 22.99

Mg 24.31

K 39 10

Ca 40 08

Sc 44 96

Ti 47 88

V 50 94

Cr 51 99

Mn 54 94

Fe 55 85

Co 58 93

Ni 58 69

Cu 63 55

Zn 65 39

21 22 23 24 25 26 27 28 29 30

B10.81

Al 26.98

Ga 69 72

C12.01

Si 28.09

Ge 72 59

N14.01

P 30.97

As 74 92

O16.00

S 32.06

Se 78 96

F19.00

Cl 35.45

Br 79 90

Ne20.18

Ar 39.95

Kr 83 80

13 14 15 16 17 18

31 32 33 34 35 36

2

3

4

IIIBIV

BI B IIBV

BVI

BVII

BVIII

Deep Level Impurites in Silicon

39.10 40.08

Rb 85.47

Cs 132.9

Sr 87.62

Ba 137.3

37 38

55 56

44.96 47.88 50.94 51.99 54.94 55.85 58.93 58.69 63.55 65.39

Y 88.91

Zr 91.22

Nb 92.91

Mo 95.94

Tc 98

Ru 101.1

Rh 102.9

Pd 106.4

Ag 107.9

Cd 112.4

39 40 41 42 43 44 45 46 47 48

La 138.9

Hf 178.5

Ta 180.8

W 183.9

Re 186.2

Os 190.2

Ir 192.2

Pt 195.1

Au 197.0

Hg 200.6

57 72 73 74 75 76 77 78 79 80

69.72

In 114.8

Tl 204.4

72.59

Sn 118.7

Pb 207.2

74.92

Sb 121.8

Bi 209.0

78.96

Te 127.6

Po 209

79.90

I 126.9

At 210

83.80

Xe 131.3

Rn 222

49 50 51 52 53 54

81 82 83 84 85 86

5

6

Fr 223

Ra 226

87 88 Ac 227.0

Unq 261

Unp 262

Unh 263

Uns 262

89 104 105 106 1077

allo

w D

onor

s

ow A

ccep

tors

lem

enta

l ic

ondu

ctor

sSh

a

Shal

lo ESe

mi

Elements for gettering:• Alkali Ions• Metals




Gettering• Steps:

1. Free elements from current Devices in near

PSG Layer

sites, making them mobile2. Diffuse through silicon to

desired sites

Devices in near surface region

Denuded Zone or Epi Layer

10 - 20 µm

3. Become trapped.

• Aalkali ions: dielectric layers on the topside (PSG or

Intrinsic Gettering

Region 500+ µ m

on the topside (PSG or barrier Si3N4 layers).

• Heavy metal ions: traps on the wafer backside (extrinsic) or in the wafer bulk (intrinsic).

Backside Gettering

Region



bulk (intrinsic).

20


Gettering• Diffusivity of various elements

– Diffuse as interstitials (they don’t easily fit in the lattice)(through wafer during normal dopant drive-in)( g g p )

– Dopants diffuse as a substitution

C1200 1100 1000 900 800

T (ÞC)

10 -8

10 -6

CrPt

Fe

AuI

Cu

InterstitialDiffusers

I Diffusivity

10 -4

m2

sec

-1)

14

10 -12

10 -10

AuS

Diffusers

Ti

y (c

m2

sec-

1 )

sivity

Diff

usiv

ity (c

m

10 -18

10 -16

10 -14

SiAs

B, P

Dopants

Diff

usiv

ity



10 -20

0.65 0.7 0.75 0.8 0.85 0.9 0.95 11000/T (Kelvin)

p


Traps1100Outdiffusion

Precipitation Stacking V I

900

Precipitation gFault

V I

OI

OI

OI SiO2

500

700T e m p e r a t u r e Þ C

Time

Nucleation

OI Diffusion

[OI]

SiO2

OIOI

Time OI Diffusion2

1253.2exp13.0 −⎟⎠⎞

⎜⎝⎛−⋅= seccmeVDO

• “Trap” sites can be created by SiO2 precipitates (intrinsic gettering), or by backside damage (extrinsic gettering)

p ⎟⎠

⎜⎝ kTO

(extrinsic gettering).

• In intrinsic gettering, CZ silicon is used and SiO2precipitates are formed in the wafer bulk throughSiO precipitates (white dots) in bulk



p p gtemperature cycling at the start of the process.

SiO2 precipitates (white dots) in bulkof wafer.


Intrinsic Gettering: Oxide Precipitates

Precipitates (size) grow @ high T

Density of nucleation sites grow @ low T

Surface (top) has few defects

The largest & the most dense defects -> the most efficient gettering

Surface (top) has few defects.




MEASUREMENT METHODSMEASUREMENT METHODS




Measurement Methods• Clean factories = particle control

– Detect concentrations < 10/wafer of particles smaller than 0.1 µm

• Unpatterened wafers (blank)C t ti l i i– Count particles in microscope

– Laser scanning systems → maps of particles down to ≈ 0.2 µm(see MEMC video on laser inspection from Chapter 3)

• Patterned wafers– Optical system compares a die with a “known good reference”

die (adjacent die, chip design - its appearance) ( j , p g pp )– Image processing identifies defects (SEM)– Test structure (not in high volume manufacturing)




Test Structures

Trapped charge

Resistance CapacitanceTrapped charge

QT VTH change

Dielectric breakdown due to particles, metals etc.




Monitoring the Wafer Cleaning EfficiencyConcentrations of impurities determined by surface analysis

works with SEM He+ 1-3 MeVRutherford Back-scattering

Secondary Ion Mass Spectro-metry: O+ or Cs+

•Excite•Identify (unique atomic signature)•Count concentrations emitted

sputtering and mass analyses

•Count concentrations

Primary beam – e - good lateral resolution

Detected beam – e – good depth resolution and surface sensitivity

X-ray poor depth resolution and poor surface sensitivity



ions (SIMS) excellent

ions (RBS) good depth resolution, reasonable sensitivity (0.1 atomic%)


Electron Beam Emissions (1)

Inelastic collision with target electrons, which are then emitted from the solid

(as in SEM)

are then emitted from the solidElastic collision of incoming electrons with atoms (reflected back) ~ the same energy as for the incoming electronsg

~ 5 eV




If X Ray is at the input:

Electron Beam Emissions (2)If X-Ray is at the input:

• el. Emitted= X-ray Photoelectron Spectroscopy (XPS)

• X-ray emitted= X-ray Fluorescence (XRF)

AES scheme is for lighter elements (Z=33 as is crossover between Auger /AES and X-Ray/XES) Several

( )

XPS usually more dominant for lighter elements, XRF for heavier

g y ) SevekeV

The core electron energy levels

Several keV3 3

kicked out a core electron

Electron Microprobe

energy levels

12

12



X-Ray Electron SpectroscopyAuger Electron Spectroscopy

Manufacturing, Cleaning, Gettering - Chapter 4Monitoring of Gettering Through Device Properties and Dielectricp – n leakage, refresh time DRAM junction and dielectric breakdown, β of n-p-n

Material properties : τG(>>τR) in the bulk and on the surface emission↔capture

Device Properties and Dielectric

Photoconductive Decay Measurements

∆n=gopτG

•Carriers are generated due to light •Decrease resistivity•Recombine

)/exp()0()( Rtntn τ−Δ=Δ




Carrier Generation Lifetime

== +DL

inversion

t =10(NA /ni)τG

Deep Depletion - Return to Inversion via Carrier Generation (measure τG) and surface recombination (s)



p p ( G) ( )

Zerbst technique:

ddt

( CoxC

)2 → τG

ddt

( CoxC

)2 → s if plotted vs. (Cmin/C)-1

s=f(NST, σ) σ=Capture cross section

Manufacturing, Cleaning, Gettering - Chapter 4Lifetime Measurements: Open Circuit Voltage Decay

VD (t) = VD (0) − kT ln(erfc t )

t=0

≈0.7V

Voltage Decay

τ R

Diode switched from ON VD when carriers recombine

off

for t/τ>4

τR =kT/q

dVD /dtMeasurements include surface and

for t/τ>4

bulk recombination

Use also DLTS: identifies traps (Et) and concentrationsThermal or photoexcitation processes in voltage modulable space-charge region (Schottky Diode, p-n junction, MOS Capacitor)



Measured: capacitance, currents or conductance


Deep Level Transient Spectroscopy• An experimental tool for studying electrically active

defects (known as charge carrier traps) in semiconductors. – DLTS enables to establish fundamental defect parameters

and measure their concentration in the material. – Some of the parameters are considered as defect “finger

prints” used for their identifications and analysis.– identifies traps (Et) and concentrationsidentifies traps (Et) and concentrations– http://en.wikipedia.org/wiki/DLTS

• Thermal or photoexcitation processes in voltage d l bl h imodulable space-charge region

(Schottky Diode, p-n junction, MOS Capacitor)– Measured: capacitance, currents or conductance



p

13


MODELINGMODELING




Models and Simulation Goal

Computer Integrated Manufacturing (CIM)• Tools to monitor and control machines, to maintain

recipes, to control wafer throughput, and to improve operating efficiency (i.e. higher yields)

• Higher initial yields and shorter time to maturity.




Contamination and Yield• ≈ 75% of yield loss in modern VLSI fabs is due to particle

contamination.Yi ld d l d d i f ti b t th di t ib ti f• Yield models depend on information about the distribution of particles.

• Particles on the order of 0.1 - 0.3 µm are the most troublesome:– larger particles precipitate easily– smaller ones coagulate into larger particles

Den

sity

ity o

f Par

ticle

Y

ield

Los

s

0.6

0.8

1

If particle is in a critical areaDoes not go to zero

Part

icle

Prob

abili

Cau

sing

Y

0.2

0.4

critical areaDoes not go to zero



Particle Diameter- 0.1 - 0.3 µm


Contamination and Yield Model• Yields are described by Poisson statistics in the

simplest case.DAY

where AC is the critical area and DO the defect density

OC DAY −= exp

density.• If some fraction of the wafer, G, always produces

zero yields (near the edge of the wafer) this is y ( g )modified as

( ) OC DAGY −⋅−= exp1

• This model assumes independent randomly distributed defects and often under predicts yields



distributed defects and often under predicts yields.

17


Alternate Models• Use of negative

binomial statistics COC DA

Y⎟⎞

⎜⎛

=

1

1(4)

eliminates these assumptions and is more accurate.

OC

C⎟⎠⎞

⎜⎝⎛ +1

1more accurate.

– where C is a measure of th ti l ti l

0.1Negative Binomial (C = 2)

the particle spatial distribution (clustering factor).

0 001

0.01

Poisson

Negative Binomial (C = 10)

DO = 1 cm -2

0.0001

0.001

0 2 4 6 8 10 120.0001

O



0 2 4 6 8 10 12Chip Area (cm 2)


Negative Binomial Yield for C=2

1997 2006 2012

1Do = 0.01 cm-2

D = 0 1 cm-2

• Vertical lines are estimated chip sizes (from the ITRS).

0. 1

C h Y d

Do = 0.1 cm 2

• Note that defect densities will need to be extremely small in the future to achieve the high yields

i d f i ICip Y

ield

C h i p Y i e l d

Do = 1 cm-2

required for economic IC manufacturing.

• (See particle defect densities on

Chi

0 .0 10 5 10 15 20

Chip Area (cm2)

( pTable 4-1.)




Overall Yield• The total wafer yield must be the product of the yields

for each process step.

∏=

−

⎟⎠⎞

⎜⎝⎛ +=

levels

i

CiOiCi

CiDAY

1

1

• Note that previous curves refer to chip yield– Table 4-1 and Figures 4-22 and 4-23– Table 4-1 and Figures 4-22 and 4-23




Modeling Wafer Cleaning• Cleaning involves removing particles, organics

(photoresist) and metals from wafer surfaces.– Particles are largely removed by ultrasonic agitation during

cleaning.– Organics like photoresists are removed in an O2 plasma or in g p 2 p

H2SO4/H2O2 solutions.– The “RCA clean” is used to remove metals and any remaining

organics.g

• Metal cleaning can be understood in terms of:– Convert metal into ions soluble in the cleaning solution

Oxidation: the process that removes electrons from an atom ( )• Oxidation: the process that removes electrons from an atom (→)• Reduction: the process that gains and electron (←)

Si + 2H 2O ↔ SiO 2 + 4H + + 4e− (5)



M ↔ Mz+ + ze −

( )

(6)


Modeling Wafer Cleaning

−+ ++↔+ eHSiOOHSi 442 22 (5)22

−+ +↔ zeMM z

( )

(6)

−+ ++↔ eHOHOH 222 (7)

• If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate

++↔ eHOHOH 222 222 (7)

the stronger reaction will dominate.• Generally (7) is driven to the left and (5) and (6) to the right so that

SiO2 is formed and Mz+ is a solution soluble ion.• Good cleaning solutions drive (6) to the right since Mz+ is soluble and• Good cleaning solutions drive (6) to the right since Mz is soluble and

will be desorbed from the wafer surface.

N d l i t b t th i l d t di f th h i t



• No model exists, but there is a general understanding of the chemistry.

22


Oxidation-Reduction ReactionsOxidant/

Reductant Standard Oxidation Potential

(volts)

Oxidation-Reduction Reaction

Mn2+/Mn 1.05 Mn ↔ Mn2 + + 2e−

SiO2/Si 0.84 Si + 2H2O ↔ SiO2 + 4H+ + 4e− Cr 3+ /Cr 0.71 Cr ↔ Cr3 + + 3e−

Ni 2 + /Ni 0 25 Ni ↔ Ni2 + + 2e−

Less dominant

Ni /Ni 0.25 Ni ↔ Ni + 2eFe 3+ /Fe 0.17 Fe ↔ Fe3+ + 3e−

H2SO 4/H2SO3 -0.20 H2O + H2SO3 ↔ H2SO4 + 2H + + 2e−

Cu 2+ /Cu -0.34 Cu ↔ Cu 2 + + 2e−

/ +O2 /H2O -1.23 2H2O ↔ O2 + 4H + + 2e−

Au3+ /Au -1.42 Au ↔ Au3+ + 3e−

H2O2 / H2O -1.77 2H2O ↔ H2O2 + 2H+ + 2e− O3/O2 -2.07 O2 + H2O ↔ O3 + 2H+ + 2e− Dominant

3 2 2 2 3

• The strongest oxidants are at the bottom (H2O2 and O3). These reactions

go to the left grabbing e-, dominating, and forcing (6) to the right.



• Fundamentally the RCA clean works by using H2O2 as a strong oxidant.


Modeling Gettering• Gettering consists of

1. Making metal atoms mobile.2 Migration of these atoms to

Devices in nearsurface region

PSG Layer

2. Migration of these atoms to trapping sites.

3. Trapping of atoms.

surface regionDenuded Zoneor Epi Layer

10 - 20 µm1

2

Aus → Aui

• Step 1 generally happens by “kicking-out” the substitutional atom into an interstitial site. One possible reaction is:

IntrinsicGettering

Region 500+ µm

3

*Trapping

Diffusion

Au + I ↔ Auis:

• Step 2 usually happens easily once the metal is interstitial since most

t l diff idl i thi f3

Au S + I ↔ Au i

metals diffuse rapidly in this form.

• Step 3 happens because heavy metals segregate preferentially to damaged

BacksideGettering

Region *3

Trapping



segregate preferentially to damaged regions or to N+ regions or pair with effective getters like P (AuP pairs).


Gettering

“I”

All metal atoms mobile (DMi > DMs 10x)

“I” are closer to wafer surface

DM>> DDopantss

Sol Sol M >>M (Cu Ni)

Except of Ti, Mo, etc.

Sol. Sol MI>>MS (Cu, Ni)Sol. Sol. MI<<MS (Au, Pt)

AuS+I Aui kick-out mechanism, then getterSAus Aui+V dissociative or Frank-Turnbull mech.

I increase improves gettering of AuV increase hinders gettering



Ex. P diffusion, Ion Implant=damage, intrinsic gettering (=I ↑ )


Metal Diffusion to the Gettering Sites

Initial constant concentration

Time increase

Au diffuses to the waferAu diffuses to the wafer back side and is trappedBack

side trap



Manufacturing, Cleaning, Gettering - Chapter 4Trapping the Metal Atoms at the Gettering Sites (1)

• Trapped by: ion implantation, P diffusion, laser damage, poly-Si films, mechanical damage, etc. But HOW?

at the Gettering Sites (1)

• Physical damage -> metal trapped at defect sites; binding energy Eg depends on T;

i d ( )Fraction Bound=(1-K1exp-Eg/kT)

• Segregation, related to solubility in the silicon perfect crystal and in the gettering regionand in the gettering region

CAu,Si=NSiexp(-EA1/kT) in silicon regionCAu,G=NGexp(-EA2/kT) in gettering region

• The segregation coefficient is defined asThe segregation coefficient is defined ask0=(CAu,G+CAu,Si)/CAu,Si= 1+K2exp[-(EA1-EA2)/kT]For the case of phosphorousk0=1+NG/5x1022exp(0.82eV/kT ) (fraction of Au bound in gettering )



0 G p( ) ( g g )

Manufacturing, Cleaning, Gettering - Chapter 4Trapping the Metal Atoms at the Gettering Sites (2)

• Enhances sol.sol by high dopant concentrations: in “n” Au=acceptor, “p” - Au=donorA + - A - K [A -]/[A ][ -] t t

at the Gettering Sites (2)

Au+e- ↔Au-, Keq=[Au-]/[Au][e-]=constant,

[Au-i]/[Au]ni= [Au-

n]/[Au]n or [Au-n]/[Au-

i] = n/ni

Au acceptor ↑ in “n+” Si (100x if ni(1000°C)=7 14x1018 -> 1021cm-3 doping level)Au acceptor ↑ in n Si (100x if ni(1000°C) 7.14x10 > 10 cm doping level)

• Ion pairing model: AuP ↔ less strainIncreases with Phosphorous concentration

• Coulombic attraction Au+P → Au-P+

• Interaction with point defects V- ↑↑ in “n+” Aui+V- ↔Aus at the trapepd siteInteraction with point defects V ↑↑ in n Aui V Aus at the trapepd site

• Intrinsic gettering - trapping on dislocations and SF which surround precipitates. Dislocations have compressive and tensile stress - accommodate smaller and larger atoms



atoms

Manufacturing, Cleaning, Gettering - Chapter 4Limits and Future Trends in Technology and Modeling (1)Technology and Modeling (1)

• Eliminate defects from wafers: particles, contaminants, clean room.– SMIF Box (Standard Mechanical Interface): limit clean room

size, transport between stations in a clean box

• Wafer cleaning (next slide)Wafer cleaning (next slide)• Gettering:

– intrinsic (less extrinsic), – control Oi, Cs, – use low T processing, – use modeling tool →point defects engineering, g p g g,– release, diffuse, entrap.



Manufacturing, Cleaning, Gettering - Chapter 4Limits and Future Trends in Technology and Modeling (2)Technology and Modeling (2)

• Wafer cleaning in future ICsl h i l (li id– less chemicals (liquids, vapors), more diluted (disposal)N l i– New cleaning:

• Use ozone• Dry and vapor phase,

(Vapors Plasmas)(Vapors, Plasmas) environment! Cluster tools

• Low Energy Physical Processes (sputtering)

Watch for surface roughness

( p g)• Photochemically enhanced

clean




Summary of Key Ideas• A three-tiered approach is used to minimize contamination in wafer

processing.• Particle control wafer cleaning and gettering are some of the "nuts and• Particle control, wafer cleaning and gettering are some of the nuts and

bolts" of chip manufacturing.• The economic success (i.e. chip yields) of companies manufacturing

chips today depends on careful attention to these issues.c ps oday depe ds o ca e u a e o o ese ssues• Level 1 control - clean factories through air filtration and highly purified

chemicals and gases.• Level 2 control - wafer cleaning using basic chemistry to remove g g y

unwanted elements from wafer surfaces.• Level 3 control - gettering to collect metal atoms in regions of the wafer

far away from active devices.• The bottom line is chip yield. Since "bad" die are manufactured

alongside "good" die, increasing yield leads to better profitability in manufacturing chips.



text book: silicon vlsi technology fundamentals, …• bunny suits, gloves, air showers, covered...

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