May 2, 2012 1May 2, 2012

Leor Nevo – Intel PE Courtesy of Intel mates: John Giacobbe

Rick Livengood, Donna Medeiros Rev 07

The 2012 transitionfrom

DFM to PDFD DESIGN FOR (PHYSICAL) DEBUG FOR SILICON MICROSURGERY AND PROBING OF FLIP-CHIP PACKAGED INTEGRATED CIRCUITS

May 2, 2012 2

Outline

• ACRONYMS (alphabetically)• From DFM to PDFD - Transition motivation• PDFD capabilities overview• PDFD scope & flow• Flip-chip mechanical preparation and navigation• Bonus combinational and sequential cells• PDFD in Clock Elements• Insertion, placement and automation• Summary & Conclusions

PDFD - Leor Nevo, Intel

May 2, 2012 3

ACRONYMS (alphabetically)

Al Aluminums Cl CupperCAD Computer Aided DesignCNC Computer Numerical ControlDFD Design For DebugDFM Design for ManufactureDFT Design For TestDRC Design Rule Checker ECO’s Engineering Change OrderEDA Electronic Design AutomationFAB FABrication PlantFIB Focused Iron BeamLVP Laser Voltage Probe

HVM High Volume ManufacturingHW HardWareIC Integrated CircuitsIR Infra Red.PDFD Physical Design For DebugPE Principal EngineerTPT Through Put TimeRC Resistance & CapacitanceSW SoftWareVLSI Very Large Scale Integrated

May 2, 2012 4

Transition Motivation

• DFM – we all got used to talking about DFM.. For years..(taking care for high Yield, reduced variation by optimized density.)

• While DFM mostly moved to become a hard DRC (~> 1000)– HVM Fabs can’t count on designers “good will”..– They have moved most of the DFM guidelines into strict rules !!

• We assume that the VLSI design timeline is quite predictable– But the silicon debug for sub-micron becomes a big challenge..– The Micro-surgery HW has difficulty in following Moore’s law – The

relevant HW can not keep scaling every 2 years !

• SO – PDFD provides hooks in the design to enable analysis of the deep sub-micron IC beyond DFT & system debug.

PDFD - Leor Nevo, Intel

May 2, 2012 5

Overview • What is PDFD? Design hooks placed in layout to enable optimized access to nodes

during silicon debug: FIB probe access, backside circuit edit, probing. PDFD Feature types include:

Bonus/happy devices, probe points, debug tool navigation features, FIB cut / Connect cells.

• PDFD provides critical bug research during the debug phase of a VLSI product for faster time-to-market. Features designed to add capability or to improve productivity. Bugs can be root caused and validated in a few days compared to weeks or

months required for a new mask set. Reduces the number of steppings/masks required to certify for HVM.

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PDFD Scope

• PDFD provides hooks into the design to enhance and enable analysis of Integrated Circuits in a more reasonable time frame.

• This paper will cover design automation/cad solutions and real life technical proposal to enable: Smooth & accurate Backside Navigation (flip-chip) Pre-placed Enhanced Probe-ability (cut/connect) Enhanced Silicon Microsurgery (able to Trim, Cut, connect by-

pass using external low-res wires). Fibable and Spare Logic Gate for FIB or design ECO’s to be

tested on silicon before reproducing on next design step/retrofit.

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Flip-Chip Substrate

Chip A Chip BCaps Caps

Lands

Global thinning of Silicon Substrate:

May 2, 2012 8

Flip-Chip Substrate

Chip ACaps Caps

Lands

Chip B first thinned down from 720m to < 200m using Mechanical Polishing or CNC Mill

Chip B

Global thinning of Silicon SubstrateReminder : If we will go too

deep – we will start impact the devices functionality too…

May 2, 2012 9

Trench (Top View)

Silicon Substrate

Fine Trench Etch Step

Trench Etch Step

Trenching Process

SiliconSubstrate

SiCl4

Cl2

Argon IonLaser

ScanningMirrors

Cl2SiCl4

Physical Debug Overview: example only

Laser Chemical Etcher

04/10/2023

May 2, 2012 10

The big Fiducials provide navigation points for FIB IR (for circuit edits)

The more spreading- the more accurate hit point.

Don't forget – we are drilling from the back with eyes like blind folded .

High density of Fiducials improve beam placement accuracy < 100nm

Design For Debug (Flip-Chip Navigation Fiducial)

Die

May 2, 2012 11

Navigation Features

• The fiducial alignment points are the most utilized PDFD features as they are used on every edit.– The larger cell referred to as a global fiducial is placed with a 5-10mm

pitch and provides the 1st level of navigation..– The smaller local fiducial has a much higher pitch typically around 70u

and is used to achieve sub 100nm accuracy.

• Both have an array of contacts and diffusion that are exposed in the FIB and locked to CAD database of the chip

M1

Contact

Diffusion

Global

Local

EDITAREA

May 2, 2012 12

Discover bug through

production, debug or

system level test

Generate or

customize specific

pattern to highlight

bug

Isolate bug

using DFT to functionalarea or clk

region

NavigateAccurately &

Root cause bug using probe and design data/tools

Confirm fix by performing FIB edit or rely on re-simulation

Implement Fix in layout and

generate new mask set

PDFD flow overview

Siliconarrived

May 2, 2012 13

Circuit Edit Geometry and RC Challenges

• The device scaling and layout efficiency improvements have reduced the physical debug tools ability to access transistors and metal signals:– 65nm to 32nm and below= meaningful reduction in white space. – This drives the FIB which has not been able to support the Nano.– Probe tools have been able to scale but at reduced productivity.– This limit in technology scaling has resulted in a greater need for

features to be placed in silicon to enable access (i.e., PDFD).

130nm

Gate

FIB Box

90nm

65nm

45nm

32nm

M1

Poly

Diffusion

M1

S/D

130nmM1

S/D

May 2, 2012 14

FIB SiO2

Circuit Edit Geometry and RC Challenges

M1

M2

GateV1

Diff

Contacts

Si

FIB Line

STR

FIB Via

Demo

• PDFD features provide guaranteed access to critical signals on the 2-3 lowest metals.– Excellent correlation of FIB wire resistance: same ballpark.– Shown here on the left is a metal 1 PDFD connection point and

on the right is an opportunistic metal 1.

May 2, 2012 15

PDFD Building Blocks• Basic building block features are designed to meet FIB rules

The features are created as cells that can get auto spread by CAD.

• The Metal 1 connection pad provides safe access to signals Optimized to keep the FIB via resistance close to real via resistance. Cell area driven to min required – mostly meet projects cells. [A] - Metal 1 area maximized to decrease contact resistance.

• Cut cells provide guaranteed access to target signals. [B] Metal 1 version typically used for active signals (not impact timing) [C] Poly cut cell introduced when metal signals migrated from Al to Cu

M1

Poly

B C

Probe point

M1 Cut option Poly cut option

A

May 2, 2012 1616

Design For Debug (Node Access Points)

Auto placement tool can first place FIB (edit) node access points.Consider auto route in upper metal??

Auto placement tool follow up with placement of LVP access points.

Layout showing Metal lines without PDFD coverage

May 2, 2012 17

Design For Debug (Spare Logic Gates)

o Designed in FIB Cut Points

Diff

Diff

Spare Logic Gate(3 input device)

o Designed in FIB

Connection Points

FIB-able Bonus Logic

May 2, 2012 18

Bonus Combinational and Sequential Cells • Bonus logic and sequential

elements are added to a design to validate functions and speed path bugs. – Typical cells include NAND,

NOR, Buffer, latch, and Flop.– They can be used in dash.

• Chose cell from a standard library that has the ability to drive FIB metal ~100-200um.– The cell is enlarged so that

building block cut & connect cells can be inserted.

– Input tied to ground.– output left floating.

1st Stage 2nd Stage

GroundBuf Output

Inv OutputInput

Cut

May 2, 2012 19

Bonus Combinational and Sequential Cells • In the below example Signal-B is driving a buffer but now should get the

NAND of Signal-A and Signal-B. • The FIB connects Signal-A and Signal-B which are then routed using FIB

metal to the inputs of a bonus NAND. – The output of the NAND is connected back to Signal-B before the input to the next stage.

• Once the routing and connecting are done the FIB will cut Signal-B as shown by the “X” and the FIB CUT cells at the NAND’s input.

Bonus NAND

SignalB

SignalA

May 2, 2012 20

PDFD In Clock Elements• The ability to alter the timing of clocks is one of the main

activities performed during speed path debug. On current generation processes it has become essential to design PDFD

features and accessibility into the clock elements themselves.

• To provide FIB access in such small geometries clock elements are designed with increased spacing's. In this case a multi legged clock inverter can be trimmed successfully without

damaging the unrelated adjacent device (Trim= ability to reduce device/driver size (strength) ).

For optical probe accessing the separation helps minimize cross talk.

v

M1

Poly

Diffusion

Insert Extra spacing inside the Clock cell to ensure FIB success.

Clock InverterUnrelated DeviceUnrelated Device Clock Inverter

Minimum spaced devices.

May 2, 2012 21

PDFD In Clock Elements• A second type of PDFD feature designed into clocks are

mechanical probe points/FIB access cells. o A building block with connect cells is placed in free space.o The connection point allows for a FIB load capacitor to be

connected thus delaying the signal. o It allows the output to be routed to another circuit using FIB.o Since design requires fills in empty areas for DFM – why not use it

for PDFD?

M1

Poly

Diffusion

M1 FIB Connect

Large Clock inverter with Offset Diffusion

May 2, 2012 22

Insertion and Placement Methodologies• Historically each functional block owner has had to manually insert PDFD

features resulting in wasted effort and inconsistent implementation. Some alternate options would be: integrate features directly into cells from the common lib. Another method : use of automated scripts and customized flows.– Can be developed by central CAD team into design flows– An insertion example is shown here where a script pre-placed bonus

combinational and sequential cells as well as navigation cells into a block prior to the synthesis flow.

– Flow customized to meet individual product’s needs for cell types, strength and pitches. For example: A product that utilizes proven design may decide to have larger pitches then a design with untested logic and verified circuits.

Q

QSET

CLR

D

L

Q

QSET

CLR

D

L

• The bonus cell pitch is also determined by FIB

routing technology and RC impact.

• The pitch for the fiducial [+] is based on FIB labs

& navigation equipment accuracy.

May 2, 2012 23

PDFD Utilization for Product Stepping's

• The production of a VLSI DIE might require multiple loops– So while DFM helps long term and HVM yield – current business need is for

development and implementation of PDFD so that some of the below scenarios can be avoided.

For e.g.$ A full stepping requires a complete set of masks- IMPACTs TTM, TPT & Cost.$ Products use dash or sub stepping's which requires only few new backend masks = potential saving

month's/weeks of time – IMPACTs TTM, TPT & Cost.$ This reduces time to market as product can be held in the FAB at a specific layer until the new backend

masks are generated – IMPACTS TTM. $ DFM : For simplistic timing or electrical issues a dash stepping typically can be performed at metal

layers only since they do not require additional transistors. IMPACTS TTM, TPT & Cost.

• The implementation of strategically placed PDFD cells allow these type of logic or complex bugs to be fixed in a dash.

May 2, 2012 24

Wait.. Did we miss something? • With future Deep sub-micron design < 32nm –

– How can one navigate to the exact location?– Is the ability to navigate to +/- 1 u good enough?– While metals width is less than 100nm: 1u means I will get to few

signals but not to the specific one … not good.

• So we: – innovated Global fiducials to get to the 1u Local Fiducials so as to facilitate reaching the exact signal.. – Even if it is deep inside the silicon. We have lots of challenges to get

to the upper metals… across M1-M2 to M3-M4 .. Deeper?– Assuming design will budget the area for the Global fiducials..

(~10*10u) and for the local fiducials 1-2x basic cells size, CAD/SW automation will be needed to place the fiducials.

• After all – it require 3 notable spots to find a new location

PDFD - Leor Nevo, Intel Corporation

May 2, 2012 25

Flip-Chip Substrate

Chip ACaps CapsChip B

First Conclusion The transition from DFM to PDFD is due :

While DFM ensures HVM a clean design is of equal importance. PDFD implementation in next generations VLSI products is a critical part of

the overall DFD concept that must be employed by VLSI Product teams. Placing design access hooks into the silicon and mainly on critical nodes

and cell types results in higher productivity and capability for physical debug tools which further enables faster TPT from 1st silicon to product.

The utilization of PDFD results in fewer stepping's or partials layers retrofits which translates to faster TTM. Having each new step already validated on silicon has a big upside potential to save millions of $$$

May 2, 2012 26

Second Conclusion Optimal coverage of PDFD will become even more critical as

the semiconductor industry moves into the 45nm,32nm and below or else “no bug” guarantee is questionable. It is clear that improvements are needed in scaling circuit

edit equipment's and material properties! Is that enough? A comprehensive PDFD strategy is required on future

technologies if the industry is to continue to realize the benefits of performing in-silicon validation of speed, yield & logic bugs. SO while old traditional DFM guides have became strict

rules - a better use of the white space would be to add DFM fillers for DFD – Right ?

This is true for front-side design as the same as Flip-chips.

May 2, 2012 27

Q & ALeor Nevo - Intel DFM-PDFD PE

Thanks .

Leor Nevo, Intel Corporation

May 2, 2012 28

References (Back-up)

• There is a very small set of literature outside and projects are trying to do their best using DFT features to debug by the flip-chip pins - but it requires more and more area.

• The Design Automation Conference, EDA, test and silicon debug companies announced the creation of the Design-for-Debug Consortium to address silicon debug challenges and collaboratively define the tools needed.

PDFD - Leor Nevo, Intel Corporation

May 2, 2012 29

PDFD In Clock Elements• The ability to alter the timing of clocks is one of the main

activities performed during speed path debug.– On current generation processes it has become essential to design PDFD features

and accessibility into the clock elements themselves.

• To provide FIB access in such small geometries clk cells must be designed with extra spacing between transistor’s.

– In this case a multi legged clock inverter can be trimmed successfully without damaging the unrelated adjacent device.

• For optical probe access the separation helps minimize cross talk.

v

M1

Poly

Diffusion

Insert Extra spacing inside the Clock cell to ensure FIB success.

Clock InverterUnrelated DeviceUnrelated Device Clock Inverter

Minimum spaced devices.