the 3d enigma · ieee components, packaging and manufacturing technology chapter, scv section nov....
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![Page 1: The 3D Enigma · IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section Nov. 11, 2013 3 Excessive Complexity Fear](https://reader033.vdocument.in/reader033/viewer/2022050310/5f71faf1bce37a352d55804f/html5/thumbnails/1.jpg)
IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 1
Stacking Untested Wafers to Improve Yield
or
3D: Where the Timid Go to Die
The 3D Enigma
The Promise The Reality
• High Performance• Low Power• Improved Density
M th M
• A decade of“next year”
• High costs• Low yields• Non existentMore than Moore
or at leastas much as Moore
• Non-existent ecosystem
• Loss of credibility
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 2
Historic Precedent
Poor Science
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 3
Excessive Complexity
Fear
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 4
But Flying is EASY
Heroes focus on Landing
US Airways Flight 1549 in the Hudson River– Capt. Chesley Sullenberger in command.
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 5
Step 1: Commit to 3D
DiRAM™ True 3D RAM Architecture
Tezzaron Confidential 10
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 6
Dis-Integrated 3D RAM Architecture
DiRAM™ Architecture
Memory Cellsand
Access Transistors
S A t
Tezzaron Confidential 11
Sense Amps, etc. I/O Layer
256 Independent Channels
Each Channel• 256 Mb Storage
• 64 Gb/s Bandwidth
• 9ns Latency
• 15ns tRC
• 16 Paired Banks
Tezzaron Confidential 12
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 7
DiRAM4 Stack Performance
• 64 Gigabits Storage64 Gigabits Storage
• 16.4 Terabit/s
Data Bandwidth
• 4096 Open Pages
• > 500 Billion256 • > 500 Billion Transactions Per Second
Tezzaron Confidential 13
IndependentChannels
DiRAM4 Scale* Drawing
Top View Sid ViTop View
175 mm214 m
m
12.5 mm
Side View
0.5 mm
Tezzaron Confidential 14
Isometric View* Almost to scale
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 8
Via-Free Wafer Stacking
Copper TSVCopper TSV≈ 10µ x 50µ
2x
Tezzaron Tungsten
Tezzaron Confidential 15
gSuperContact™
≈ 1µ x 5.5µ
Tiny, Common, Cheap, Fast and…
One 100
10 Di t 1 Di t10µ DiameterCopper TSV
1µ DiameterTungsten SuperContact
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 9
Radically Different Manufacturing
Conventional Flow
F b i t W f
Tezzaron Flow
F b i t W f• Fabricate Wafer
• Probe Test Die
• Thin Wafer
• Singulate Die
• Stack Good Die
• Fabricate Wafer
• Stack & Thin Wafers
• Probe Test Wafer Stacks
• Singulate Stacks
• Stack Wafers• Thin Top Wafer• Repeat• Probe Test Stacks• Singulate Stacks
• Package Stack
• Burn-In & Test Stack
• Package Stacks
• Burn-In & Test Stack
Tezzaron Confidential 17
Singulate Stacks
Never Handle A Thin Wafer
The Tezzaron MantraThe Tezzaron Mantra
Bond Two…Grind One
…to make the world’s
Tezzaron Confidential 18
…to make the world s
thinnest RAM wafers
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 10
“That can’t work…”
“…bonding un-tested die will produce near zero yields, poor
reliability and high costs.”
Translation
Tezzaron Confidential 19
You Tezzaron people are crazy!
Novati Technologies - Austin
• Tezzaron subsidiary– Manufacturing volume– Services available
• 3D Assembly Options– Cu-Cu– DBI®,
– Oxide Bonding– Intermetallic– Gold-Indium, Gold-Gold
• Silicon Interposers– Passive– Passive Plus– Active
Tezzaron Confidential 20
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 11
Super dense interconnect allows…
Bi-STAR™Bi STARBuilt-in Self Test And Repair
• Controlled by embedded ARM processor
• Enabled by per-cell control interconnect
• Super-fine grained test and repair
• Continuous, in-the-system hard and soft error repair
Tezzaron Confidential 21
Bi-STAR™ Does More, Works Better
Bi-STAR Repairs• Bad memory cells
Bi-STAR Tests
T t > 300 000• Bad memory cells• Bad line drivers• Bad sense amps• Shorted word lines• Shorted bit-lines
L k bit
• Tests > 300,000 nodes per clock cycle
• Tests > 1,000x faster than external memory tester
• Via SPI port works• Leaky bits• Bad secondary bus
drivers
• Via SPI port, works with Host to allow continuous scrub / repair
Tezzaron Confidential 22
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 12
Bi-STAR Repair Improves Yield
100%
Yie
ld
Tezzaron Confidential 23
Stack Height
EnablesSuper Thin
Bonding Untested
Solve 3D Problems with 3D
EnablesEffective
EnablesSub-micron
Super Thin Wafers
Untested Wafers
EffectiveRepair
Sub-micron Vias
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 13
DiRAM: Efficiency for the Future
• Less aggressive wafersgg
• Higher array efficiency
• Much lower test cost
Hi h i ld• Higher yield
• Longer product life cycles
Tezzaron Confidential 25
DiRAM: Efficiency for the Future
• Less aggressive wafersgg
• Higher array efficiency
• Much lower test cost
Hi h i ld• Higher yield
• Longer product life cycles
Tezzaron Confidential 26
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 14
High End Routing
Tasks
P k t B ff
Performance Metrics
D it• Packet Buffer(Burst Read/Write)
• Tables(Read Dominated)
• Stats
• Density – Line Rate / Seconds
• Bandwidth– Line Rate x 2.5
• Transaction Rate(Read-Mod-Write)
Tezzaron Confidential 27
– Transactions x Line Rate / Min Packet Size
400Gb Routing with DiRAM4
Network Processor
22 mm x 19 mm
DiRAM4
14 mm x 12.5 mm
Tezzaron Confidential 28
26 mm x 32 mm Interposer
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 15
1Tb Routing with DiRAM4
D
14 mm
Network Processor
22 mm x 19 mmD
iRA
M4
m x 12.5 m
m
DiR
AM
14 mm
x 12
Tezzaron Confidential 29
27 mm x 35 mm Interposer
M4
2.5 mm
The Right I/O for Each MarketPhotonic I/O• Lowest Power
Hi h t P f
SerDes I/O• Highest Power• Moderate Performance
Pico-SerDes I/O• Lower Power• Moderate Performance
• Highest PerformanceDiRAM4
Launcheswith
0.7 V CMOS I/O
Tezzaron Confidential 30
Moderate Performance
2.5D Si or Organic• Low Power• High Performance
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IEEE Components, Packaging and Manufacturing Technology Chapter, SCV Section
Nov. 11, 2013
www.cpmt.org/scv/ 16
Tezzaron DiRAM Roadmap
64 Tb/s
32 Tb/s
64 Tb/s
Tezzaron Confidential 31
2014 2016 2018
16 Tb/s
David Chapman
VP Marketing & Technical SalesTechnical Sales
Tezzaron Confidential 32