the belle ii silicon vertex detector
DESCRIPTION
VCI, 13 February 2013. The Belle II Silicon Vertex Detector. Markus Friedl (HEPHY Vienna) for the Belle II SVD Group. Introduction Front-End Electronics Performance Summary. Introduction Front-End Electronics Performance Summary. Belle. KEKB. Linac. - PowerPoint PPT PresentationTRANSCRIPT
The Belle II Silicon Vertex DetectorMarkus Friedl (HEPHY Vienna) for the Belle II SVD Group
VCI, 13 February 2013
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 2
IntroductionFront-EndElectronicsPerformanceSummary
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 3
IntroductionFront-EndElectronicsPerformanceSummary
KEKB and Belle @ KEK (1999-2010)
Center of mass energy: Y(4S) (10.58 GeV)
High intensity beams (1.6 A & 1.3 A) Integrated luminosity of 1 ab-1
recorded in total Belle mentioned explicitly in 2008
Physics Nobel Prize announcement to Kobayashi and Masukawa
Linac
Belle
KEKB
~1 km in diameter
KEKB Belle
Linac
About 60km northeast of Tokyo
Asymmetric machine:8 GeV e- on 3.5 GeV e+
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 4
M.Friedl (Belle II SVD Group): The Belle II SVD
SuperKEKB/Belle II Upgrade: 2010–2015 Aim: super-high luminosity ~81035 cm-2s-1 11010 BB /
year LoI published in 2004; TDR published in 2010 Refurbishment of accelerator and detector required
nano-beams with cross-sections of ~10 µm x 60 nm 10 mm radius beam pipe at interaction region
13 February 2013 5
http://belle2.kek.jp
Belle II Vertexing Subdetectors
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 6
Silicon Vertex Detector (SVD) 4 layers of DSSDs
Pixel Detector (PXD) 2 layers of DEPFET pixels
Belle II Vertexing Environment Low energy machine (10.58 GeV) – multiple
scattering Needs very low mass detector
PXD DEPFET sensors are thinned to 75 µm SVD uses “Origami chip-on-sensor” concept
High luminosity – occupancy/pile-up Need small sensitive area and/or fast readout
PXD has small cell size (50 x 50 µm2) SVD has fast shaping (50 ns) and hit time
reconstruction (~3 ns) Radiation – 100 kGy Magnetic field – 1.8 T
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 7
Silicon Vertex Detector Concept Use largest possible (6”) double-sided sensors
(DSSDs) Minimize relative amount of structural material
Fast shaping readout Minimize occupancy Fast readout implies higher noise Noise is mainly determined by input capacitance
Place readout chips as close as possible to sensor strips Minimize capacitive load by avoiding long fanouts
Use efficient CO2 cooling Allows thin cooling pipes 13 February
2013M.Friedl (Belle II SVD Group): The Belle II SVD 8
Belle II Vertex Detector Pixel Detector – 8M pixels
2 DEPFET layers at r = 14, 22 mm Excellent and unambiguous
spatial resolution (~15 µm) Coarse time resolution (20 µs)
Silicon Vertex Detector – 220k strips 4 DSSD layers at r = 38, 80, 104, 135 mm Good spatial resolution (~12/25 µm)
but ambiguities due to ghosting Excellent time resolution (~3 ns)
Combining both parts yields a very powerful device!13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 9
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 10
IntroductionFront-EndElectronicsPerformanceSummary
Front-End Geometry
4 layers arranged in ladders Outer 3 layers have slanted forward part Limited acceptance angle (17°…150°) allows to
place services outside (cyan cones) while minimizing material within
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 11
Double-Sided Silicon Sensors 3 different types required
Large rectangular sensors – 123 x 58 mm2 (HPK) Small rectangular sensors – 123 x 38 mm2 (HPK) Trapezoidal sensors – 123 x 58…38 mm2 (Micron)
Production is in progress Presently ~60% delivered
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 12
Origami Chip-on-Sensor Concept Low-mass double-sided readout Flex fanout pieces wrapped to opposite side All chips aligned on one side single cooling pipe (D = 1.6 mm)
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 13
Side View (below)
APV25 chips(thinned to 100µm )
3-layer kapton hybrid
fanout for n-side (z)DSSD
flex fanout wrapped to p-side (r-phi)
cooling pipeCF sandwich ribs
APV25(thinned to 100µm )
support ribs
cooling p ipe
SensorAirex
Kaptonwrappedflex fanout
Origami Prototype Modules Single Origami module
Double Origami module
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 14
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 15
APV25 chips
Cooling pipe
Origami ladder
Sensor underneath flex circuit
Pitch adapter bentaround sensor edge
End ring (support)
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 16
IntroductionFront-EndElectronicsPerformanceSummary
General SVD Readout Scheme Based on existing prototype
system (2007) verified in lab and beam tests
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 17
1748APV25chips
Front-endhybrids
Rad-hardDC/DC
converters
Analog level translation,data sparsification andhit time reconstruction
Unified Belle IIDAQ system
~2mcoppercable
Junctionbox
~10mcoppercable
FADCUnified optical
data link (>20m)
Finesse Transmitter Board (FTB)
COPP
ER
DATCON ONSEN
APV25 Front-End Chip
Developed for CMS by IC London and RAL 70,000 chips running in the CMS Tracker since 2008
40 MHz clock; 128 channels; 192 cells deep analog pipeline 50 ns (adjustable) shaping time 0.25 µm CMOS process (>100 MRad tolerant) Low noise: 250 e + 36 e/pF Multi-peak mode (read out several samples along shaping
curve) 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 18
preamp shaperAPSP S/H
inverterpipeline
MUX gain
128:1MUX Differential
currentoutput amp
Junction Box
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 19
CERN-made DC/DC converters for front-end powering
Comparative measurement: no noise penalty
FADC Block Diagram
Analog & digital level translation between bias and GND Digitization, signal conditioning (FIR filter), data processing Central FPGA is an Altera Stratix IV GX13 February
2013M.Friedl (Belle II SVD Group): The Belle II SVD 20
Leve
l Tra
nsla
tion
AD
Cs
Mon
itorin
g
CentralFPGA
VM EFPGA
JitterCleaner
Delay
VM E bus
GbE
FADC Controller
FTB
Junc
tion
Box
Signals
CLK
Contro ls
S lowContro ls
Data
Data
Contro ls
V/I
HV LV
FIR
FADC: Overall Concept 9U VME
module (needs much space for level translation circuits)
Circuit is designed, now PCB layout is made13 February
2013M.Friedl (Belle II SVD Group): The Belle II SVD 21
IndicatorLED s
H ybridC onnectors
V M EA ltera
S tra tix 4 G Xdaughte r boa rd
P1
P2
Bus
G bE
P3
Analogleveltrans lation
FE contro l& m onitoring
D igita l(contro ls)leveltrans lation
AD C s
D elay
De lay
JitterC leanerC LK
distribu tion
C LKdistribu tion
The “Human” Touch…
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 22
FTB: Link to DAQ and PXD Firmware development ongoing Optical link tests at 2.54 and 3.175 Gb/s
successful
Second iteration of PCB for minor corrections underway
SVD data are also streamed to PXD for online data reduction
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 23
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 24
IntroductionFront-EndElectronicsPerformanceSummary
Threshold
Threshold
Tim e over threshold ~ 2000ns (m easured)
Tim e over threshold ~ 160ns (measured)
Sensitive tim e w indow ~ 20ns
VA1TATp~800ns
APV25Tp~50ns
Pulse shapeprocessingRM S(tm ax)~3ns
Reduction ~12.5
Reduction ~8
Total reduction ~100
Hit Time Reconstruction Benefits
Sufficient to cope with a 40-fold increase in luminosity 13 February
2013M.Friedl (Belle II SVD Group): The Belle II SVD 25
Belle I SVD
Belle II SVD
Achieved Hit Time Resolution
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 26
Results achieved in beam tests with several different types of Belle II prototype modules (covering a broad range of SNR)
2...3 ns RMSaccuracy at typical cluster SNR(14...24)
Will be donein FPGA (using lookup tables) – simulationsuccessful
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30
Trm
s [n
s]
Cluster SNR
Peak time precision vs. SNR
SPS June 2008
KEK Nov 08 standard
KEK Nov 08 doubled IPRE
KEK Nov 08 31.8 Mhz
SPS Aug 09 run042
SPS Aug 09 run043
SPS Aug 09 run6873
SPS Aug 09 run012
SPS Aug 09 run019
Theory
Close to theoretical limit(G. De Geronimo, in “Medical Imaging” by K. Iniewski)
Z Vertex Resolution
Belle II (PXD & SVD) will be a factor 2 better than Belle (SVD only)
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 27
13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD 28
IntroductionFront-EndElectronicsPerformanceSummary
Summary Belle II Vertex Detector consists of
Pixel Detector (PXD): unambiguous spatial resolution
Silicon Vertex Detector (SVD): precise timing Silicon Vertex Detector
4 layers of 6” double-sided silicon sensors APV25 front-end chip with 50 ns shaping time Origami chip-on-sensor readout concept for low
mass Highly efficient CO2 cooling
Schedule R&D completed, construction has started Now building final prototypes (pre-series)13 February
2013M.Friedl (Belle II SVD Group): The Belle II SVD 29