CS152Lec11.1

CS 152 Computer Architecture and Engineering

Lecture 11

Multicycle Controller Design (Continued)

CS152Lec11.2

The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

° Today’s Topics: • Microprogramed control• Administrivia• Microprogram it yourself• Exceptions

Control

Datapath

Memory

ProcessorInput

Output

CS152Lec11.3

Controller Design° The state digrams that arise define the controller

for an instruction set processor are highly structured

° Use this structure to construct a simple “microsequencer”

° Control reduces to programming this very simple device

microprogramming sequencercontrol

datapath control

micro-PCsequencer

microinstruction

CS152Lec11.4

Multicycle Datapath

PC

Nex

t PC

Ope

rand

Fetc

h

Inst

ruct

ion

Fetc

h

nPC

_sel

IRRegFile E

xtA

LU Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

Res

ult S

tore

Reg

Dst

Reg

Wr

Mem

Wr

Mem

Rd

S

M

Mem

ToR

eg

Equ

al

ALU

ctr

ALU

Src

ExtO

p

A

B

E

CS152Lec11.5

State Diagram of Controller

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQPC <= Next(PC)

SW

“instruction fetch”

“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

00111011

1100

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec11.6

Using a Jump Counter

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQPC <= Next(PC)

SW

“instruction fetch”

“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

00111011

1100

inc

load

zero zerozero

zero

zeroinc inc inc inc

inc

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec11.7

Example: Jump-Counter

op-codeMap ROM

Counterzeroincload

0000i

i+1

i

None of above: Do nothing (for wait states)

CS152Lec11.8

Sequencer°Sequencer-based control unit

• Called “microPC” or “µPC” vs. state register

Control Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1

DispatchROM:

Opcode

microPC

1

µAddressSelectLogic

Adder

DispatchROM

Mux

0012

Opcode DispatchState

R-type 000000 0100BEQ 000100 0011ori 001101 0110LW 100011 1000SW 101011 1011

Microprogram

CS152Lec11.9

Microprogramming (Maurice Wilkes)° Control is the hard part of processor design

° Datapath is fairly regular and well-organized° Memory is highly regular° Control is irregular and global

Microprogramming:

-- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations

Microarchitecture:

-- Logical structure and functional capabilities of the hardware as seen by the microprogrammer

Historical Note:

IBM 360 Series first to distinguish between architecture & organizationSame instruction set across wide range of implementations, each with different cost/performance

CS152Lec11.10

“Macro and micro - instruction” Interpretation

MainMemory

executionunit

controlmemory

CPU

ADDSUBAND

DATA

.

.

.

User program plus Data

this can change!

AND microsequence

e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)

one of these ismapped into oneof these

CS152Lec11.11

Variations on Microprogramming

° “Horizontal” Microcode– control field for each control point in the machine

° “Vertical” Microcode– compact microinstruction format for each class of microoperation

– local decode to generate all control points (remember ALU?)branch: µseq-op µaddexecute: ALU-op A,B,Rmemory: mem-op S, D

µseq µaddr A-mux B-mux bus enables register enables

HorizontalVertical

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Extreme Horizontal

inputselectN3 N2 N1 N0. . .

13

Incr PCALU control

1 bit for each loadable register enbMAR enbAC . . .

Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time.

Makes sense to encode fields to save ROM space

Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits

NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction

CS152Lec11.13

More Vertical Formatsrc dst

DEC

DEC

other control fields next states inputs

MUX

Multiformat Microcode:1 3 6

1 3 3 3

0 cond next address

1 dst src alu

DEC

DEC

Branch Jump

Register Xfer Operation

CS152Lec11.14

Hybrid Control

Not all critical control information is derived from control logic

E.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc.

RegisterFile

RS1

DEC

RS2

DEC

RD

DEC

op rs1 rs2 rdIRtocontrol

enablesignalsfromcontrol

CS152Lec11.15

Summary: Horizontal vs. Vertical Microprogramming

NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations

Most microprogramming-based controllers vary between:

horizontal organization (1 control bit per control point)

vertical organization (fields encoded in the control memory and must be decoded to control something)

Horizontal

+ more control over the potential parallelism of operations in the datapath

- uses up lots of control store

Vertical

+ easier to program, not very different from programming a RISC machine in assembly language

- extra level of decoding may slow the machine down

CS152Lec11.16

Microprogramming a multicycle processor

° 1) Choose datapath and sequencer architecture° 2) Assign states and sequence of each (multicycle)

instruction (i.e. define the controller FSM)° 2) Choose microinstruction format (minimum bits to

describe all allowable functions of sequencer and datapath)

° 3) Map instructions into microinstruction sequences

CS152Lec11.17

Sequencer°Sequencer-based control unit

• Called “microPC” or “µPC” vs. state register

Control Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1

DispatchROM:

Opcode

microPC

1

µAddressSelectLogic

Adder

DispatchROM

Mux

0012

Opcode DispatchState

R-type 000000 0100BEQ 000100 0011ori 001101 0110LW 100011 1000SW 101011 1011

Microprogram

CS152Lec11.18

Datapath – single memory, single regfile

° Miminizes Hardware: 1 memory, 1 adder

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instruction Reg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mux

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mux

0

1

32

PC

MemtoReg

Extend

ExtOp

Mux

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mux

1

0

32

Zero

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A

CS152Lec11.19

Finite State Machine (FSM) Spec

IR <= MEM[PC]PC <= PC + 4

R-type

ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi

ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW

“instruction fetch”

“decode”

Exe

cute

Mem

ory

Writ

e-ba

ck

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010

0011

If A = B then PC <= ALUout

ALUout <= PC +SX

Q: What can wedo instate 0001?

CS152Lec11.20

Finite State Machine (FSM) Spec (improved)

IR <= MEM[PC]PC <= PC + 4

R-type

ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi

ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW

“instruction fetch”

“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010

If A = B then PC <= ALUout

ALUout <= PC +SX

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec11.21

Designing a Microinstruction Set

1) Start with list of control signals2) Group signals together that make sense (vs.

random): called “fields”3) Place fields in some logical order

(e.g., ALU operation & ALU operands first and microinstruction sequencing last)

4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals

5) To minimize the width, encode operations that will never be used at the same time

CS152Lec11.22

1) Start with list of control signalsSignal name Effect when deasserted Effect when asserted

ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWr None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRd None Memory at address is read, MemWr None Memory at address is written IorD Memory address = PC Memory address = SIRWr None IR <= MemoryPCWr None PC <= PCSourcePCWrCond None IF ALUzero then PC <= PCSourcePCSrc PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended

Sing

le B

it C

ontr

ol

Signal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code

11 ALU does logical OR ALUSelB 00 2nd ALU input = 4 01 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extended

Mul

tiple

Bit

Con

trol

CS152Lec11.23

2) Group into fields of unrelated signals

° Miminizes Hardware: 1 memory, 1 adder

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instruction Reg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mux

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mux

0

1

32

PC

MemtoReg

Extend

ExtOp

Mux

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mux

1

0

32

Zero

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A

ALU

SRC1

SRC2

MemRd

PCWrite

CS152Lec11.24

2,3 & 4 ) Group into fields, order and assign names

Field Name Values for Field Function of Field with Specific ValueALU Add ALU adds

Subt. ALU subtractsFunc ALU does function codeOr ALU does logical OR

SRC1 PC 1st ALU input <= PCrs 1st ALU input <= Reg[rs]

SRC2 4 2nd ALU input <= 4Extend 2nd ALU input <= sign ext. IR[15-0]Extend0 2nd ALU input <= zero ext. IR[15-0] Extshft 2nd ALU input <= sign ex., sl IR[15-0]rt 2nd ALU input <= Reg[rt]

dest(ination) rd ALU Reg[rd] <= ALUout rt ALU Reg[rt] <= ALUout

rt Mem Reg[rt] <= Mem Mem(ory) Read PC Read memory using PC

Read ALU Read memory using ALUout for addrWrite ALU Write memory using ALUout for addr

Memreg IR IR <= MemPCwrite PCwr PC <= PCSource

PCSrc IF Zero then PCSource <= ALUout else ALUPCWrCond IF Zero then PC <= PCSource

Seq(uencing) Seq Go to sequential µinstructionFetch Go to the first microinstructionDispatch Dispatch using ROM.

ALU SRC1

SRC2

Dest Mem Memreg PCwrite Seq

CS152Lec11.25

5) Encode each field

Field Name Width Control Signals Setwide narrow

ALU 4 2ALUOpSRC1 2 1ALUSelASRC2 5 3ALUSelB, ExtOpDest 3 2RegWrite, MemtoReg, RegDstMem 3 2MemRd, MemWre, IorDMemreg 1 1IRWritePCWrite 3 1PCWr, PCSrc, PCWrCondSeq 3 2AddrCtlTotal width 24 14bits

CS152Lec11.26

5) Encode each field (cont.)

Code Name RegWrite MemToReg RegDest00 --- 0 X X01rd ALU 1 0 110rt ALU 1 0 011rt MEM 1 1 0

Code Name ALUSelB ExtOp000 --- X X001 4 00 X010 rt 01 X011 ExtShft 10 1100 Extend 11 1111 Extend0 11 0

Dest:

SRC2:

CS152Lec11.27

Finally – Do the microprogram….

Label ALU SRC1 SRC2 Dest. Memory MemReg. PCWrite SeqFetch: Add PC 4 Read PC IR PCwr Seq

Add PC Extshft Dispatch

Rtype: Func rs rt Seqrd ALU Fetch

Ori: Or rs Extend0 Seqrt ALU Fetch

Lw: Add rs Extend SeqRead ALU Seq

rt MEM Fetch

Sw: Add rs Extend SeqWrite ALU Fetch

Beq: Subt. rs rt PCWrCond. Fetch

0000 0001

01000101

01100111

100010011010

10111100

0010

CS152Lec11.28

Microprogramming Pros and Cons° Ease of design° Flexibility

• Easy to adapt to changes in organization, timing, technology• Can make changes late in design cycle, or even in the field

° Can implement very powerful instruction sets (just more control memory)

° Generality• Can implement multiple instruction sets on same machine.• Can tailor instruction set to application.

° Compatibility• Many organizations, same instruction set

° Costly to implement° Slow

CS152Lec11.29

Adding a more complex memory model

PC

InstructionMemory

Inst. Reg

addr

data

IR_en

InstMem_rd

IM_wait

Add a wait flag of indeterminate length – IM_wait(due to caching)

CS152Lec11.30

Controller handles non-ideal memory

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= B

BEQPC <=

Next(PC)

SW

“instruction fetch”

“decode / operand fetch”

Exe

cute

Mem

ory

Writ

e-ba

ck

~IMwait IMwait

~wait wait

PC <= PC + 4

~wait wait

CS152Lec11.31

Really Simple Time-State Control

inst

ruct

ion

fetc

hde

code

Exe

cute

Mem

ory

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= B

BEQ

PC <= Next(PC)

SW

~IMwait IMwait

wait

PC <= PC + 4

wait

writ

e-ba

ck

CS152Lec11.32

Time-state Control Path

° Local decode and control at each stage

Exe

c

Reg

. Fi

le

Mem

Acc

ess

Dat

aM

em

A

B

S

M

Reg

File

Equ

al

PC

Nex

t PC

IR

Inst

. Mem

Valid

IRex

Dcd

Ctrl

IRm

em

Ex

Ctrl

IRw

b

Mem

Ctrl

WB

Ctrl

CS152Lec11.33

Overview of Control° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.

Initial Representation Finite State Diagram Microprogram

Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs

Logic Representation Logic Equations Truth Tables

Implementation PLA ROM Technique

“hardwired control” “microprogrammed control”

CS152Lec11.34

Summary° Specialize state-diagrams easily captured by

microsequencer• simple increment & “branch” fields

• datapath control fields

° Most microprogramming-based controllers vary between:• horizontal organization (1 control bit per control point)

• vertical organization (fields encoded in the control memory and must be decoded to control something)

° Steps: • identify control signals, group them, develop “mini language”, then

microprogram

° Control design reduces to Microprogramming • Arbitrarily complicated instructions possible

CS152Lec11.35

Summary: Microprogramming one inspiration for RISC

° If simple instruction could execute at very high clock rate…

° If you could even write compilers to produce microinstructions…

° If most programs use simple instructions and addressing modes…

° If microcode is kept in RAM instead of ROM so as to fix bugs …

° If same memory used for control memory could be used instead as cache for “macroinstructions”…

° Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine?