the bubblewrap many-core

http://iacoma.cs.uiuc.edu/

Universityof Illinois

The BubbleWrap Many-Core:Popping Cores for Sequential Acceleration

Ulya Karpuzcu, Brian Greskamp, Josep TorrellasUniversity of Illinois

http://iacoma.cs.uiuc.edu


Ulya Karpuzcu The BubbleWrap Many-Core

Problem: The Power Wall

2



2

Ideal Scaling



• Dynamic (switching) power density remains constant

2

Ideal Scaling




2

Ideal Scaling

PDYN = #Devices x




2

Ideal Scaling

Frequency of switchingPDYN = #Devices x x




2

Ideal Scaling

Frequency of switchingPDYN = #Devices Energy per switchingx x


∝Vdd2



2

Ideal Scaling



∝Vdd2



2

Ideal Scaling

Practical Scaling• Vdd has been scaling down slower than ideally



∝Vdd2



2

Ideal Scaling


• Historically: Higher Vdd ≡ Higher performance



∝Vdd2



2

Ideal Scaling



• Recently: Practically stagnated Vth scaling to control static power



∝Vdd2



2

Ideal Scaling



• Recently: Practically stagnated Vth scaling to control static power

Dynamic Power Density is increasing



The Power Wall

3


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

2008 2013 2018 20220

5

10

15

20

25

The Power Wall

3

ITRS 2008


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

2008 2013 2018 20220

5

10

15

20

25

The Power Wall

3

Total

ITRS 2008


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

2008 2013 2018 20220

5

10

15

20

25

The Power Wall

3

TotalPowered-on for 100W

ITRS 2008


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

The Power Wall

4

TotalPowered on for 100W

ITRS 2008

0

5

10

15

20

25

2008 2013 2018 2022

Active CoresDormant Cores


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

The Power Wall

4


ITRS 2008

0

5

10

15

20

25

2008 2013 2018 2022


In 9 years


Num

ber o

f Cor

es p

er C

hip

Nor

mal

ized

to 2

008

The Power Wall

4


ITRS 2008

0

5

10

15

20

25

2008 2013 2018 2022


Only ~25% of coresactive at any time

In 9 years


The BubbleWrap Many-Core

5



5

• Exploit dormant cores to accelerate sequential sections at the cost of a shorter per-core service life



5

• Base: A homogeneous many-core




5


• Throughput Cores




5



• Most energy-efficient cores




5




• Run parallel sections




5





• Operate at nominal V/f


Nom

inal

V/f



5






• Expendable Cores


Nom

inal

V/f



5







• Run sequential sections


Nom

inal

V/f



5








• Operate at elevated V/f


Nom

inal

V/f

Hig

h V/

f



5








• Operate at elevated V/f

• Discarded early due to shorter service life (Popped like BubbleWrap)


Nom

inal

V/f

Hig

h V/

f


Core Aging

6


Core Aging

• Manifestation: Progressive slow-down in logic as the core is being used

6


Core Aging


• Main contributor: Bias Temperature Instability (BTI)

6


Core Aging



• Induces increase in critical path delays ∝ timeconst.<1

6


Core Aging



• Induces increase in critical path delays ∝ timeconst.<1

• Aging rate: Exponential dependence on Vdd and T

6


τ0

Aging-induced Degradation

7

Crit

ical

Pat

h De

lay

VddNOM

SNOM0time

Vdd

0 SNOM time


τ0


7

Crit

ical

Pat

h De

lay

VddNOM

SNOM0time

Vdd

0 SNOM

• BTI-induced increase in critical path delays ∝ timeconst.<1

time


τ0


7

Crit

ical

Pat

h De

lay

VddNOM

SNOM0time

Vdd

0 SNOM


• fNOM set by the delay at the end of the service-life (SNOM)

fNOM = 1/τD

time

τD

fNOM


τ0


7

Crit

ical

Pat

h De

lay

VddNOM

SNOM0time

Vdd

0 SNOM


• fNOM set by the delay at the end of the service-life (SNOM)

fNOM = 1/τD

time

τD

Wasted Opportunity: Guardband

fNOM


Impact of Operation at Higher V/f on Aging

8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM

VddNOM



8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM SSHORTSSHORT

VddNOM



8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM SSHORTSSHORT

VddOP

• Higher Vdd: VddOP >> VddNOM

VddNOM



8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM SSHORTSSHORT

VddOP


• Result: Lower critical path delay; higher aging rate

VddNOM



8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM SSHORTSSHORT

VddOP τOP



• Run at constant fOP = 1/τOP until SSHORT; then discard

VddNOM fOP



8

time

Crit

ical

Pat

h De

lay

SNOM0time

Vdd

0 SNOM SSHORTSSHORT

VddOP τOP



• Run at constant fOP = 1/τOP until SSHORT; then discard

VddNOM fOP

Wasted Opportunity


How to Manage Aging Optimally?

9

Wasted Opportunity

τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD



9

Wasted Opportunity

Contribution: DVS for Aging Management (DVSAM)

τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD



9

Wasted Opportunity

• Change Vdd with time to compensate for critical path degradation


τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD



9

Wasted Opportunity


• Enforce minimum Vdd needed for any f-target


τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD



9

Wasted Opportunity

• DVSAM-Pow: Turn wasted opportunity to power efficiency




τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD



9

Wasted Opportunity

• DVSAM-Pow: Turn wasted opportunity to power efficiency

• DVSAM-Perf: Turn wasted opportunity to higher frequency




τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τD

fNOM=1/τD

Ulya Karpuzcu The BubbleWrap Many-Core 10

DVSAM-Pow


DVSAM-PowIdea: Minimize power consumption at fNOM = 1/τD



τ0

time

Crit

ical

Pat

h De

lay

SNOM0

VddNOM

time

Vdd

0 SNOM



τ0

time

Crit

ical

Pat

h De

lay

SNOM0

VddNOM

time

Vdd

0 SNOM

• Critical path delays are kept at τD until SNOM: Run at fNOM



τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τDVddNOM

time

Vdd

0 SNOM




τ0

time

Crit

ical

Pat

h De

lay

SNOM0

τDVddNOM

time

Vdd

0 SNOM

VddOP


• Start with low Vdd and increase slowly


DVSAM-Pow


• Vdd < VddNOM and f = fNOM throughout SNOM

DVSAM-Pow



• Power savings due to Vdd < VddNOM

DVSAM-Pow




➡ More cores active for the same P-budget

DVSAM-Pow




➡ More cores active for the same P-budget➡ Increased throughput

DVSAM-Pow


DVSAM-Perf


DVSAM-PerfIdea: Maximize frequency for the same service life



time

Crit

ical

Pat

h De

lay

SNOM0

τDVddNOM

time

Vdd

0 SNOM

τ0



τOP

time

Crit

ical

Pat

h De

lay

SNOM0

τDVddNOM

time

Vdd

0 SNOM

• Shorter critical path delay τOP until SNOM: Run at higher f = 1 / τOP

τ0



τOP

time

Crit

ical

Pat

h De

lay

SNOM0

τDVddOP

VddNOM

time

Vdd

0 SNOM

• Shorter critical path delay τOP until SNOM: Run at higher f = 1 / τOP

• Start with low Vdd and increase rapidly

τ0


DVSAM-Perf for SSHORT



Idea: Aggressive DVSAM-Perf for a short service life to get even higher performance


τOP

time

Crit

ical

Pat

h De

lay

SNOM0

VddOP

timeVd

d0 SNOM




τOP

time

Crit

ical

Pat

h De

lay

SNOM0

VddOP

timeVd

d0 SNOM



SSHORT SSHORT


τOP

time

Crit

ical

Pat

h De

lay

SNOM0

VddOP

timeVd

d0 SNOM



SSHORT SSHORT

τSH


τOP

time

Crit

ical

Pat

h De

lay

SNOM0

VddOP

timeVd

d0 SNOM



SSHORT SSHORT

τSH

VddSH


τOP

time

Crit

ical

Pat

h De

lay

SNOM0

VddOP

timeVd

d0 SNOM



SSHORT SSHORT

τSH

VddSH

• Even higher frequency than DVSAM-Perf for short service life

fSSHORT

fSNOM


BubbleWrap Environments

14

Throughput Cores

Expendable Cores



14

• Two choices for Throughput CoresThroughput Cores

Expendable Cores



14

• Two choices for Throughput Cores

• Nominal operationThroughput Cores

Expendable Cores



14


• Nominal operation

• Use DVSAM-Pow and expand the set of throughout cores for the same power budget

Throughput Cores

Expendable Cores



14




Throughput Cores

Expendable Cores

• Two choices for Expendable Cores



14




Throughput Cores

Expendable Cores


• Higher, constant Vdd until SSHORT; then discard



14




Throughput Cores

Expendable Cores


• Higher, constant Vdd until SSHORT; then discard

• DVSAM-Perf until SSHORT; then discard


Hardware Support?

15


Hardware Support?• No change in the core architecture

15



• Need circuits to measure aging

15




• Need high-precision DVS

15





• Clock and power distribution

15





• Clock and power distribution• Two separate V/f domains: One for Expendable and one for

Throughput Cores

15


BubbleWrap Evaluation

16


BubbleWrap Evaluation• 32 core chip: NT = 16 Throughput and NE = 16 Expendable cores

16



• 22nm high-k metal-gate process

16




• Multiprogrammed workload synthesized from SPEC2000

16




• Multiprogrammed workload synthesized from SPEC2000

• SESC enhanced by a power & thermal model

16


Frequency Gains of Sequential Section

17



17

1 0.8 0.6 0.4 0.20.90

0.95

1.00

1.05

1.10

1.15

1.20

Nor

mal

ized

Freq

uenc

y G

ain

Sequential Fraction (LSEQ)



17

Base

1 0.8 0.6 0.4 0.20.90

0.95

1.00

1.05

1.10

1.15

1.20

Nor

mal

ized

Freq

uenc

y G

ain




18

Base DVSAM-Perf for SSHORT

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1 0.8 0.6 0.4 0.2Nor

mal

ized

Freq

uenc

y G

ain




18

• Large f gains are feasible


0.90

0.95

1.00

1.05

1.10

1.15

1.20

1 0.8 0.6 0.4 0.2Nor

mal

ized

Freq

uenc

y G

ain




18

• Large f gains are feasible• f increases with smaller sequential section


0.90

0.95

1.00

1.05

1.10

1.15

1.20

1 0.8 0.6 0.4 0.2Nor

mal

ized

Freq

uenc

y G

ain




18

• Large f gains are feasible• f increases with smaller sequential section• For DVSAM-Perf, each expendable core runs for LSEQ/NE x SNOM


0.90

0.95

1.00

1.05

1.10

1.15

1.20

1 0.8 0.6 0.4 0.2Nor

mal

ized

Freq

uenc

y G

ain



Power Consumption of Sequential Section

19



19

• Each Expendable core has max P budget of two cores


1 0.8 0.6 0.4 0.2 00

0.5

1.0

1.5

2.0

Nor

mal

ized

Pow

er C

onsu

mpt

ion



19



1 0.8 0.6 0.4 0.2 00

0.5

1.0

1.5

2.0

Nor

mal

ized

Pow

er C

onsu

mpt

ion



19


Base


0

0.5

1.0

1.5

2.0

1 0.8 0.6 0.4 0.2 0

Nor

mal

ized

Pow

er C

onsu

mpt

ion



20




0

0.5

1.0

1.5

2.0

1 0.8 0.6 0.4 0.2 0

Nor

mal

ized

Pow

er C

onsu

mpt

ion



20


• Tolerable power cost for the frequency gains



Conclusion

21

The BubbleWrap Many-Core: Exploiting dormant cores for sequential acceleration


Conclusion

• Simple homogeneous design

21



Conclusion


• No architectural or software changes

21



Conclusion



• Improves sequential and parallel performance

21



Conclusion




• Fully sequential applications at 16% higher f

21



Conclusion




• Fully sequential applications at 16% higher f

• Fully parallel applications at 30% higher throughput

21


http://iacoma.cs.uiuc.edu/

Universityof Illinois

The BubbleWrap Many-Core:Popping Cores for Sequential Acceleration

Ulya Karpuzcu, Brian Greskamp, Josep TorrellasUniversity of Illinois



the bubblewrap many-core

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